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bassofono/codice/build/stm32g4xx_hal_rcc_ex.lst

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1 .cpu cortex-m4
2 .eabi_attribute 27, 1
3 .eabi_attribute 28, 1
4 .eabi_attribute 23, 1
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 2
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32g4xx_hal_rcc_ex.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits
16 .align 1
17 .p2align 2,,3
18 .global HAL_RCCEx_PeriphCLKConfig
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu fpv4-sp-d16
24 HAL_RCCEx_PeriphCLKConfig:
25 .LFB329:
26 .file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c"
1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ******************************************************************************
3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @file stm32g4xx_hal_rcc_ex.c
4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @author MCD Application Team
5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Extended RCC HAL module driver.
6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * functionalities RCC extended peripheral:
8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * + Extended Peripheral Control functions
9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * + Extended Clock management functions
10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * + Extended Clock Recovery System Control functions
11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ******************************************************************************
13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @attention
14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * All rights reserved.</center></h2>
17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * This software component is licensed by ST under BSD 3-Clause license,
19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * the "License"; You may not use this file except in compliance with the
20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * License. You may obtain a copy of the License at:
21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * opensource.org/licenses/BSD-3-Clause
22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ******************************************************************************
24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/
27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #include "stm32g4xx_hal.h"
28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
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33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx
34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief RCC Extended HAL module driver
35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED
39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/
41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private defines -----------------------------------------------------------*/
42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define DIVIDER_P_UPDATE 0U
48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define DIVIDER_Q_UPDATE 1U
49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define DIVIDER_R_UPDATE 2U
50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define LSCO_GPIO_PORT GPIOA
53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #define LSCO_PIN GPIO_PIN_2
54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @}
56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private macros ------------------------------------------------------------*/
59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/
60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/
61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @}
67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Exported functions --------------------------------------------------------*/
70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions
77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @verbatim
79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ===============================================================================
80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ##### Extended Peripheral Control functions #####
81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ===============================================================================
82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** [..]
83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the RCC Clocks
84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequencies.
85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** [..]
86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** select the RTC clock source; in this case the Backup domain will be reset in
88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** order to modify the RTC Clock source, as consequence RTC registers (including
89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** the backup registers) are set to their reset values.
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90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @endverbatim
92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Initialize the RCC extended peripherals clocks according to the specified
96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * parameters in the RCC_PeriphCLKInitTypeDef.
97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * contains a field PeriphClockSelection which can be a combination of the following value
99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN)
114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devic
118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_QSPI QuadSPI peripheral clock (only for devices with QuadSP
119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * the RTC clock source: in this case the access to Backup domain is enabled.
122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval HAL status
124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
27 .loc 1 126 0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 8
30 @ frame_needed = 0, uses_anonymous_args = 0
31 .LVL0:
32 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr}
33 .LCFI0:
34 .cfi_def_cfa_offset 24
35 .cfi_offset 4, -24
36 .cfi_offset 5, -20
37 .cfi_offset 6, -16
38 .cfi_offset 7, -12
39 .cfi_offset 8, -8
40 .cfi_offset 14, -4
127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t tmpregister;
128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t tickstart;
129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; /* Final status */
131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
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133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- RTC clock source configuration ----------------------*/
136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
41 .loc 1 136 0
42 0004 0368 ldr r3, [r0]
126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t tmpregister;
43 .loc 1 126 0
44 0006 0446 mov r4, r0
45 .loc 1 136 0
46 0008 13F40020 ands r0, r3, #524288
47 .LVL1:
126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t tmpregister;
48 .loc 1 126 0
49 000c 82B0 sub sp, sp, #8
50 .LCFI1:
51 .cfi_def_cfa_offset 32
52 .loc 1 136 0
53 000e 57D0 beq .L2
54 .LVL2:
55 .LBB2:
137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET;
139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check for RTC Parameters used to output RTCCLK */
141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable Power Clock */
144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED())
56 .loc 1 144 0
57 0010 9F4B ldr r3, .L87
58 0012 9A6D ldr r2, [r3, #88]
59 0014 D000 lsls r0, r2, #3
60 0016 40F10D81 bpl .L80
138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
61 .loc 1 138 0
62 001a 0027 movs r7, #0
63 .LVL3:
64 .L3:
145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE();
147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pwrclkchanged = SET;
148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */
151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP);
65 .loc 1 151 0
66 001c 9D4D ldr r5, .L87+4
67 001e 2B68 ldr r3, [r5]
68 0020 43F48073 orr r3, r3, #256
69 0024 2B60 str r3, [r5]
152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */
154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** tickstart = HAL_GetTick();
70 .loc 1 154 0
71 0026 FFF7FEFF bl HAL_GetTick
72 .LVL4:
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 5
aggiunta cod
2021-07-02 22:19:04 +02:00
73 002a 0646 mov r6, r0
74 .LVL5:
155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** while((PWR->CR1 & PWR_CR1_DBP) == 0U)
75 .loc 1 156 0
76 002c 05E0 b .L4
77 .LVL6:
78 .L6:
157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
79 .loc 1 158 0
80 002e FFF7FEFF bl HAL_GetTick
81 .LVL7:
82 0032 801B subs r0, r0, r6
83 0034 0228 cmp r0, #2
84 0036 00F20F81 bhi .L10
85 .L4:
156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
86 .loc 1 156 0
87 003a 2B68 ldr r3, [r5]
88 003c D905 lsls r1, r3, #23
89 003e F6D5 bpl .L6
159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ret = HAL_TIMEOUT;
161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(ret == HAL_OK)
166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
90 .loc 1 168 0
91 0040 934B ldr r3, .L87
92 0042 216C ldr r1, [r4, #64]
93 0044 D3F89020 ldr r2, [r3, #144]
94 .LVL8:
169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection
95 .loc 1 170 0
96 0048 12F44072 ands r2, r2, #768
97 .LVL9:
98 004c 28D0 beq .L8
99 .loc 1 170 0 is_stmt 0 discriminator 1
100 004e 8A42 cmp r2, r1
101 0050 26D0 beq .L8
171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Store the content of BDCR register before the reset of Backup Domain */
173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
102 .loc 1 173 0 is_stmt 1
103 0052 D3F89000 ldr r0, [r3, #144]
174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */
175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE();
104 .loc 1 175 0
105 0056 D3F89020 ldr r2, [r3, #144]
106 .LVL10:
107 005a 42F48032 orr r2, r2, #65536
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 6
aggiunta cod
2021-07-02 22:19:04 +02:00
108 005e C3F89020 str r2, [r3, #144]
176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE();
109 .loc 1 176 0
110 0062 D3F89020 ldr r2, [r3, #144]
111 0066 22F48032 bic r2, r2, #65536
112 006a C3F89020 str r2, [r3, #144]
173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */
113 .loc 1 173 0
114 006e 20F44075 bic r5, r0, #768
115 .LVL11:
177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */
178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC->BDCR = tmpregister;
179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
116 .loc 1 182 0
117 0072 C207 lsls r2, r0, #31
178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
118 .loc 1 178 0
119 0074 C3F89050 str r5, [r3, #144]
120 .LVL12:
121 .loc 1 182 0
122 0078 12D5 bpl .L8
183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get Start Tick*/
185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** tickstart = HAL_GetTick();
186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Wait till LSE is ready */
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
123 .loc 1 188 0
124 007a 1D46 mov r5, r3
185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
125 .loc 1 185 0
126 007c FFF7FEFF bl HAL_GetTick
127 .LVL13:
189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
128 .loc 1 190 0
129 0080 41F28836 movw r6, #5000
130 .LVL14:
185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
131 .loc 1 185 0
132 0084 8046 mov r8, r0
133 .LVL15:
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
134 .loc 1 188 0
135 0086 06E0 b .L9
136 .LVL16:
137 .L11:
138 .loc 1 190 0
139 0088 FFF7FEFF bl HAL_GetTick
140 .LVL17:
141 008c A0EB0800 sub r0, r0, r8
142 0090 B042 cmp r0, r6
143 0092 00F2E180 bhi .L10
144 .L9:
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 7
aggiunta cod
2021-07-02 22:19:04 +02:00
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
145 .loc 1 188 0
146 0096 D5F89030 ldr r3, [r5, #144]
147 009a 9B07 lsls r3, r3, #30
148 009c F4D5 bpl .L11
149 009e 216C ldr r1, [r4, #64]
150 .LVL18:
151 .L8:
191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ret = HAL_TIMEOUT;
193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(ret == HAL_OK)
199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Apply new RTC clock source selection */
201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
152 .loc 1 201 0
153 00a0 7B4A ldr r2, .L87
154 00a2 D2F89030 ldr r3, [r2, #144]
155 00a6 23F44073 bic r3, r3, #768
156 00aa 0B43 orrs r3, r3, r1
157 00ac C2F89030 str r3, [r2, #144]
158 .LBE2:
130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
159 .loc 1 130 0
160 00b0 0020 movs r0, #0
161 .L5:
162 .LVL19:
163 .LBB4:
202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* set overall return value */
206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** status = ret;
207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* set overall return value */
212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** status = ret;
213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Restore clock configuration if changed */
216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(pwrclkchanged == SET)
164 .loc 1 216 0
165 00b2 27B1 cbz r7, .L78
217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE();
166 .loc 1 218 0
167 00b4 764A ldr r2, .L87
168 00b6 936D ldr r3, [r2, #88]
169 00b8 23F08053 bic r3, r3, #268435456
170 00bc 9365 str r3, [r2, #88]
171 .L78:
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 8
aggiunta cod
2021-07-02 22:19:04 +02:00
172 00be 2368 ldr r3, [r4]
173 .LVL20:
174 .L2:
175 .LBE4:
219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- USART1 clock source configuration -------------------*/
223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
176 .loc 1 223 0
177 00c0 DE07 lsls r6, r3, #31
178 00c2 08D5 bpl .L13
224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the USART1 clock source */
229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
179 .loc 1 229 0
180 00c4 7249 ldr r1, .L87
181 00c6 6568 ldr r5, [r4, #4]
182 00c8 D1F88820 ldr r2, [r1, #136]
183 00cc 22F00302 bic r2, r2, #3
184 00d0 2A43 orrs r2, r2, r5
185 00d2 C1F88820 str r2, [r1, #136]
186 .L13:
230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- USART2 clock source configuration -------------------*/
233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
187 .loc 1 233 0
188 00d6 9D07 lsls r5, r3, #30
189 00d8 08D5 bpl .L14
234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the USART2 clock source */
239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
190 .loc 1 239 0
191 00da 6D49 ldr r1, .L87
192 00dc A568 ldr r5, [r4, #8]
193 00de D1F88820 ldr r2, [r1, #136]
194 00e2 22F00C02 bic r2, r2, #12
195 00e6 2A43 orrs r2, r2, r5
196 00e8 C1F88820 str r2, [r1, #136]
197 .L14:
240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- USART3 clock source configuration -------------------*/
243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
198 .loc 1 243 0
199 00ec 5907 lsls r1, r3, #29
200 00ee 08D5 bpl .L15
244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 9
aggiunta cod
2021-07-02 22:19:04 +02:00
247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the USART3 clock source */
249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
201 .loc 1 249 0
202 00f0 6749 ldr r1, .L87
203 00f2 E568 ldr r5, [r4, #12]
204 00f4 D1F88820 ldr r2, [r1, #136]
205 00f8 22F03002 bic r2, r2, #48
206 00fc 2A43 orrs r2, r2, r5
207 00fe C1F88820 str r2, [r1, #136]
208 .L15:
250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART4)
253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- UART4 clock source configuration --------------------*/
254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
209 .loc 1 254 0
210 0102 1A07 lsls r2, r3, #28
211 0104 08D5 bpl .L16
255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the UART4 clock source */
260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
212 .loc 1 260 0
213 0106 6249 ldr r1, .L87
214 0108 2569 ldr r5, [r4, #16]
215 010a D1F88820 ldr r2, [r1, #136]
216 010e 22F0C002 bic r2, r2, #192
217 0112 2A43 orrs r2, r2, r5
218 0114 C1F88820 str r2, [r1, #136]
219 .L16:
261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART4 */
263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART5)
265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- UART5 clock source configuration --------------------*/
267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the UART5 clock source */
273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART5 */
277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- LPUART1 clock source configuration ------------------*/
279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
220 .loc 1 279 0
221 0118 9F06 lsls r7, r3, #26
222 011a 08D5 bpl .L17
280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
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ARM GAS /tmp/ccZxUtAY.s page 10
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282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the LPUAR1 clock source */
285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
223 .loc 1 285 0
224 011c 5C49 ldr r1, .L87
225 011e 6569 ldr r5, [r4, #20]
226 0120 D1F88820 ldr r2, [r1, #136]
227 0124 22F44062 bic r2, r2, #3072
228 0128 2A43 orrs r2, r2, r5
229 012a C1F88820 str r2, [r1, #136]
230 .L17:
286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- I2C1 clock source configuration ---------------------*/
289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
231 .loc 1 289 0
232 012e 5E06 lsls r6, r3, #25
233 0130 08D5 bpl .L18
290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the I2C1 clock source */
295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
234 .loc 1 295 0
235 0132 5749 ldr r1, .L87
236 0134 A569 ldr r5, [r4, #24]
237 0136 D1F88820 ldr r2, [r1, #136]
238 013a 22F44052 bic r2, r2, #12288
239 013e 2A43 orrs r2, r2, r5
240 0140 C1F88820 str r2, [r1, #136]
241 .L18:
296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- I2C2 clock source configuration ---------------------*/
299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
242 .loc 1 299 0
243 0144 1D06 lsls r5, r3, #24
244 0146 08D5 bpl .L19
300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the I2C2 clock source */
305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
245 .loc 1 305 0
246 0148 5149 ldr r1, .L87
247 014a E569 ldr r5, [r4, #28]
248 014c D1F88820 ldr r2, [r1, #136]
249 0150 22F44042 bic r2, r2, #49152
250 0154 2A43 orrs r2, r2, r5
251 0156 C1F88820 str r2, [r1, #136]
252 .L19:
306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- I2C3 clock source configuration ---------------------*/
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ARM GAS /tmp/ccZxUtAY.s page 11
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309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
253 .loc 1 309 0
254 015a D905 lsls r1, r3, #23
255 015c 08D5 bpl .L20
310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the I2C3 clock source */
315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
256 .loc 1 315 0
257 015e 4C49 ldr r1, .L87
258 0160 256A ldr r5, [r4, #32]
259 0162 D1F88820 ldr r2, [r1, #136]
260 0166 22F44032 bic r2, r2, #196608
261 016a 2A43 orrs r2, r2, r5
262 016c C1F88820 str r2, [r1, #136]
263 .L20:
316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(I2C4)
319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- I2C4 clock source configuration ---------------------*/
321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the I2C4 clock source */
327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* I2C4 */
331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- LPTIM1 clock source configuration ---------------------*/
333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
264 .loc 1 333 0
265 0170 9A05 lsls r2, r3, #22
266 0172 08D5 bpl .L21
334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the LPTIM1 clock source */
339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
267 .loc 1 339 0
268 0174 4649 ldr r1, .L87
269 0176 656A ldr r5, [r4, #36]
270 0178 D1F88820 ldr r2, [r1, #136]
271 017c 22F44022 bic r2, r2, #786432
272 0180 2A43 orrs r2, r2, r5
273 0182 C1F88820 str r2, [r1, #136]
274 .L21:
340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- SAI1 clock source configuration ---------------------*/
343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 12
aggiunta cod
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275 .loc 1 343 0
276 0186 5F05 lsls r7, r3, #21
277 0188 0BD5 bpl .L23
344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the SAI1 interface clock source */
349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
278 .loc 1 349 0
279 018a 4149 ldr r1, .L87
280 018c A56A ldr r5, [r4, #40]
281 018e D1F88820 ldr r2, [r1, #136]
282 0192 22F44012 bic r2, r2, #3145728
283 0196 2A43 orrs r2, r2, r5
350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
284 .loc 1 351 0
285 0198 B5F5801F cmp r5, #1048576
349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
286 .loc 1 349 0
287 019c C1F88820 str r2, [r1, #136]
288 .loc 1 351 0
289 01a0 5CD0 beq .L81
290 .L23:
352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLL48M1CLK output */
354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- I2S clock source configuration ---------------------*/
359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
291 .loc 1 359 0
292 01a2 1E05 lsls r6, r3, #20
293 01a4 0BD5 bpl .L26
360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the I2S interface clock source */
365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
294 .loc 1 365 0
295 01a6 3A49 ldr r1, .L87
296 01a8 E56A ldr r5, [r4, #44]
297 01aa D1F88820 ldr r2, [r1, #136]
298 01ae 22F44002 bic r2, r2, #12582912
299 01b2 2A43 orrs r2, r2, r5
366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
300 .loc 1 367 0
301 01b4 B5F5800F cmp r5, #4194304
365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
302 .loc 1 365 0
303 01b8 C1F88820 str r2, [r1, #136]
304 .loc 1 367 0
305 01bc 53D0 beq .L82
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 13
aggiunta cod
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306 .L26:
368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLL48M1CLK output */
370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(FDCAN1)
375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- FDCAN clock source configuration ---------------------*/
376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
307 .loc 1 376 0
308 01be DD04 lsls r5, r3, #19
309 01c0 0BD5 bpl .L29
377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the FDCAN interface clock source */
382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
310 .loc 1 382 0
311 01c2 3349 ldr r1, .L87
312 01c4 256B ldr r5, [r4, #48]
313 01c6 D1F88820 ldr r2, [r1, #136]
314 01ca 22F04072 bic r2, r2, #50331648
315 01ce 2A43 orrs r2, r2, r5
383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
316 .loc 1 384 0
317 01d0 B5F1807F cmp r5, #16777216
382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
318 .loc 1 382 0
319 01d4 C1F88820 str r2, [r1, #136]
320 .loc 1 384 0
321 01d8 4AD0 beq .L83
322 .L29:
385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLL48M1CLK output */
387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* FDCAN1 */
391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(USB)
393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- USB clock source configuration ----------------------*/
395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
323 .loc 1 395 0
324 01da 9904 lsls r1, r3, #18
325 01dc 0BD5 bpl .L32
396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
326 .loc 1 398 0
327 01de 2C49 ldr r1, .L87
328 01e0 656B ldr r5, [r4, #52]
329 01e2 D1F88820 ldr r2, [r1, #136]
330 01e6 22F04062 bic r2, r2, #201326592
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 14
aggiunta cod
2021-07-02 22:19:04 +02:00
331 01ea 2A43 orrs r2, r2, r5
399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
332 .loc 1 400 0
333 01ec B5F1006F cmp r5, #134217728
398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
334 .loc 1 398 0
335 01f0 C1F88820 str r2, [r1, #136]
336 .loc 1 400 0
337 01f4 41D0 beq .L84
338 .L32:
401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLL48M1CLK output */
403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* USB */
408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- RNG clock source configuration ----------------------*/
410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
339 .loc 1 410 0
340 01f6 5A04 lsls r2, r3, #17
341 01f8 0BD5 bpl .L35
411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
342 .loc 1 413 0
343 01fa 2549 ldr r1, .L87
344 01fc A56B ldr r5, [r4, #56]
345 01fe D1F88820 ldr r2, [r1, #136]
346 0202 22F04062 bic r2, r2, #201326592
347 0206 2A43 orrs r2, r2, r5
414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
348 .loc 1 415 0
349 0208 B5F1006F cmp r5, #134217728
413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
350 .loc 1 413 0
351 020c C1F88820 str r2, [r1, #136]
352 .loc 1 415 0
353 0210 38D0 beq .L85
354 .L35:
416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLL48M1CLK output */
418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- ADC12 clock source configuration ----------------------*/
423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
355 .loc 1 423 0
356 0212 1B04 lsls r3, r3, #16
357 0214 0BD5 bpl .L44
424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
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427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the ADC12 interface clock source */
429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
358 .loc 1 429 0
359 0216 1E4A ldr r2, .L87
360 0218 E16B ldr r1, [r4, #60]
361 021a D2F88830 ldr r3, [r2, #136]
362 021e 23F04053 bic r3, r3, #805306368
363 0222 0B43 orrs r3, r3, r1
430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
364 .loc 1 431 0
365 0224 B1F1805F cmp r1, #268435456
429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
366 .loc 1 429 0
367 0228 C2F88830 str r3, [r2, #136]
368 .loc 1 431 0
369 022c 0DD0 beq .L86
370 .L44:
432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLLADCCLK output */
434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(ADC345_COMMON)
439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- ADC345 clock source configuration ----------------------*/
440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345)
441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the ADC345 interface clock source */
446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL)
449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLLADCCLK output */
451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* ADC345_COMMON */
455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(QUADSPI)
457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /*-------------------------- QuadSPIx clock source configuration ----------------*/
459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the QuadSPI clock source */
465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL)
468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable PLL48M1CLK output */
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470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* QUADSPI */
475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** return status;
477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
371 .loc 1 477 0
372 022e 02B0 add sp, sp, #8
373 .LCFI2:
374 .cfi_remember_state
375 .cfi_def_cfa_offset 24
376 @ sp needed
377 0230 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
378 .LVL21:
379 .L80:
380 .LCFI3:
381 .cfi_restore_state
382 .LBB5:
383 .LBB3:
146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pwrclkchanged = SET;
384 .loc 1 146 0
385 0234 9A6D ldr r2, [r3, #88]
386 0236 42F08052 orr r2, r2, #268435456
387 023a 9A65 str r2, [r3, #88]
388 023c 9B6D ldr r3, [r3, #88]
389 023e 03F08053 and r3, r3, #268435456
390 0242 0193 str r3, [sp, #4]
391 0244 019B ldr r3, [sp, #4]
392 .LVL22:
393 .LBE3:
147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
394 .loc 1 147 0
395 0246 0127 movs r7, #1
396 0248 E8E6 b .L3
397 .LVL23:
398 .L86:
399 .LBE5:
434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
400 .loc 1 434 0
401 024a D368 ldr r3, [r2, #12]
402 024c 43F48033 orr r3, r3, #65536
403 0250 D360 str r3, [r2, #12]
404 .loc 1 477 0
405 0252 02B0 add sp, sp, #8
406 .LCFI4:
407 .cfi_remember_state
408 .cfi_def_cfa_offset 24
409 @ sp needed
410 0254 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
411 .LVL24:
412 .L10:
413 .LCFI5:
414 .cfi_restore_state
415 .LBB6:
160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
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416 .loc 1 160 0
417 0258 0320 movs r0, #3
418 025a 2AE7 b .L5
419 .LVL25:
420 .L81:
421 .LBE6:
354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
422 .loc 1 354 0
423 025c CA68 ldr r2, [r1, #12]
424 025e 42F48012 orr r2, r2, #1048576
425 0262 CA60 str r2, [r1, #12]
426 0264 9DE7 b .L23
427 .L82:
370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
428 .loc 1 370 0
429 0266 CA68 ldr r2, [r1, #12]
430 0268 42F48012 orr r2, r2, #1048576
431 026c CA60 str r2, [r1, #12]
432 026e A6E7 b .L26
433 .L83:
387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
434 .loc 1 387 0
435 0270 CA68 ldr r2, [r1, #12]
436 0272 42F48012 orr r2, r2, #1048576
437 0276 CA60 str r2, [r1, #12]
438 0278 AFE7 b .L29
439 .L84:
403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
440 .loc 1 403 0
441 027a CA68 ldr r2, [r1, #12]
442 027c 42F48012 orr r2, r2, #1048576
443 0280 CA60 str r2, [r1, #12]
444 0282 B8E7 b .L32
445 .L85:
418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
446 .loc 1 418 0
447 0284 CA68 ldr r2, [r1, #12]
448 0286 42F48012 orr r2, r2, #1048576
449 028a CA60 str r2, [r1, #12]
450 028c C1E7 b .L35
451 .L88:
452 028e 00BF .align 2
453 .L87:
454 0290 00100240 .word 1073876992
455 0294 00700040 .word 1073770496
456 .cfi_endproc
457 .LFE329:
459 .section .text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits
460 .align 1
461 .p2align 2,,3
462 .global HAL_RCCEx_GetPeriphCLKConfig
463 .syntax unified
464 .thumb
465 .thumb_func
466 .fpu fpv4-sp-d16
468 HAL_RCCEx_GetPeriphCLKConfig:
469 .LFB330:
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478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * returns the configuration information for the Extended Peripherals
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2, I2C3, I2C4,
484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI).
485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
470 .loc 1 488 0
471 .cfi_startproc
472 @ args = 0, pretend = 0, frame = 0
473 @ frame_needed = 0, uses_anonymous_args = 0
474 @ link register save eliminated.
475 .LVL26:
489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/
490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(STM32G474xx) || defined(STM32G484xx)
492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART5 | \
495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCL
496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C4 | \
497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCL
498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCL
499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_QSPI | \
500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RTC;
501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G491xx) || defined(STM32G4A1xx)
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART5 | \
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCL
506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCL
507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCL
508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_QSPI | \
509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RTC;
510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G473xx) || defined(STM32G483xx)
512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART5 | \
515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCL
516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C4 | \
517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCL
518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCL
519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_QSPI | \
520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RTC;
521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G471xx)
523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART5 | \
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCL
527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C4 | \
528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCL
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529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCL
530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RTC;
531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32G431xx) || defined(STM32G441xx)
532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCL
535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCL
536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCL
537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RTC;
538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #elif defined(STM32GBK1CB)
539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCL
541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCL
542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCL
543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCL
544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_RTC;
545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* STM32G431xx */
547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the USART1 clock source ---------------------------------------------*/
550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
476 .loc 1 550 0
477 0000 294B ldr r3, .L90
533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCL
478 .loc 1 533 0
479 0002 2A4A ldr r2, .L90+4
480 0004 0260 str r2, [r0]
481 .loc 1 550 0
482 0006 D3F88820 ldr r2, [r3, #136]
483 000a 02F00302 and r2, r2, #3
484 000e 4260 str r2, [r0, #4]
551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the USART2 clock source ---------------------------------------------*/
552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
485 .loc 1 552 0
486 0010 D3F88820 ldr r2, [r3, #136]
487 0014 02F00C02 and r2, r2, #12
488 0018 8260 str r2, [r0, #8]
553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the USART3 clock source ---------------------------------------------*/
554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
489 .loc 1 554 0
490 001a D3F88820 ldr r2, [r3, #136]
491 001e 02F03002 and r2, r2, #48
492 0022 C260 str r2, [r0, #12]
555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART4)
557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the UART4 clock source ----------------------------------------------*/
558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
493 .loc 1 558 0
494 0024 D3F88820 ldr r2, [r3, #136]
495 0028 02F0C002 and r2, r2, #192
496 002c 0261 str r2, [r0, #16]
559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART4 */
560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART5)
562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the UART5 clock source ----------------------------------------------*/
563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
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564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART5 */
565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the LPUART1 clock source --------------------------------------------*/
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
497 .loc 1 567 0
498 002e D3F88820 ldr r2, [r3, #136]
499 0032 02F44062 and r2, r2, #3072
500 0036 4261 str r2, [r0, #20]
568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the I2C1 clock source -----------------------------------------------*/
570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
501 .loc 1 570 0
502 0038 D3F88820 ldr r2, [r3, #136]
503 003c 02F44052 and r2, r2, #12288
504 0040 8261 str r2, [r0, #24]
571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the I2C2 clock source ----------------------------------------------*/
573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
505 .loc 1 573 0
506 0042 D3F88820 ldr r2, [r3, #136]
507 0046 02F44042 and r2, r2, #49152
508 004a C261 str r2, [r0, #28]
574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the I2C3 clock source -----------------------------------------------*/
576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
509 .loc 1 576 0
510 004c D3F88820 ldr r2, [r3, #136]
511 0050 02F44032 and r2, r2, #196608
512 0054 0262 str r2, [r0, #32]
577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(I2C4)
579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the I2C4 clock source -----------------------------------------------*/
580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* I2C4 */
582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the LPTIM1 clock source ---------------------------------------------*/
584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
513 .loc 1 584 0
514 0056 D3F88820 ldr r2, [r3, #136]
515 005a 02F44022 and r2, r2, #786432
516 005e 4262 str r2, [r0, #36]
585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the SAI1 clock source -----------------------------------------------*/
587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
517 .loc 1 587 0
518 0060 D3F88820 ldr r2, [r3, #136]
519 0064 02F44012 and r2, r2, #3145728
520 0068 8262 str r2, [r0, #40]
588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the I2S clock source -----------------------------------------------*/
590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
521 .loc 1 590 0
522 006a D3F88820 ldr r2, [r3, #136]
523 006e 02F44002 and r2, r2, #12582912
524 0072 C262 str r2, [r0, #44]
591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(FDCAN1)
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593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the FDCAN clock source -----------------------------------------------*/
594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
525 .loc 1 594 0
526 0074 D3F88820 ldr r2, [r3, #136]
527 0078 02F04072 and r2, r2, #50331648
528 007c 0263 str r2, [r0, #48]
595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* FDCAN1 */
596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(USB)
598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the USB clock source ------------------------------------------------*/
599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
529 .loc 1 599 0
530 007e D3F88820 ldr r2, [r3, #136]
531 0082 02F04062 and r2, r2, #201326592
532 0086 4263 str r2, [r0, #52]
600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* USB */
601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the RNG clock source ------------------------------------------------*/
603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
533 .loc 1 603 0
534 0088 D3F88820 ldr r2, [r3, #136]
535 008c 02F04062 and r2, r2, #201326592
536 0090 8263 str r2, [r0, #56]
604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the ADC12 clock source -----------------------------------------------*/
606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
537 .loc 1 606 0
538 0092 D3F88820 ldr r2, [r3, #136]
539 0096 02F04052 and r2, r2, #805306368
540 009a C263 str r2, [r0, #60]
607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(ADC345_COMMON)
609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the ADC345 clock source ----------------------------------------------*/
610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->Adc345ClockSelection = __HAL_RCC_GET_ADC345_SOURCE();
611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* ADC345_COMMON */
612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(QUADSPI)
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the QuadSPIclock source --------------------------------------------*/
615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* QUADSPI */
617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the RTC clock source ------------------------------------------------*/
619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
541 .loc 1 619 0
542 009c D3F89030 ldr r3, [r3, #144]
543 00a0 03F44073 and r3, r3, #768
544 00a4 0364 str r3, [r0, #64]
620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
545 .loc 1 621 0
546 00a6 7047 bx lr
547 .L91:
548 .align 2
549 .L90:
550 00a8 00100240 .word 1073876992
551 00ac EFFF0800 .word 589807
552 .cfi_endproc
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553 .LFE330:
555 .section .text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits
556 .align 1
557 .p2align 2,,3
558 .global HAL_RCCEx_GetPeriphCLKFreq
559 .syntax unified
560 .thumb
561 .thumb_func
562 .fpu fpv4-sp-d16
564 HAL_RCCEx_GetPeriphCLKFreq:
565 .LFB331:
622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Return the peripheral clock frequency for peripherals with clock source from PLL
625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note Return 0 if peripheral clock identifier not managed by this API
626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param PeriphClk Peripheral clock identifier
627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * This parameter can be one of the following values:
628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4)
632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5)
633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4)
638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S SPI peripheral clock
641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN)
642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB)
644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock
645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devic
646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock (only for devices with QSPI)
647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval Frequency in Hz
649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
566 .loc 1 651 0
567 .cfi_startproc
568 @ args = 0, pretend = 0, frame = 0
569 @ frame_needed = 0, uses_anonymous_args = 0
570 @ link register save eliminated.
571 .LVL27:
652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t frequency = 0U;
653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t srcclk;
654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t pllvco, plln, pllp;
655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(PeriphClk == RCC_PERIPHCLK_RTC)
572 .loc 1 659 0
573 0000 B0F5002F cmp r0, #524288
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 23
aggiunta cod
2021-07-02 22:19:04 +02:00
660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current RTC source */
662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_RTC_SOURCE();
574 .loc 1 662 0
575 0004 C44A ldr r2, .L288
659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
576 .loc 1 659 0
577 0006 2ED0 beq .L278
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check if LSE is ready and if RTC clock selection is LSE */
665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check if LSI is ready and if RTC clock selection is LSI */
670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSI_VALUE;
673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 32U;
678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for RTC*/
680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Other external peripheral clock source than RTC */
688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Compute PLL clock input */
690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */
578 .loc 1 690 0
579 0008 D368 ldr r3, [r2, #12]
580 000a 03F00303 and r3, r3, #3
581 000e 022B cmp r3, #2
582 0010 22D0 beq .L279
691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllvco = HSI_VALUE;
695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllvco = 0U;
699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */
583 .loc 1 701 0
584 0012 D368 ldr r3, [r2, #12]
585 0014 03F00303 and r3, r3, #3
586 0018 032B cmp r3, #3
587 001a 00F0AF80 beq .L280
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 24
aggiunta cod
2021-07-02 22:19:04 +02:00
698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
588 .loc 1 698 0
589 001e 0022 movs r2, #0
590 .L98:
591 .LVL28:
702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllvco = HSE_VALUE;
706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllvco = 0U;
710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else /* No source */
713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllvco = 0U;
715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLL Source) / PLLM */
718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
592 .loc 1 718 0
593 0020 BD49 ldr r1, .L288
594 0022 CB68 ldr r3, [r1, #12]
719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** switch(PeriphClk)
595 .loc 1 720 0
596 0024 B0F5807F cmp r0, #256
718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
597 .loc 1 718 0
598 0028 C3F30313 ubfx r3, r3, #4, #4
599 002c 03F10103 add r3, r3, #1
600 0030 B2FBF3F2 udiv r2, r2, r3
601 .LVL29:
602 .loc 1 720 0
603 0034 00F05A81 beq .L99
604 0038 35D8 bhi .L100
605 003a 0828 cmp r0, #8
606 003c 00F07681 beq .L101
607 0040 4ED9 bls .L281
608 0042 4028 cmp r0, #64
609 0044 00F03F81 beq .L106
610 0048 8028 cmp r0, #128
611 004a 00F02981 beq .L107
612 004e 2028 cmp r0, #32
613 0050 00F0A680 beq .L282
614 .LVL30:
615 .L177:
652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t srcclk;
616 .loc 1 652 0
617 0054 0020 movs r0, #0
618 .LVL31:
619 0056 7047 bx lr
620 .LVL32:
621 .L279:
692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 25
aggiunta cod
2021-07-02 22:19:04 +02:00
622 .loc 1 692 0
623 0058 1368 ldr r3, [r2]
694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
624 .loc 1 694 0
625 005a B04A ldr r2, .L288+4
626 005c 13F4806F tst r3, #1024
627 0060 08BF it eq
628 0062 0022 moveq r2, #0
629 0064 DCE7 b .L98
630 .L278:
662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
631 .loc 1 662 0
632 0066 D2F89030 ldr r3, [r2, #144]
665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
633 .loc 1 665 0
634 006a D2F89020 ldr r2, [r2, #144]
635 006e 9207 lsls r2, r2, #30
662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
636 .loc 1 662 0
637 0070 03F44073 and r3, r3, #768
638 .LVL33:
665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
639 .loc 1 665 0
640 0074 03D5 bpl .L94
665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
641 .loc 1 665 0 is_stmt 0 discriminator 1
642 0076 B3F5807F cmp r3, #256
643 007a 00F08680 beq .L135
644 .L94:
670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
645 .loc 1 670 0 is_stmt 1
646 007e A64A ldr r2, .L288
647 0080 D2F89420 ldr r2, [r2, #148]
648 0084 9007 lsls r0, r2, #30
649 .LVL34:
650 0086 03D5 bpl .L96
670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
651 .loc 1 670 0 is_stmt 0 discriminator 1
652 0088 B3F5007F cmp r3, #512
653 008c 00F08580 beq .L164
654 .L96:
675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
655 .loc 1 675 0 is_stmt 1
656 0090 A14A ldr r2, .L288
657 0092 1068 ldr r0, [r2]
658 0094 10F40030 ands r0, r0, #131072
659 0098 21D0 beq .L267
677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
660 .loc 1 677 0 discriminator 1
661 009a B3F5407F cmp r3, #768
662 009e A048 ldr r0, .L288+8
663 00a0 18BF it ne
664 00a2 0020 movne r0, #0
665 00a4 7047 bx lr
666 .LVL35:
667 .L100:
668 .loc 1 720 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 26
aggiunta cod
2021-07-02 22:19:04 +02:00
669 00a6 B0F5805F cmp r0, #4096
670 00aa 00F0BF80 beq .L109
671 00ae 39D9 bls .L283
672 00b0 B0F5804F cmp r0, #16384
673 00b4 06D0 beq .L114
674 00b6 B0F5004F cmp r0, #32768
675 00ba 00F08F80 beq .L115
676 00be B0F5005F cmp r0, #8192
677 00c2 C7D1 bne .L177
678 .L114:
721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART1:
724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current USART1 source */
725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART1_SOURCE();
726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK2Freq();
730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI) )
736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for USART1 */
744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART2:
751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current USART2 source */
752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART2_SOURCE();
753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 27
aggiunta cod
2021-07-02 22:19:04 +02:00
768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for USART2 */
771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART3:
778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current USART3 source */
779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART3_SOURCE();
780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for USART3 */
798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART4)
805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_UART4:
806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current UART4 source */
807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_UART4_SOURCE();
808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 28
aggiunta cod
2021-07-02 22:19:04 +02:00
825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for UART4 */
826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART4 */
832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(UART5)
834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_UART5:
835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current UART5 source */
836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_UART5_SOURCE();
837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for UART5 */
855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* UART5 */
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LPUART1:
863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current LPUART1 source */
864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 29
aggiunta cod
2021-07-02 22:19:04 +02:00
882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for LPUART1 */
883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C1:
890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current I2C1 source */
891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C1_SOURCE();
892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for I2C1 */
906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C2:
913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current I2C2 source */
914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C2_SOURCE();
915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for I2C2 */
929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C3:
936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current I2C3 source */
937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C3_SOURCE();
938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 30
aggiunta cod
2021-07-02 22:19:04 +02:00
939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI))
948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for I2C3 */
952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(I2C4)
959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C4:
961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current I2C4 source */
962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C4_SOURCE();
963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_I2C4CLKSOURCE_PCLK1)
965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for I2C4 */
977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* I2C4 */
984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LPTIM1:
986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current LPTIM1 source */
987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSI_VALUE;
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 31
aggiunta cod
2021-07-02 22:19:04 +02:00
996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = LSE_VALUE;
1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for LPTIM1 */
1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_SAI1:
1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current SAI1 source */
1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_SAI1_SOURCE();
1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_SAI1CLKSOURCE_SYSCLK)
1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_SAI1CLKSOURCE_PLL)
1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_SAI1CLKSOURCE_EXT)
1030:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1031:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* External clock used.*/
1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE;
1033:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SAI1CLKSOURCE_HSI))
1035:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1036:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
1037:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1038:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for SAI1 */
1039:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1040:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1041:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1042:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1043:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1044:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1045:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2S:
1046:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current I2Sx source */
1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2S_SOURCE();
1048:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_I2SCLKSOURCE_SYSCLK)
1050:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1051:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
1052:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 32
aggiunta cod
2021-07-02 22:19:04 +02:00
1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_I2SCLKSOURCE_PLL)
1054:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1055:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
1056:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1057:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
1058:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1059:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
1060:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1061:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_I2SCLKSOURCE_EXT)
1063:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1064:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* External clock used.*/
1065:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE;
1066:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2SCLKSOURCE_HSI))
1068:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1069:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
1070:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1071:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for I2S */
1072:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1073:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1074:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1075:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1076:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1077:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1078:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(FDCAN1)
1079:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_FDCAN:
1080:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current FDCANx source */
1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
1082:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_FDCANCLKSOURCE_PCLK1)
1084:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1085:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq();
1086:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_FDCANCLKSOURCE_HSE)
1088:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSE_VALUE;
1090:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_FDCANCLKSOURCE_PLL)
1092:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U)
1094:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1095:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
1096:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1097:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
1098:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1099:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for FDCAN */
1101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* FDCAN1 */
1107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(USB)
1109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 33
aggiunta cod
2021-07-02 22:19:04 +02:00
1110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USB:
1111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current USB source */
1112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USB_SOURCE();
1113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */
1115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
1117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
1119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48
1121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI48_VALUE;
1123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else /* No clock source */
1125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* USB */
1131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_RNG:
1133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current RNG source */
1134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_RNG_SOURCE();
679 .loc 1 1134 0
680 00c4 D1F88830 ldr r3, [r1, #136]
681 00c8 03F04063 and r3, r3, #201326592
682 .LVL36:
1135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */
683 .loc 1 1136 0
684 00cc B3F1006F cmp r3, #134217728
685 00d0 00F0BF80 beq .L272
1137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
1141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if( (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI4
686 .loc 1 1142 0
687 00d4 D1F89800 ldr r0, [r1, #152]
688 .LVL37:
689 00d8 10F00200 ands r0, r0, #2
690 00dc 58D1 bne .L284
691 .LVL38:
692 .L267:
1143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI48_VALUE;
1145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else /* No clock source */
1147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC12:
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 34
aggiunta cod
2021-07-02 22:19:04 +02:00
1153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current ADC12 source */
1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC12_SOURCE();
1155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_ADC12CLKSOURCE_PLL)
1157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
1159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLP) = f(VCO input) * PLLN / PLLP */
1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(pllp == 0U)
1164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
1166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = 17U;
1168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = 7U;
1172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / pllp;
1175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_ADC12CLKSOURCE_SYSCLK)
1178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
1180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for ADC12 */
1182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(ADC345_COMMON)
1189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC345:
1190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current ADC345 source */
1191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC345_SOURCE();
1192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_ADC345CLKSOURCE_PLL)
1194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U)
1196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLP) = f(VCO input) * PLLN / PLLP */
1198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
1200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(pllp == 0U)
1201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
1203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = 17U;
1205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = 7U;
1209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 35
aggiunta cod
2021-07-02 22:19:04 +02:00
1210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / pllp;
1212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_ADC345CLKSOURCE_SYSCLK)
1215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
1217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clock not enabled for ADC345 */
1219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* ADC345_COMMON */
1225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(QUADSPI)
1227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_QSPI:
1229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the current QSPI source */
1230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_QSPI_SOURCE();
1231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(srcclk == RCC_QSPICLKSOURCE_PLL) /* PLL ? */
1233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */
1235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
1237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_QSPICLKSOURCE_HSI)
1239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HSI_VALUE;
1241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(srcclk == RCC_QSPICLKSOURCE_SYSCLK)
1243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq();
1245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else /* No clock source */
1247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* nothing to do: frequency already initialized to 0 */
1249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #endif /* QUADSPI */
1253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** default:
1255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** break;
1256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** return(frequency);
1260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
693 .loc 1 1260 0
694 00de 7047 bx lr
695 .LVL39:
696 .L281:
720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
697 .loc 1 720 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 36
aggiunta cod
2021-07-02 22:19:04 +02:00
698 00e0 0228 cmp r0, #2
699 00e2 00F0C380 beq .L103
700 00e6 0428 cmp r0, #4
701 00e8 00F08680 beq .L104
702 00ec 0128 cmp r0, #1
703 00ee B1D1 bne .L177
725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
704 .loc 1 725 0
705 00f0 D1F88830 ldr r3, [r1, #136]
706 .LVL40:
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
707 .loc 1 727 0
708 00f4 13F00303 ands r3, r3, #3
709 .LVL41:
710 00f8 00F07E81 beq .L285
731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
711 .loc 1 731 0
712 00fc 012B cmp r3, #1
713 00fe 79D0 beq .L268
735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
714 .loc 1 735 0
715 0100 0A68 ldr r2, [r1]
716 .LVL42:
717 0102 5105 lsls r1, r2, #21
718 0104 02D5 bpl .L119
735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
719 .loc 1 735 0 is_stmt 0 discriminator 1
720 0106 022B cmp r3, #2
721 0108 00F07481 beq .L165
722 .L119:
739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
723 .loc 1 739 0 is_stmt 1
724 010c 824A ldr r2, .L288
725 010e D2F89000 ldr r0, [r2, #144]
726 .LVL43:
727 0112 10F00200 ands r0, r0, #2
728 0116 E2D0 beq .L267
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
729 .loc 1 741 0 discriminator 1
730 0118 032B cmp r3, #3
731 011a 14BF ite ne
732 011c 0020 movne r0, #0
733 011e 4FF40040 moveq r0, #32768
734 0122 7047 bx lr
735 .LVL44:
736 .L283:
720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
737 .loc 1 720 0
738 0124 B0F5806F cmp r0, #1024
739 0128 00F03281 beq .L111
740 012c B0F5006F cmp r0, #2048
741 0130 00F01781 beq .L112
742 0134 B0F5007F cmp r0, #512
743 0138 8CD1 bne .L177
987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
744 .loc 1 987 0
745 013a D1F88830 ldr r3, [r1, #136]
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 37
aggiunta cod
2021-07-02 22:19:04 +02:00
746 .LVL45:
989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
747 .loc 1 989 0
748 013e 13F44023 ands r3, r3, #786432
749 .LVL46:
750 0142 49D0 beq .L123
993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
751 .loc 1 993 0
752 0144 D1F89420 ldr r2, [r1, #148]
753 .LVL47:
754 0148 9007 lsls r0, r2, #30
755 .LVL48:
756 014a 02D5 bpl .L127
993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
757 .loc 1 993 0 is_stmt 0 discriminator 1
758 014c B3F5802F cmp r3, #262144
759 0150 23D0 beq .L164
760 .L127:
997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
761 .loc 1 997 0 is_stmt 1
762 0152 714A ldr r2, .L288
763 0154 1268 ldr r2, [r2]
764 0156 5105 lsls r1, r2, #21
765 0158 03D5 bpl .L128
997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
766 .loc 1 997 0 is_stmt 0 discriminator 1
767 015a B3F5002F cmp r3, #524288
768 015e 00F04981 beq .L165
769 .L128:
1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
770 .loc 1 1001 0 is_stmt 1
771 0162 6D4A ldr r2, .L288
772 0164 D2F89000 ldr r0, [r2, #144]
773 0168 10F00200 ands r0, r0, #2
774 016c B7D0 beq .L267
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
775 .loc 1 741 0 discriminator 1
776 016e B3F5402F cmp r3, #786432
777 0172 14BF ite ne
778 0174 0020 movne r0, #0
779 0176 4FF40040 moveq r0, #32768
780 017a 7047 bx lr
781 .LVL49:
782 .L280:
703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
783 .loc 1 703 0
784 017c 1368 ldr r3, [r2]
705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
785 .loc 1 705 0
786 017e 694A ldr r2, .L288+12
787 0180 13F4003F tst r3, #131072
788 0184 08BF it eq
789 0186 0022 moveq r2, #0
790 0188 4AE7 b .L98
791 .LVL50:
792 .L135:
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 38
aggiunta cod
2021-07-02 22:19:04 +02:00
793 .loc 1 741 0
794 018a 4FF40040 mov r0, #32768
795 .LVL51:
796 018e 7047 bx lr
797 .LVL52:
798 .L284:
1122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
799 .loc 1 1122 0 discriminator 1
800 0190 002B cmp r3, #0
801 0192 6548 ldr r0, .L288+16
802 0194 18BF it ne
803 0196 0020 movne r0, #0
804 0198 7047 bx lr
805 .LVL53:
806 .L164:
995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
807 .loc 1 995 0
808 019a 4FF4FA40 mov r0, #32000
809 019e 7047 bx lr
810 .LVL54:
811 .L282:
864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
812 .loc 1 864 0
813 01a0 D1F88830 ldr r3, [r1, #136]
814 .LVL55:
866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
815 .loc 1 866 0
816 01a4 13F44063 ands r3, r3, #3072
817 .LVL56:
818 01a8 16D0 beq .L123
870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
819 .loc 1 870 0
820 01aa B3F5806F cmp r3, #1024
821 01ae 21D0 beq .L268
874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
822 .loc 1 874 0
823 01b0 0A68 ldr r2, [r1]
824 .LVL57:
825 01b2 5205 lsls r2, r2, #21
826 01b4 03D5 bpl .L126
874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
827 .loc 1 874 0 is_stmt 0 discriminator 1
828 01b6 B3F5006F cmp r3, #2048
829 01ba 00F01B81 beq .L165
830 .L126:
878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
831 .loc 1 878 0 is_stmt 1
832 01be 564A ldr r2, .L288
833 01c0 D2F89000 ldr r0, [r2, #144]
834 .LVL58:
835 01c4 10F00200 ands r0, r0, #2
836 01c8 89D0 beq .L267
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
837 .loc 1 741 0 discriminator 1
838 01ca B3F5406F cmp r3, #3072
839 01ce 14BF ite ne
840 01d0 0020 movne r0, #0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 39
aggiunta cod
2021-07-02 22:19:04 +02:00
841 01d2 4FF40040 moveq r0, #32768
842 01d6 7047 bx lr
843 .LVL59:
844 .L123:
756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
845 .loc 1 756 0
846 01d8 FFF7FEBF b HAL_RCC_GetPCLK1Freq
847 .LVL60:
848 .L115:
1154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
849 .loc 1 1154 0
850 01dc D1F88830 ldr r3, [r1, #136]
851 01e0 03F04053 and r3, r3, #805306368
852 .LVL61:
1156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
853 .loc 1 1156 0
854 01e4 B3F1805F cmp r3, #268435456
855 01e8 00F0EE80 beq .L286
1177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
856 .loc 1 1177 0
857 01ec B3F1005F cmp r3, #536870912
858 01f0 7FF430AF bne .L177
859 .L268:
733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
860 .loc 1 733 0
861 01f4 FFF7FEBF b HAL_RCC_GetSysClockFreq
862 .LVL62:
863 .L104:
779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
864 .loc 1 779 0
865 01f8 D1F88830 ldr r3, [r1, #136]
866 .LVL63:
781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
867 .loc 1 781 0
868 01fc 13F03003 ands r3, r3, #48
869 .LVL64:
870 0200 EAD0 beq .L123
785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
871 .loc 1 785 0
872 0202 102B cmp r3, #16
873 0204 F6D0 beq .L268
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
874 .loc 1 789 0
875 0206 0A68 ldr r2, [r1]
876 .LVL65:
877 0208 5005 lsls r0, r2, #21
878 .LVL66:
879 020a 02D5 bpl .L124
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
880 .loc 1 789 0 is_stmt 0 discriminator 1
881 020c 202B cmp r3, #32
882 020e 00F0F180 beq .L165
883 .L124:
793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
884 .loc 1 793 0 is_stmt 1
885 0212 414A ldr r2, .L288
886 0214 D2F89000 ldr r0, [r2, #144]
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 40
aggiunta cod
2021-07-02 22:19:04 +02:00
887 0218 10F00200 ands r0, r0, #2
888 021c 3FF45FAF beq .L267
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
889 .loc 1 741 0 discriminator 1
890 0220 302B cmp r3, #48
891 0222 14BF ite ne
892 0224 0020 movne r0, #0
893 0226 4FF40040 moveq r0, #32768
894 022a 7047 bx lr
895 .LVL67:
896 .L109:
1081:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
897 .loc 1 1081 0
898 022c D1F88830 ldr r3, [r1, #136]
899 0230 03F04073 and r3, r3, #50331648
900 .LVL68:
1083:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
901 .loc 1 1083 0
902 0234 B3F1007F cmp r3, #33554432
903 0238 CED0 beq .L123
1087:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
904 .loc 1 1087 0
905 023a 002B cmp r3, #0
906 023c 00F0DE80 beq .L176
1091:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
907 .loc 1 1091 0
908 0240 B3F1807F cmp r3, #16777216
909 0244 7FF406AF bne .L177
910 .L275:
1093:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
911 .loc 1 1093 0
912 0248 C868 ldr r0, [r1, #12]
913 .LVL69:
914 024a 10F48010 ands r0, r0, #1048576
915 024e 3FF446AF beq .L267
916 .L272:
1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
917 .loc 1 1139 0
918 0252 C868 ldr r0, [r1, #12]
919 .LVL70:
1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
920 .loc 1 1140 0
921 0254 CB68 ldr r3, [r1, #12]
922 .LVL71:
923 0256 C3F34153 ubfx r3, r3, #21, #2
924 025a 0133 adds r3, r3, #1
1139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PL
925 .loc 1 1139 0
926 025c C0F30620 ubfx r0, r0, #8, #7
927 .LVL72:
1140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
928 .loc 1 1140 0
929 0260 5B00 lsls r3, r3, #1
930 0262 02FB00F0 mul r0, r2, r0
931 0266 B0FBF3F0 udiv r0, r0, r3
932 .LVL73:
933 026a 7047 bx lr
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 41
aggiunta cod
2021-07-02 22:19:04 +02:00
934 .LVL74:
935 .L103:
752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
936 .loc 1 752 0
937 026c D1F88830 ldr r3, [r1, #136]
938 .LVL75:
754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
939 .loc 1 754 0
940 0270 13F00C03 ands r3, r3, #12
941 .LVL76:
942 0274 B0D0 beq .L123
758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
943 .loc 1 758 0
944 0276 042B cmp r3, #4
945 0278 BCD0 beq .L268
762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
946 .loc 1 762 0
947 027a 0A68 ldr r2, [r1]
948 .LVL77:
949 027c 5205 lsls r2, r2, #21
950 027e 02D5 bpl .L122
762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
951 .loc 1 762 0 is_stmt 0 discriminator 1
952 0280 082B cmp r3, #8
953 0282 00F0B780 beq .L165
954 .L122:
766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
955 .loc 1 766 0 is_stmt 1
956 0286 244A ldr r2, .L288
957 0288 D2F89000 ldr r0, [r2, #144]
958 .LVL78:
959 028c 10F00200 ands r0, r0, #2
960 0290 3FF425AF beq .L267
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
961 .loc 1 741 0 discriminator 1
962 0294 0C2B cmp r3, #12
963 0296 14BF ite ne
964 0298 0020 movne r0, #0
965 029a 4FF40040 moveq r0, #32768
966 029e 7047 bx lr
967 .LVL79:
968 .L107:
914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
969 .loc 1 914 0
970 02a0 D1F88830 ldr r3, [r1, #136]
971 .LVL80:
916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
972 .loc 1 916 0
973 02a4 13F44043 ands r3, r3, #49152
974 .LVL81:
975 02a8 96D0 beq .L123
920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
976 .loc 1 920 0
977 02aa B3F5804F cmp r3, #16384
978 02ae A1D0 beq .L268
924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
979 .loc 1 924 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 42
aggiunta cod
2021-07-02 22:19:04 +02:00
980 02b0 0868 ldr r0, [r1]
981 .LVL82:
982 02b2 10F48060 ands r0, r0, #1024
983 02b6 3FF412AF beq .L267
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
984 .loc 1 903 0 discriminator 1
985 02ba B3F5004F cmp r3, #32768
986 02be 1748 ldr r0, .L288+4
987 02c0 18BF it ne
988 02c2 0020 movne r0, #0
989 02c4 7047 bx lr
990 .LVL83:
991 .L106:
891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
992 .loc 1 891 0
993 02c6 D1F88830 ldr r3, [r1, #136]
994 .LVL84:
893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
995 .loc 1 893 0
996 02ca 13F44053 ands r3, r3, #12288
997 .LVL85:
998 02ce 83D0 beq .L123
897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
999 .loc 1 897 0
1000 02d0 B3F5805F cmp r3, #4096
1001 02d4 8ED0 beq .L268
901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1002 .loc 1 901 0
1003 02d6 0868 ldr r0, [r1]
1004 .LVL86:
1005 02d8 10F48060 ands r0, r0, #1024
1006 02dc 3FF4FFAE beq .L267
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1007 .loc 1 903 0 discriminator 1
1008 02e0 B3F5005F cmp r3, #8192
1009 02e4 0D48 ldr r0, .L288+4
1010 02e6 18BF it ne
1011 02e8 0020 movne r0, #0
1012 02ea 7047 bx lr
1013 .LVL87:
1014 .L99:
937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1015 .loc 1 937 0
1016 02ec D1F88830 ldr r3, [r1, #136]
1017 .LVL88:
939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1018 .loc 1 939 0
1019 02f0 13F44033 ands r3, r3, #196608
1020 .LVL89:
1021 02f4 3FF470AF beq .L123
943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1022 .loc 1 943 0
1023 02f8 B3F5803F cmp r3, #65536
1024 02fc 3FF47AAF beq .L268
947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1025 .loc 1 947 0
1026 0300 0868 ldr r0, [r1]
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 43
aggiunta cod
2021-07-02 22:19:04 +02:00
1027 .LVL90:
1028 0302 10F48060 ands r0, r0, #1024
1029 0306 3FF4EAAE beq .L267
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1030 .loc 1 903 0 discriminator 1
1031 030a B3F5003F cmp r3, #131072
1032 030e 0348 ldr r0, .L288+4
1033 0310 18BF it ne
1034 0312 0020 movne r0, #0
1035 0314 7047 bx lr
1036 .L289:
1037 0316 00BF .align 2
1038 .L288:
1039 0318 00100240 .word 1073876992
1040 031c 0024F400 .word 16000000
1041 0320 B0710B00 .word 750000
1042 0324 00366E01 .word 24000000
1043 0328 006CDC02 .word 48000000
1044 .LVL91:
1045 .L101:
807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1046 .loc 1 807 0
1047 032c D1F88830 ldr r3, [r1, #136]
1048 .LVL92:
809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1049 .loc 1 809 0
1050 0330 13F0C003 ands r3, r3, #192
1051 .LVL93:
1052 0334 3FF450AF beq .L123
813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1053 .loc 1 813 0
1054 0338 402B cmp r3, #64
1055 033a 3FF45BAF beq .L268
817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1056 .loc 1 817 0
1057 033e 0A68 ldr r2, [r1]
1058 .LVL94:
1059 0340 5105 lsls r1, r2, #21
1060 0342 01D5 bpl .L125
817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1061 .loc 1 817 0 is_stmt 0 discriminator 1
1062 0344 802B cmp r3, #128
1063 0346 55D0 beq .L165
1064 .L125:
821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1065 .loc 1 821 0 is_stmt 1
1066 0348 384A ldr r2, .L290
1067 034a D2F89000 ldr r0, [r2, #144]
1068 .LVL95:
1069 034e 10F00200 ands r0, r0, #2
1070 0352 3FF4C4AE beq .L267
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1071 .loc 1 741 0 discriminator 1
1072 0356 C02B cmp r3, #192
1073 0358 14BF ite ne
1074 035a 0020 movne r0, #0
1075 035c 4FF40040 moveq r0, #32768
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 44
aggiunta cod
2021-07-02 22:19:04 +02:00
1076 0360 7047 bx lr
1077 .LVL96:
1078 .L112:
1047:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1079 .loc 1 1047 0
1080 0362 D1F88830 ldr r3, [r1, #136]
1081 .LVL97:
1049:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1082 .loc 1 1049 0
1083 0366 13F44003 ands r3, r3, #12582912
1084 .LVL98:
1085 036a 3FF443AF beq .L268
1053:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1086 .loc 1 1053 0
1087 036e B3F5800F cmp r3, #4194304
1088 0372 3FF469AF beq .L275
1062:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1089 .loc 1 1062 0
1090 0376 B3F5000F cmp r3, #8388608
1091 037a 52D0 beq .L173
1067:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1092 .loc 1 1067 0
1093 037c 0A68 ldr r2, [r1]
1094 .LVL99:
1095 037e 5205 lsls r2, r2, #21
1096 0380 7FF568AE bpl .L177
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1097 .loc 1 903 0 discriminator 1
1098 0384 B3F5400F cmp r3, #12582912
1099 0388 2948 ldr r0, .L290+4
1100 .LVL100:
1101 038a 18BF it ne
1102 038c 0020 movne r0, #0
1103 038e 7047 bx lr
1104 .LVL101:
1105 .L111:
651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t frequency = 0U;
1106 .loc 1 651 0
1107 0390 10B4 push {r4}
1108 .LCFI6:
1109 .cfi_def_cfa_offset 4
1110 .cfi_offset 4, -4
1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1111 .loc 1 1014 0
1112 0392 D1F88840 ldr r4, [r1, #136]
1113 .LVL102:
1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1114 .loc 1 1016 0
1115 0396 14F44014 ands r4, r4, #3145728
1116 .LVL103:
1117 039a 11D0 beq .L121
1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1118 .loc 1 1020 0
1119 039c B4F5801F cmp r4, #1048576
1120 03a0 2ED0 beq .L287
1029:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1121 .loc 1 1029 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 45
aggiunta cod
2021-07-02 22:19:04 +02:00
1122 03a2 B4F5001F cmp r4, #2097152
1123 03a6 3ED0 beq .L169
1034:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1124 .loc 1 1034 0
1125 03a8 0868 ldr r0, [r1]
1126 .LVL104:
1127 03aa 10F48060 ands r0, r0, #1024
1128 03ae 04D0 beq .L92
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1129 .loc 1 903 0 discriminator 1
1130 03b0 B4F5401F cmp r4, #3145728
1131 03b4 1E48 ldr r0, .L290+4
1132 03b6 18BF it ne
1133 03b8 0020 movne r0, #0
1134 .LVL105:
1135 .L92:
1136 .loc 1 1260 0
1137 03ba 5DF8044B ldr r4, [sp], #4
1138 .LCFI7:
1139 .cfi_remember_state
1140 .cfi_restore 4
1141 .cfi_def_cfa_offset 0
1142 .LVL106:
1143 03be 7047 bx lr
1144 .LVL107:
1145 .L121:
1146 .LCFI8:
1147 .cfi_restore_state
1148 03c0 5DF8044B ldr r4, [sp], #4
1149 .LCFI9:
1150 .cfi_restore 4
1151 .cfi_def_cfa_offset 0
1152 .LVL108:
733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1153 .loc 1 733 0
1154 03c4 FFF7FEBF b HAL_RCC_GetSysClockFreq
1155 .LVL109:
1156 .L286:
1158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1157 .loc 1 1158 0
1158 03c8 C868 ldr r0, [r1, #12]
1159 .LVL110:
1160 03ca 10F48030 ands r0, r0, #65536
1161 03ce 3FF486AE beq .L267
1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
1162 .loc 1 1161 0
1163 03d2 C868 ldr r0, [r1, #12]
1162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(pllp == 0U)
1164 .loc 1 1162 0
1165 03d4 CB68 ldr r3, [r1, #12]
1166 .LVL111:
1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1167 .loc 1 1163 0
1168 03d6 DB0E lsrs r3, r3, #27
1161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
1169 .loc 1 1161 0
1170 03d8 C0F30620 ubfx r0, r0, #8, #7
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 46
aggiunta cod
2021-07-02 22:19:04 +02:00
1171 .LVL112:
1163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1172 .loc 1 1163 0
1173 03dc 05D1 bne .L134
1165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1174 .loc 1 1165 0
1175 03de CB68 ldr r3, [r1, #12]
1171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1176 .loc 1 1171 0
1177 03e0 13F4003F tst r3, #131072
1178 03e4 14BF ite ne
1179 03e6 1123 movne r3, #17
1180 03e8 0723 moveq r3, #7
1181 .L134:
1182 .LVL113:
1174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1183 .loc 1 1174 0
1184 03ea 00FB02F0 mul r0, r0, r2
1185 .LVL114:
1186 03ee B0FBF3F0 udiv r0, r0, r3
1187 .LVL115:
1188 03f2 7047 bx lr
1189 .LVL116:
1190 .L165:
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1191 .loc 1 903 0
1192 03f4 0E48 ldr r0, .L290+4
1193 03f6 7047 bx lr
1194 .LVL117:
1195 .L285:
729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1196 .loc 1 729 0
1197 03f8 FFF7FEBF b HAL_RCC_GetPCLK2Freq
1198 .LVL118:
1199 .L176:
1089:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1200 .loc 1 1089 0
1201 03fc 0D48 ldr r0, .L290+8
1202 .LVL119:
1203 03fe 7047 bx lr
1204 .LVL120:
1205 .L287:
1206 .LCFI10:
1207 .cfi_def_cfa_offset 4
1208 .cfi_offset 4, -4
1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1209 .loc 1 1022 0
1210 0400 C868 ldr r0, [r1, #12]
1211 .LVL121:
1212 0402 10F48010 ands r0, r0, #1048576
1213 0406 D8D0 beq .L92
1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
1214 .loc 1 1025 0
1215 0408 C868 ldr r0, [r1, #12]
1216 .LVL122:
1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1217 .loc 1 1026 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 47
aggiunta cod
2021-07-02 22:19:04 +02:00
1218 040a CB68 ldr r3, [r1, #12]
1219 040c C3F34153 ubfx r3, r3, #21, #2
1220 0410 0133 adds r3, r3, #1
1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_
1221 .loc 1 1025 0
1222 0412 C0F30620 ubfx r0, r0, #8, #7
1223 .LVL123:
1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1224 .loc 1 1026 0
1225 0416 5B00 lsls r3, r3, #1
1226 0418 02FB00F0 mul r0, r2, r0
1227 041c B0FBF3F0 udiv r0, r0, r3
1228 .LVL124:
1229 0420 CBE7 b .L92
1230 .LVL125:
1231 .L173:
1232 .LCFI11:
1233 .cfi_def_cfa_offset 0
1234 .cfi_restore 4
1032:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1235 .loc 1 1032 0
1236 0422 0548 ldr r0, .L290+12
1237 .LVL126:
1238 0424 7047 bx lr
1239 .LVL127:
1240 .L169:
1241 .LCFI12:
1242 .cfi_def_cfa_offset 4
1243 .cfi_offset 4, -4
1244 0426 0448 ldr r0, .L290+12
1245 .LVL128:
1246 0428 C7E7 b .L92
1247 .L291:
1248 042a 00BF .align 2
1249 .L290:
1250 042c 00100240 .word 1073876992
1251 0430 0024F400 .word 16000000
1252 0434 00366E01 .word 24000000
1253 0438 0080BB00 .word 12288000
1254 .cfi_endproc
1255 .LFE331:
1257 .section .text.HAL_RCCEx_EnableLSECSS,"ax",%progbits
1258 .align 1
1259 .p2align 2,,3
1260 .global HAL_RCCEx_EnableLSECSS
1261 .syntax unified
1262 .thumb
1263 .thumb_func
1264 .fpu fpv4-sp-d16
1266 HAL_RCCEx_EnableLSECSS:
1267 .LFB332:
1261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @}
1264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 48
aggiunta cod
2021-07-02 22:19:04 +02:00
1267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Extended Clock management functions
1268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
1269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @verbatim
1270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ===============================================================================
1271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ##### Extended clock management functions #####
1272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ===============================================================================
1273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** [..]
1274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the
1275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** activation or deactivation of LSE CSS,
1276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** Low speed clock output and clock after wake-up from STOP mode.
1277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @endverbatim
1278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
1279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Enable the LSE Clock Security System.
1283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
1284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
1285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * clock with HAL_RCCEx_PeriphCLKConfig().
1286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS(void)
1289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1268 .loc 1 1289 0
1269 .cfi_startproc
1270 @ args = 0, pretend = 0, frame = 0
1271 @ frame_needed = 0, uses_anonymous_args = 0
1272 @ link register save eliminated.
1290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
1273 .loc 1 1290 0
1274 0000 034A ldr r2, .L293
1275 0002 D2F89030 ldr r3, [r2, #144]
1276 0006 43F02003 orr r3, r3, #32
1277 000a C2F89030 str r3, [r2, #144]
1291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1278 .loc 1 1291 0
1279 000e 7047 bx lr
1280 .L294:
1281 .align 2
1282 .L293:
1283 0010 00100240 .word 1073876992
1284 .cfi_endproc
1285 .LFE332:
1287 .section .text.HAL_RCCEx_DisableLSECSS,"ax",%progbits
1288 .align 1
1289 .p2align 2,,3
1290 .global HAL_RCCEx_DisableLSECSS
1291 .syntax unified
1292 .thumb
1293 .thumb_func
1294 .fpu fpv4-sp-d16
1296 HAL_RCCEx_DisableLSECSS:
1297 .LFB333:
1292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Disable the LSE Clock Security System.
1295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note LSE Clock Security System can only be disabled after a LSE failure detection.
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 49
aggiunta cod
2021-07-02 22:19:04 +02:00
1296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableLSECSS(void)
1299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1298 .loc 1 1299 0
1299 .cfi_startproc
1300 @ args = 0, pretend = 0, frame = 0
1301 @ frame_needed = 0, uses_anonymous_args = 0
1302 @ link register save eliminated.
1300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
1303 .loc 1 1300 0
1304 0000 054B ldr r3, .L296
1305 0002 D3F89020 ldr r2, [r3, #144]
1306 0006 22F02002 bic r2, r2, #32
1307 000a C3F89020 str r2, [r3, #144]
1301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Disable LSE CSS IT if any */
1303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
1308 .loc 1 1303 0
1309 000e 9A69 ldr r2, [r3, #24]
1310 0010 22F40072 bic r2, r2, #512
1311 0014 9A61 str r2, [r3, #24]
1304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1312 .loc 1 1304 0
1313 0016 7047 bx lr
1314 .L297:
1315 .align 2
1316 .L296:
1317 0018 00100240 .word 1073876992
1318 .cfi_endproc
1319 .LFE333:
1321 .section .text.HAL_RCCEx_EnableLSECSS_IT,"ax",%progbits
1322 .align 1
1323 .p2align 2,,3
1324 .global HAL_RCCEx_EnableLSECSS_IT
1325 .syntax unified
1326 .thumb
1327 .thumb_func
1328 .fpu fpv4-sp-d16
1330 HAL_RCCEx_EnableLSECSS_IT:
1331 .LFB334:
1305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
1308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19
1309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS_IT(void)
1312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1332 .loc 1 1312 0
1333 .cfi_startproc
1334 @ args = 0, pretend = 0, frame = 0
1335 @ frame_needed = 0, uses_anonymous_args = 0
1336 @ link register save eliminated.
1313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable LSE CSS */
1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
1337 .loc 1 1314 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 50
aggiunta cod
2021-07-02 22:19:04 +02:00
1338 0000 0A4A ldr r2, .L299
1315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable LSE CSS IT */
1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
1318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable IT on EXTI Line 19 */
1320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
1339 .loc 1 1320 0
1340 0002 0B4B ldr r3, .L299+4
1314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1341 .loc 1 1314 0
1342 0004 D2F89010 ldr r1, [r2, #144]
1343 0008 41F02001 orr r1, r1, #32
1344 000c C2F89010 str r1, [r2, #144]
1317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1345 .loc 1 1317 0
1346 0010 9169 ldr r1, [r2, #24]
1347 0012 41F40071 orr r1, r1, #512
1348 0016 9161 str r1, [r2, #24]
1349 .loc 1 1320 0
1350 0018 1A68 ldr r2, [r3]
1351 001a 42F40022 orr r2, r2, #524288
1352 001e 1A60 str r2, [r3]
1321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
1353 .loc 1 1321 0
1354 0020 9A68 ldr r2, [r3, #8]
1355 0022 42F40022 orr r2, r2, #524288
1356 0026 9A60 str r2, [r3, #8]
1322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1357 .loc 1 1322 0
1358 0028 7047 bx lr
1359 .L300:
1360 002a 00BF .align 2
1361 .L299:
1362 002c 00100240 .word 1073876992
1363 0030 00040140 .word 1073808384
1364 .cfi_endproc
1365 .LFE334:
1367 .section .text.HAL_RCCEx_LSECSS_Callback,"ax",%progbits
1368 .align 1
1369 .p2align 2,,3
1370 .weak HAL_RCCEx_LSECSS_Callback
1371 .syntax unified
1372 .thumb
1373 .thumb_func
1374 .fpu fpv4-sp-d16
1376 HAL_RCCEx_LSECSS_Callback:
1377 .LFB336:
1323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Handle the RCC LSE Clock Security System interrupt request.
1326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_LSECSS_IRQHandler(void)
1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check RCC LSE CSSF flag */
1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 51
aggiunta cod
2021-07-02 22:19:04 +02:00
1332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* RCC LSE Clock Security System interrupt user callback */
1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_RCCEx_LSECSS_Callback();
1335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear RCC LSE CSS pending bit */
1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
1338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief RCCEx LSE Clock Security System interrupt callback.
1343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval none
1344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_LSECSS_Callback(void)
1346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1378 .loc 1 1346 0
1379 .cfi_startproc
1380 @ args = 0, pretend = 0, frame = 0
1381 @ frame_needed = 0, uses_anonymous_args = 0
1382 @ link register save eliminated.
1347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
1348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
1349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1383 .loc 1 1350 0
1384 0000 7047 bx lr
1385 .cfi_endproc
1386 .LFE336:
1388 0002 00BF .section .text.HAL_RCCEx_LSECSS_IRQHandler,"ax",%progbits
1389 .align 1
1390 .p2align 2,,3
1391 .global HAL_RCCEx_LSECSS_IRQHandler
1392 .syntax unified
1393 .thumb
1394 .thumb_func
1395 .fpu fpv4-sp-d16
1397 HAL_RCCEx_LSECSS_IRQHandler:
1398 .LFB335:
1329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check RCC LSE CSSF flag */
1399 .loc 1 1329 0
1400 .cfi_startproc
1401 @ args = 0, pretend = 0, frame = 0
1402 @ frame_needed = 0, uses_anonymous_args = 0
1403 0000 10B5 push {r4, lr}
1404 .LCFI13:
1405 .cfi_def_cfa_offset 8
1406 .cfi_offset 4, -8
1407 .cfi_offset 14, -4
1331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1408 .loc 1 1331 0
1409 0002 054C ldr r4, .L309
1410 0004 E369 ldr r3, [r4, #28]
1411 0006 9B05 lsls r3, r3, #22
1412 0008 00D4 bmi .L308
1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1413 .loc 1 1339 0
1414 000a 10BD pop {r4, pc}
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 52
aggiunta cod
2021-07-02 22:19:04 +02:00
1415 .L308:
1334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1416 .loc 1 1334 0
1417 000c FFF7FEFF bl HAL_RCCEx_LSECSS_Callback
1418 .LVL129:
1337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1419 .loc 1 1337 0
1420 0010 4FF40073 mov r3, #512
1421 0014 2362 str r3, [r4, #32]
1339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1422 .loc 1 1339 0
1423 0016 10BD pop {r4, pc}
1424 .L310:
1425 .align 2
1426 .L309:
1427 0018 00100240 .word 1073876992
1428 .cfi_endproc
1429 .LFE335:
1431 .section .text.HAL_RCCEx_EnableLSCO,"ax",%progbits
1432 .align 1
1433 .p2align 2,,3
1434 .global HAL_RCCEx_EnableLSCO
1435 .syntax unified
1436 .thumb
1437 .thumb_func
1438 .fpu fpv4-sp-d16
1440 HAL_RCCEx_EnableLSCO:
1441 .LFB337:
1351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
1354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param LSCOSource specifies the Low Speed clock source to output.
1355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * This parameter can be one of the following values:
1356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
1357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
1358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1442 .loc 1 1361 0
1443 .cfi_startproc
1444 @ args = 0, pretend = 0, frame = 32
1445 @ frame_needed = 0, uses_anonymous_args = 0
1446 .LVL130:
1447 0000 70B5 push {r4, r5, r6, lr}
1448 .LCFI14:
1449 .cfi_def_cfa_offset 16
1450 .cfi_offset 4, -16
1451 .cfi_offset 5, -12
1452 .cfi_offset 6, -8
1453 .cfi_offset 14, -4
1454 .LBB7:
1362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitTypeDef GPIO_InitStruct;
1363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET;
1364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** FlagStatus backupchanged = RESET;
1365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 53
aggiunta cod
2021-07-02 22:19:04 +02:00
1367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
1368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* LSCO Pin Clock Enable */
1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __LSCO_CLK_ENABLE();
1455 .loc 1 1370 0
1456 0002 254C ldr r4, .L318
1457 0004 E36C ldr r3, [r4, #76]
1458 0006 43F00103 orr r3, r3, #1
1459 000a E364 str r3, [r4, #76]
1460 000c E36C ldr r3, [r4, #76]
1461 .LBE7:
1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitTypeDef GPIO_InitStruct;
1462 .loc 1 1361 0
1463 000e 88B0 sub sp, sp, #32
1464 .LCFI15:
1465 .cfi_def_cfa_offset 48
1466 .LBB8:
1467 .loc 1 1370 0
1468 0010 03F00103 and r3, r3, #1
1469 0014 0193 str r3, [sp, #4]
1470 .LBE8:
1371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Configure the LSCO pin in analog mode */
1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitStruct.Pin = LSCO_PIN;
1471 .loc 1 1373 0
1472 0016 0421 movs r1, #4
1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
1473 .loc 1 1374 0
1474 0018 0322 movs r2, #3
1375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
1475 .loc 1 1375 0
1476 001a 0223 movs r3, #2
1373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
1477 .loc 1 1373 0
1478 001c 0391 str r1, [sp, #12]
1361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitTypeDef GPIO_InitStruct;
1479 .loc 1 1361 0
1480 001e 0546 mov r5, r0
1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1481 .loc 1 1376 0
1482 0020 0026 movs r6, #0
1483 .LBB9:
1370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1484 .loc 1 1370 0
1485 0022 0198 ldr r0, [sp, #4]
1486 .LVL131:
1487 .LBE9:
1374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
1488 .loc 1 1374 0
1489 0024 0492 str r2, [sp, #16]
1377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
1490 .loc 1 1377 0
1491 0026 03A9 add r1, sp, #12
1492 0028 4FF09040 mov r0, #1207959552
1376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
1493 .loc 1 1376 0
1494 002c CDE90563 strd r6, r3, [sp, #20]
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 54
aggiunta cod
2021-07-02 22:19:04 +02:00
1495 .loc 1 1377 0
1496 0030 FFF7FEFF bl HAL_GPIO_Init
1497 .LVL132:
1378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Update LSCOSEL clock source in Backup Domain control register */
1380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED())
1498 .loc 1 1380 0
1499 0034 A36D ldr r3, [r4, #88]
1500 0036 DA00 lsls r2, r3, #3
1501 0038 09D4 bmi .L312
1502 .LBB10:
1381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE();
1503 .loc 1 1382 0
1504 003a A36D ldr r3, [r4, #88]
1505 003c 43F08053 orr r3, r3, #268435456
1506 0040 A365 str r3, [r4, #88]
1507 0042 A36D ldr r3, [r4, #88]
1508 0044 03F08053 and r3, r3, #268435456
1509 0048 0293 str r3, [sp, #8]
1510 004a 029B ldr r3, [sp, #8]
1511 .LVL133:
1512 .LBE10:
1383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pwrclkchanged = SET;
1513 .loc 1 1383 0
1514 004c 0126 movs r6, #1
1515 .LVL134:
1516 .L312:
1384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
1517 .loc 1 1385 0
1518 004e 134B ldr r3, .L318+4
1519 0050 1B68 ldr r3, [r3]
1520 0052 DB05 lsls r3, r3, #23
1521 0054 11D5 bpl .L313
1386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_PWR_EnableBkUpAccess();
1388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** backupchanged = SET;
1389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
1522 .loc 1 1391 0
1523 0056 104B ldr r3, .L318
1524 0058 D3F89000 ldr r0, [r3, #144]
1525 005c 20F04070 bic r0, r0, #50331648
1526 0060 40F08070 orr r0, r0, #16777216
1527 0064 2843 orrs r0, r0, r5
1528 0066 C3F89000 str r0, [r3, #144]
1529 .LVL135:
1530 .L314:
1392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(backupchanged == SET)
1394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_PWR_DisableBkUpAccess();
1396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(pwrclkchanged == SET)
1531 .loc 1 1397 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 55
aggiunta cod
2021-07-02 22:19:04 +02:00
1532 006a 26B1 cbz r6, .L311
1398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE();
1533 .loc 1 1399 0
1534 006c 0A4A ldr r2, .L318
1535 006e 936D ldr r3, [r2, #88]
1536 0070 23F08053 bic r3, r3, #268435456
1537 0074 9365 str r3, [r2, #88]
1538 .L311:
1400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1539 .loc 1 1401 0
1540 0076 08B0 add sp, sp, #32
1541 .LCFI16:
1542 .cfi_remember_state
1543 .cfi_def_cfa_offset 16
1544 @ sp needed
1545 0078 70BD pop {r4, r5, r6, pc}
1546 .LVL136:
1547 .L313:
1548 .LCFI17:
1549 .cfi_restore_state
1387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** backupchanged = SET;
1550 .loc 1 1387 0
1551 007a FFF7FEFF bl HAL_PWR_EnableBkUpAccess
1552 .LVL137:
1391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1553 .loc 1 1391 0
1554 007e 064B ldr r3, .L318
1555 0080 D3F89000 ldr r0, [r3, #144]
1556 0084 20F04070 bic r0, r0, #50331648
1557 0088 40F08070 orr r0, r0, #16777216
1558 008c 2843 orrs r0, r0, r5
1559 008e C3F89000 str r0, [r3, #144]
1395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1560 .loc 1 1395 0
1561 0092 FFF7FEFF bl HAL_PWR_DisableBkUpAccess
1562 .LVL138:
1563 0096 E8E7 b .L314
1564 .L319:
1565 .align 2
1566 .L318:
1567 0098 00100240 .word 1073876992
1568 009c 00700040 .word 1073770496
1569 .cfi_endproc
1570 .LFE337:
1572 .section .text.HAL_RCCEx_DisableLSCO,"ax",%progbits
1573 .align 1
1574 .p2align 2,,3
1575 .global HAL_RCCEx_DisableLSCO
1576 .syntax unified
1577 .thumb
1578 .thumb_func
1579 .fpu fpv4-sp-d16
1581 HAL_RCCEx_DisableLSCO:
1582 .LFB338:
1402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 56
aggiunta cod
2021-07-02 22:19:04 +02:00
1403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Disable the Low Speed clock output.
1405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableLSCO(void)
1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1583 .loc 1 1408 0
1584 .cfi_startproc
1585 @ args = 0, pretend = 0, frame = 8
1586 @ frame_needed = 0, uses_anonymous_args = 0
1587 .LVL139:
1588 0000 10B5 push {r4, lr}
1589 .LCFI18:
1590 .cfi_def_cfa_offset 8
1591 .cfi_offset 4, -8
1592 .cfi_offset 14, -4
1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET;
1410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** FlagStatus backupchanged = RESET;
1411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Update LSCOEN bit in Backup Domain control register */
1413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED())
1593 .loc 1 1413 0
1594 0002 1A4B ldr r3, .L328
1595 0004 9A6D ldr r2, [r3, #88]
1596 0006 D200 lsls r2, r2, #3
1408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET;
1597 .loc 1 1408 0
1598 0008 82B0 sub sp, sp, #8
1599 .LCFI19:
1600 .cfi_def_cfa_offset 16
1601 .loc 1 1413 0
1602 000a 1DD4 bmi .L325
1603 .LBB11:
1414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE();
1604 .loc 1 1415 0
1605 000c 9A6D ldr r2, [r3, #88]
1606 000e 42F08052 orr r2, r2, #268435456
1607 0012 9A65 str r2, [r3, #88]
1608 0014 9B6D ldr r3, [r3, #88]
1609 0016 03F08053 and r3, r3, #268435456
1610 001a 0193 str r3, [sp, #4]
1611 001c 019B ldr r3, [sp, #4]
1612 .LVL140:
1613 .LBE11:
1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pwrclkchanged = SET;
1417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
1614 .loc 1 1418 0
1615 001e 144B ldr r3, .L328+4
1616 0020 1B68 ldr r3, [r3]
1617 0022 DB05 lsls r3, r3, #23
1416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pwrclkchanged = SET;
1618 .loc 1 1416 0
1619 0024 4FF00104 mov r4, #1
1620 .LVL141:
1621 .loc 1 1418 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 57
aggiunta cod
2021-07-02 22:19:04 +02:00
1622 0028 14D5 bpl .L322
1623 .L327:
1419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable access to the backup domain */
1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_PWR_EnableBkUpAccess();
1422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** backupchanged = SET;
1423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1624 .loc 1 1425 0
1625 002a 104A ldr r2, .L328
1626 002c D2F89030 ldr r3, [r2, #144]
1627 0030 23F08073 bic r3, r3, #16777216
1628 0034 C2F89030 str r3, [r2, #144]
1629 .LVL142:
1630 .L323:
1426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Restore previous configuration */
1428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(backupchanged == SET)
1429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Disable access to the backup domain */
1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_PWR_DisableBkUpAccess();
1432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(pwrclkchanged == SET)
1631 .loc 1 1433 0
1632 0038 24B1 cbz r4, .L320
1434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE();
1633 .loc 1 1435 0
1634 003a 0C4A ldr r2, .L328
1635 003c 936D ldr r3, [r2, #88]
1636 003e 23F08053 bic r3, r3, #268435456
1637 0042 9365 str r3, [r2, #88]
1638 .L320:
1436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1639 .loc 1 1437 0
1640 0044 02B0 add sp, sp, #8
1641 .LCFI20:
1642 .cfi_remember_state
1643 .cfi_def_cfa_offset 8
1644 @ sp needed
1645 0046 10BD pop {r4, pc}
1646 .LVL143:
1647 .L325:
1648 .LCFI21:
1649 .cfi_restore_state
1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1650 .loc 1 1418 0
1651 0048 094B ldr r3, .L328+4
1652 004a 1B68 ldr r3, [r3]
1653 004c DB05 lsls r3, r3, #23
1409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** FlagStatus backupchanged = RESET;
1654 .loc 1 1409 0
1655 004e 4FF00004 mov r4, #0
1656 .LVL144:
1418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 58
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1657 .loc 1 1418 0
1658 0052 EAD4 bmi .L327
1659 .L322:
1421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** backupchanged = SET;
1660 .loc 1 1421 0
1661 0054 FFF7FEFF bl HAL_PWR_EnableBkUpAccess
1662 .LVL145:
1425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1663 .loc 1 1425 0
1664 0058 044A ldr r2, .L328
1665 005a D2F89030 ldr r3, [r2, #144]
1666 005e 23F08073 bic r3, r3, #16777216
1667 0062 C2F89030 str r3, [r2, #144]
1431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1668 .loc 1 1431 0
1669 0066 FFF7FEFF bl HAL_PWR_DisableBkUpAccess
1670 .LVL146:
1671 006a E5E7 b .L323
1672 .L329:
1673 .align 2
1674 .L328:
1675 006c 00100240 .word 1073876992
1676 0070 00700040 .word 1073770496
1677 .cfi_endproc
1678 .LFE338:
1680 .section .text.HAL_RCCEx_CRSConfig,"ax",%progbits
1681 .align 1
1682 .p2align 2,,3
1683 .global HAL_RCCEx_CRSConfig
1684 .syntax unified
1685 .thumb
1686 .thumb_func
1687 .fpu fpv4-sp-d16
1689 HAL_RCCEx_CRSConfig:
1690 .LFB339:
1438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @}
1442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** #if defined(CRS)
1445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
1447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Extended Clock Recovery System Control functions
1448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** *
1449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @verbatim
1450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ===============================================================================
1451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ##### Extended Clock Recovery System Control functions #####
1452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** ===============================================================================
1453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** [..]
1454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as
1455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (#) In System clock config, HSI48 needs to be enabled
1457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (#) Enable CRS clock in IP MSP init which will use CRS functions
1459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
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1460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (#) Call CRS functions as follows:
1461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (##) Prepare synchronization configuration necessary for HSI48 calibration
1462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) Default values can be set for frequency Error Measurement (reload and error lim
1463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** and also HSI48 oscillator smooth trimming.
1464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
1465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** directly reload value with target and sychronization frequencies values
1466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (##) Call function HAL_RCCEx_CRSConfig which
1467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) Resets CRS registers to their default values.
1468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) Configures CRS registers with synchronization configuration
1469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) Enables automatic calibration and frequency error counter feature
1470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
1471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
1472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
1473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
1474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** should be used as SYNC signal.
1475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (##) A polling function is provided to wait for complete synchronization
1477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
1478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) According to CRS status, user can decide to adjust again the calibration or con
1479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** application if synchronization is OK
1480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (#) User can retrieve information related to synchronization in calling function
1482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_RCCEx_CRSGetSynchronizationInfo()
1483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (#) Regarding synchronization status and synchronization information, user can try a new cali
1485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
1486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** Note: When the SYNC event is detected during the downcounting phase (before reaching the
1487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** it means that the actual frequency is lower than the target (and so, that the TRIM value
1488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** incremented), while when it is detected during the upcounting phase it means that the ac
1489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** is higher (and that the TRIM value should be decremented).
1490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interr
1492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** through CRS Handler (CRS_IRQn/CRS_IRQHandler)
1493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (++) Call function HAL_RCCEx_CRSConfig()
1494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (++) Enable CRS_IRQn (thanks to NVIC functions)
1495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
1496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (++) Implement CRS status management in the following user callbacks called from
1497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_IRQHandler():
1498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_SyncOkCallback()
1499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_SyncWarnCallback()
1500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
1501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_ErrorCallback()
1502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGene
1504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick h
1505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** @endverbatim
1507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @{
1508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Start automatic synchronization for polling mode
1512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param pInit Pointer on RCC_CRSInitTypeDef structure
1513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 60
aggiunta cod
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1691 .loc 1 1516 0
1692 .cfi_startproc
1693 @ args = 0, pretend = 0, frame = 0
1694 @ frame_needed = 0, uses_anonymous_args = 0
1695 @ link register save eliminated.
1696 .LVL147:
1517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t value;
1518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameters */
1520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
1521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
1522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
1523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
1524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
1525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
1526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* CONFIGURATION */
1528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Before configuration, reset CRS registers to their default values*/
1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_FORCE_RESET();
1697 .loc 1 1530 0
1698 0000 114B ldr r3, .L332
1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_RELEASE_RESET();
1532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the SYNCDIV[2:0] bits according to Prescaler value */
1534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the SYNCSRC[1:0] bits according to Source value */
1535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the SYNCSPOL bit according to Polarity value */
1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
1537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the RELOAD[15:0] bits according to ReloadValue value */
1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** value |= pInit->ReloadValue;
1539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
1541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value);
1699 .loc 1 1541 0
1700 0002 124A ldr r2, .L332+4
1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_RELEASE_RESET();
1701 .loc 1 1530 0
1702 0004 996B ldr r1, [r3, #56]
1703 0006 41F48071 orr r1, r1, #256
1516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t value;
1704 .loc 1 1516 0
1705 000a 30B4 push {r4, r5}
1706 .LCFI22:
1707 .cfi_def_cfa_offset 8
1708 .cfi_offset 4, -8
1709 .cfi_offset 5, -4
1530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_RELEASE_RESET();
1710 .loc 1 1530 0
1711 000c 9963 str r1, [r3, #56]
1531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_RELEASE_RESET();
1712 .loc 1 1531 0
1713 000e 996B ldr r1, [r3, #56]
1714 0010 21F48071 bic r1, r1, #256
1715 0014 9963 str r1, [r3, #56]
1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the RELOAD[15:0] bits according to ReloadValue value */
1716 .loc 1 1536 0
1717 0016 D0E90035 ldrd r3, r5, [r0]
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 61
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1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
1718 .loc 1 1538 0
1719 001a D0E90214 ldrd r1, r4, [r0, #8]
1536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the RELOAD[15:0] bits according to ReloadValue value */
1720 .loc 1 1536 0
1721 001e 2B43 orrs r3, r3, r5
1722 0020 0B43 orrs r3, r3, r1
1723 .LVL148:
1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value);
1724 .loc 1 1540 0
1725 0022 0169 ldr r1, [r0, #16]
1538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
1726 .loc 1 1538 0
1727 0024 2343 orrs r3, r3, r4
1728 .LVL149:
1540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value);
1729 .loc 1 1540 0
1730 0026 43EA0143 orr r3, r3, r1, lsl #16
1731 .LVL150:
1732 .loc 1 1541 0
1733 002a 5360 str r3, [r2, #4]
1542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Adjust HSI48 oscillator smooth trimming */
1544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */
1545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
1734 .loc 1 1545 0
1735 002c 1368 ldr r3, [r2]
1736 .LVL151:
1737 002e 4169 ldr r1, [r0, #20]
1738 0030 23F4FE43 bic r3, r3, #32512
1739 0034 43EA0123 orr r3, r3, r1, lsl #8
1740 0038 1360 str r3, [r2]
1741 .LVL152:
1546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* START AUTOMATIC SYNCHRONIZATION*/
1548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Enable Automatic trimming & Frequency error counter */
1550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
1742 .loc 1 1550 0
1743 003a 1368 ldr r3, [r2]
1744 003c 43F06003 orr r3, r3, #96
1745 0040 1360 str r3, [r2]
1551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1746 .loc 1 1551 0
1747 0042 30BC pop {r4, r5}
1748 .LCFI23:
1749 .cfi_restore 5
1750 .cfi_restore 4
1751 .cfi_def_cfa_offset 0
1752 0044 7047 bx lr
1753 .L333:
1754 0046 00BF .align 2
1755 .L332:
1756 0048 00100240 .word 1073876992
1757 004c 00200040 .word 1073750016
1758 .cfi_endproc
1759 .LFE339:
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 62
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1761 .section .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate,"ax",%progbits
1762 .align 1
1763 .p2align 2,,3
1764 .global HAL_RCCEx_CRSSoftwareSynchronizationGenerate
1765 .syntax unified
1766 .thumb
1767 .thumb_func
1768 .fpu fpv4-sp-d16
1770 HAL_RCCEx_CRSSoftwareSynchronizationGenerate:
1771 .LFB340:
1552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Generate the software synchronization event
1555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
1558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1772 .loc 1 1558 0
1773 .cfi_startproc
1774 @ args = 0, pretend = 0, frame = 0
1775 @ frame_needed = 0, uses_anonymous_args = 0
1776 @ link register save eliminated.
1559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** SET_BIT(CRS->CR, CRS_CR_SWSYNC);
1777 .loc 1 1559 0
1778 0000 024A ldr r2, .L335
1779 0002 1368 ldr r3, [r2]
1780 0004 43F08003 orr r3, r3, #128
1781 0008 1360 str r3, [r2]
1560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1782 .loc 1 1560 0
1783 000a 7047 bx lr
1784 .L336:
1785 .align 2
1786 .L335:
1787 000c 00200040 .word 1073750016
1788 .cfi_endproc
1789 .LFE340:
1791 .section .text.HAL_RCCEx_CRSGetSynchronizationInfo,"ax",%progbits
1792 .align 1
1793 .p2align 2,,3
1794 .global HAL_RCCEx_CRSGetSynchronizationInfo
1795 .syntax unified
1796 .thumb
1797 .thumb_func
1798 .fpu fpv4-sp-d16
1800 HAL_RCCEx_CRSGetSynchronizationInfo:
1801 .LFB341:
1561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Return synchronization info
1564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
1565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
1568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1802 .loc 1 1568 0
1803 .cfi_startproc
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 63
aggiunta cod
2021-07-02 22:19:04 +02:00
1804 @ args = 0, pretend = 0, frame = 0
1805 @ frame_needed = 0, uses_anonymous_args = 0
1806 @ link register save eliminated.
1807 .LVL153:
1569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check the parameter */
1570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** assert_param(pSynchroInfo != (void *)NULL);
1571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get the reload value */
1573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
1808 .loc 1 1573 0
1809 0000 074B ldr r3, .L338
1810 0002 5A68 ldr r2, [r3, #4]
1811 0004 92B2 uxth r2, r2
1812 0006 0260 str r2, [r0]
1574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get HSI48 oscillator smooth trimming */
1576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
1813 .loc 1 1576 0
1814 0008 1A68 ldr r2, [r3]
1815 000a C2F30622 ubfx r2, r2, #8, #7
1816 000e 4260 str r2, [r0, #4]
1577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get Frequency error capture */
1579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
1817 .loc 1 1579 0
1818 0010 9A68 ldr r2, [r3, #8]
1819 0012 120C lsrs r2, r2, #16
1820 0014 8260 str r2, [r0, #8]
1580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get Frequency error direction */
1582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
1821 .loc 1 1582 0
1822 0016 9B68 ldr r3, [r3, #8]
1823 0018 03F40043 and r3, r3, #32768
1824 001c C360 str r3, [r0, #12]
1583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1825 .loc 1 1583 0
1826 001e 7047 bx lr
1827 .L339:
1828 .align 2
1829 .L338:
1830 0020 00200040 .word 1073750016
1831 .cfi_endproc
1832 .LFE341:
1834 .section .text.HAL_RCCEx_CRSWaitSynchronization,"ax",%progbits
1835 .align 1
1836 .p2align 2,,3
1837 .global HAL_RCCEx_CRSWaitSynchronization
1838 .syntax unified
1839 .thumb
1840 .thumb_func
1841 .fpu fpv4-sp-d16
1843 HAL_RCCEx_CRSWaitSynchronization:
1844 .LFB342:
1584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Wait for CRS Synchronization status.
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 64
aggiunta cod
2021-07-02 22:19:04 +02:00
1587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param Timeout Duration of the timeout
1588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
1589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * frequency.
1590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
1591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval Combination of Synchronization status
1592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * This parameter can be a combination of the following values:
1593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TIMEOUT
1594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCOK
1595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCWARN
1596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCERR
1597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCMISS
1598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TRIMOVF
1599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
1601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1845 .loc 1 1601 0
1846 .cfi_startproc
1847 @ args = 0, pretend = 0, frame = 0
1848 @ frame_needed = 0, uses_anonymous_args = 0
1849 .LVL154:
1850 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr}
1851 .LCFI24:
1852 .cfi_def_cfa_offset 24
1853 .cfi_offset 4, -24
1854 .cfi_offset 5, -20
1855 .cfi_offset 6, -16
1856 .cfi_offset 7, -12
1857 .cfi_offset 8, -8
1858 .cfi_offset 14, -4
1859 .loc 1 1601 0
1860 0004 0546 mov r5, r0
1602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t crsstatus = RCC_CRS_NONE;
1603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t tickstart;
1604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get timeout */
1606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** tickstart = HAL_GetTick();
1861 .loc 1 1606 0
1862 0006 FFF7FEFF bl HAL_GetTick
1863 .LVL155:
1864 000a 6B1C adds r3, r5, #1
1865 000c 34D1 bne .L341
1607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Wait for CRS flag or timeout detection */
1609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** do
1610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(Timeout != HAL_MAX_DELAY)
1612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
1614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crsstatus = RCC_CRS_TIMEOUT;
1616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS SYNCOK flag */
1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
1866 .loc 1 1619 0
1867 000e 574B ldr r3, .L420
1620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 65
aggiunta cod
2021-07-02 22:19:04 +02:00
1621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* CRS SYNC event OK */
1622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCOK;
1623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS SYNC event OK bit */
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
1868 .loc 1 1625 0
1869 0010 0126 movs r6, #1
1626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS SYNCWARN flag */
1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
1630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* CRS SYNC warning */
1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCWARN;
1633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS SYNCWARN bit */
1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
1870 .loc 1 1635 0
1871 0012 0225 movs r5, #2
1872 .LVL156:
1636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS TRIM overflow flag */
1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
1640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* CRS SYNC Error */
1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_TRIMOVF;
1643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS Error bit */
1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
1873 .loc 1 1645 0
1874 0014 0421 movs r1, #4
1646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS Error flag */
1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
1650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* CRS SYNC Error */
1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCERR;
1653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS Error bit */
1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
1656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS SYNC Missed flag */
1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
1660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* CRS SYNC Missed */
1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCMISS;
1663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS SYNC Missed bit */
1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
1666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS Expected SYNC flag */
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
1670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 66
aggiunta cod
2021-07-02 22:19:04 +02:00
1671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* frequency error counter reached a zero value */
1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
1875 .loc 1 1672 0
1876 0016 0824 movs r4, #8
1877 .LVL157:
1878 .L351:
1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1879 .loc 1 1619 0
1880 0018 9868 ldr r0, [r3, #8]
1881 001a 10F00100 ands r0, r0, #1
1882 .LVL158:
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1883 .loc 1 1625 0
1884 001e 18BF it ne
1885 0020 DE60 strne r6, [r3, #12]
1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1886 .loc 1 1629 0
1887 0022 9A68 ldr r2, [r3, #8]
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1888 .loc 1 1625 0
1889 0024 18BF it ne
1890 0026 0220 movne r0, #2
1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1891 .loc 1 1629 0
1892 0028 9707 lsls r7, r2, #30
1893 .LVL159:
1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1894 .loc 1 1635 0
1895 002a 48BF it mi
1896 002c DD60 strmi r5, [r3, #12]
1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1897 .loc 1 1639 0
1898 002e 9A68 ldr r2, [r3, #8]
1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1899 .loc 1 1632 0
1900 0030 48BF it mi
1901 0032 40F00400 orrmi r0, r0, #4
1902 .LVL160:
1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1903 .loc 1 1639 0
1904 0036 5205 lsls r2, r2, #21
1905 .LVL161:
1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1906 .loc 1 1645 0
1907 0038 48BF it mi
1908 003a D960 strmi r1, [r3, #12]
1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1909 .loc 1 1649 0
1910 003c 9A68 ldr r2, [r3, #8]
1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1911 .loc 1 1642 0
1912 003e 48BF it mi
1913 0040 40F02000 orrmi r0, r0, #32
1914 .LVL162:
1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1915 .loc 1 1649 0
1916 0044 D705 lsls r7, r2, #23
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 67
aggiunta cod
2021-07-02 22:19:04 +02:00
1917 .LVL163:
1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1918 .loc 1 1655 0
1919 0046 48BF it mi
1920 0048 D960 strmi r1, [r3, #12]
1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1921 .loc 1 1659 0
1922 004a 9A68 ldr r2, [r3, #8]
1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1923 .loc 1 1652 0
1924 004c 48BF it mi
1925 004e 40F00800 orrmi r0, r0, #8
1926 .LVL164:
1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1927 .loc 1 1659 0
1928 0052 9205 lsls r2, r2, #22
1929 0054 0AD5 bpl .L418
1930 .LVL165:
1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1931 .loc 1 1665 0
1932 0056 D960 str r1, [r3, #12]
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1933 .loc 1 1669 0
1934 0058 9A68 ldr r2, [r3, #8]
1935 005a 1207 lsls r2, r2, #28
1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1936 .loc 1 1662 0
1937 005c 40F01000 orr r0, r0, #16
1938 .LVL166:
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1939 .loc 1 1669 0
1940 0060 02D5 bpl .L340
1941 .LVL167:
1942 .L349:
1943 .loc 1 1672 0
1944 0062 DC60 str r4, [r3, #12]
1673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** } while(RCC_CRS_NONE == crsstatus);
1945 .loc 1 1674 0
1946 0064 0028 cmp r0, #0
1947 0066 D7D0 beq .L351
1948 .L340:
1675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** return crsstatus;
1677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1949 .loc 1 1677 0
1950 0068 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
1951 .L418:
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1952 .loc 1 1669 0
1953 006c 9A68 ldr r2, [r3, #8]
1954 006e 1707 lsls r7, r2, #28
1955 0070 F7D4 bmi .L349
1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1956 .loc 1 1674 0
1957 0072 0028 cmp r0, #0
1958 0074 D0D0 beq .L351
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 68
aggiunta cod
2021-07-02 22:19:04 +02:00
1959 0076 F7E7 b .L340
1960 .LVL168:
1961 .L341:
1962 0078 002D cmp r5, #0
1963 007a 38D0 beq .L353
1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1964 .loc 1 1619 0
1965 007c 3B4C ldr r4, .L420
1966 007e 0646 mov r6, r0
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1967 .loc 1 1625 0
1968 0080 4FF00108 mov r8, #1
1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1969 .loc 1 1635 0
1970 0084 0227 movs r7, #2
1971 .LVL169:
1972 .L363:
1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1973 .loc 1 1613 0
1974 0086 FFF7FEFF bl HAL_GetTick
1975 .LVL170:
1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1976 .loc 1 1619 0
1977 008a A368 ldr r3, [r4, #8]
1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1978 .loc 1 1613 0
1979 008c 801B subs r0, r0, r6
1980 008e 8542 cmp r5, r0
1981 0090 2BBF itete cs
1982 0092 0222 movcs r2, #2
1983 0094 0322 movcc r2, #3
1984 0096 0020 movcs r0, #0
1985 0098 0120 movcc r0, #1
1986 .LVL171:
1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1987 .loc 1 1619 0
1988 009a DB07 lsls r3, r3, #31
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1989 .loc 1 1625 0
1990 009c 48BF it mi
1991 009e C4F80C80 strmi r8, [r4, #12]
1992 .LVL172:
1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1993 .loc 1 1629 0
1994 00a2 A368 ldr r3, [r4, #8]
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1995 .loc 1 1625 0
1996 00a4 48BF it mi
1997 00a6 1046 movmi r0, r2
1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1998 .loc 1 1629 0
1999 00a8 9907 lsls r1, r3, #30
2000 .LVL173:
1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2001 .loc 1 1635 0
2002 00aa 48BF it mi
2003 00ac E760 strmi r7, [r4, #12]
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 69
aggiunta cod
2021-07-02 22:19:04 +02:00
1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2004 .loc 1 1639 0
2005 00ae A368 ldr r3, [r4, #8]
1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2006 .loc 1 1632 0
2007 00b0 48BF it mi
2008 00b2 40F00400 orrmi r0, r0, #4
2009 .LVL174:
1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2010 .loc 1 1639 0
2011 00b6 5A05 lsls r2, r3, #21
2012 00b8 03D5 bpl .L357
2013 .LVL175:
1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2014 .loc 1 1645 0
2015 00ba 0423 movs r3, #4
1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2016 .loc 1 1642 0
2017 00bc 40F02000 orr r0, r0, #32
2018 .LVL176:
1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2019 .loc 1 1645 0
2020 00c0 E360 str r3, [r4, #12]
2021 .LVL177:
2022 .L357:
1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2023 .loc 1 1649 0
2024 00c2 A368 ldr r3, [r4, #8]
2025 00c4 DB05 lsls r3, r3, #23
2026 00c6 03D5 bpl .L358
2027 .LVL178:
1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2028 .loc 1 1655 0
2029 00c8 0423 movs r3, #4
1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2030 .loc 1 1652 0
2031 00ca 40F00800 orr r0, r0, #8
2032 .LVL179:
1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2033 .loc 1 1655 0
2034 00ce E360 str r3, [r4, #12]
2035 .LVL180:
2036 .L358:
1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2037 .loc 1 1659 0
2038 00d0 A368 ldr r3, [r4, #8]
2039 00d2 9905 lsls r1, r3, #22
2040 00d4 3ED5 bpl .L419
2041 .LVL181:
1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2042 .loc 1 1665 0
2043 00d6 0423 movs r3, #4
2044 00d8 E360 str r3, [r4, #12]
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2045 .loc 1 1669 0
2046 00da A368 ldr r3, [r4, #8]
2047 00dc 1B07 lsls r3, r3, #28
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 70
aggiunta cod
2021-07-02 22:19:04 +02:00
1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2048 .loc 1 1662 0
2049 00de 40F01000 orr r0, r0, #16
2050 .LVL182:
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2051 .loc 1 1669 0
2052 00e2 C1D5 bpl .L340
2053 .LVL183:
2054 .L362:
1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2055 .loc 1 1672 0
2056 00e4 0823 movs r3, #8
2057 00e6 E360 str r3, [r4, #12]
1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2058 .loc 1 1674 0
2059 00e8 0028 cmp r0, #0
2060 00ea CCD0 beq .L363
2061 00ec BCE7 b .L340
2062 .LVL184:
2063 .L353:
1613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2064 .loc 1 1613 0
2065 00ee FFF7FEFF bl HAL_GetTick
2066 .LVL185:
1619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2067 .loc 1 1619 0
2068 00f2 1E4B ldr r3, .L420
2069 00f4 9A68 ldr r2, [r3, #8]
2070 00f6 D707 lsls r7, r2, #31
2071 .LVL186:
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2072 .loc 1 1625 0
2073 00f8 44BF itt mi
2074 00fa 0122 movmi r2, #1
2075 00fc DA60 strmi r2, [r3, #12]
1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2076 .loc 1 1629 0
2077 00fe 1B4B ldr r3, .L420
2078 0100 9A68 ldr r2, [r3, #8]
1625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2079 .loc 1 1625 0
2080 0102 4CBF ite mi
2081 0104 0320 movmi r0, #3
2082 .LVL187:
2083 0106 0120 movpl r0, #1
1629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2084 .loc 1 1629 0
2085 0108 9607 lsls r6, r2, #30
2086 010a 03D5 bpl .L365
2087 .LVL188:
1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2088 .loc 1 1635 0
2089 010c 0222 movs r2, #2
1632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2090 .loc 1 1632 0
2091 010e 40F00400 orr r0, r0, #4
2092 .LVL189:
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 71
aggiunta cod
2021-07-02 22:19:04 +02:00
1635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2093 .loc 1 1635 0
2094 0112 DA60 str r2, [r3, #12]
2095 .LVL190:
2096 .L365:
1639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2097 .loc 1 1639 0
2098 0114 154B ldr r3, .L420
2099 0116 9A68 ldr r2, [r3, #8]
2100 0118 5505 lsls r5, r2, #21
2101 .LVL191:
2102 011a 03D5 bpl .L366
2103 .LVL192:
1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2104 .loc 1 1645 0
2105 011c 0422 movs r2, #4
1642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2106 .loc 1 1642 0
2107 011e 40F02000 orr r0, r0, #32
2108 .LVL193:
1645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2109 .loc 1 1645 0
2110 0122 DA60 str r2, [r3, #12]
2111 .LVL194:
2112 .L366:
1649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2113 .loc 1 1649 0
2114 0124 114B ldr r3, .L420
2115 0126 9A68 ldr r2, [r3, #8]
2116 0128 D405 lsls r4, r2, #23
2117 012a 03D5 bpl .L367
2118 .LVL195:
1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2119 .loc 1 1655 0
2120 012c 0422 movs r2, #4
1652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2121 .loc 1 1652 0
2122 012e 40F00800 orr r0, r0, #8
2123 .LVL196:
1655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2124 .loc 1 1655 0
2125 0132 DA60 str r2, [r3, #12]
2126 .LVL197:
2127 .L367:
1659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2128 .loc 1 1659 0
2129 0134 0D4B ldr r3, .L420
2130 0136 9A68 ldr r2, [r3, #8]
2131 0138 9105 lsls r1, r2, #22
2132 013a 11D5 bpl .L368
2133 .LVL198:
1665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2134 .loc 1 1665 0
2135 013c 0422 movs r2, #4
2136 013e DA60 str r2, [r3, #12]
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2137 .loc 1 1669 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 72
aggiunta cod
2021-07-02 22:19:04 +02:00
2138 0140 9B68 ldr r3, [r3, #8]
2139 0142 1A07 lsls r2, r3, #28
1662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2140 .loc 1 1662 0
2141 0144 40F01000 orr r0, r0, #16
2142 .LVL199:
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2143 .loc 1 1669 0
2144 0148 8ED5 bpl .L340
2145 .LVL200:
2146 .L369:
1672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2147 .loc 1 1672 0 discriminator 2
2148 014a 084B ldr r3, .L420
2149 014c 0822 movs r2, #8
2150 014e DA60 str r2, [r3, #12]
2151 .loc 1 1677 0 discriminator 2
2152 0150 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
2153 .LVL201:
2154 .L419:
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2155 .loc 1 1669 0
2156 0154 A368 ldr r3, [r4, #8]
2157 0156 1A07 lsls r2, r3, #28
2158 0158 C4D4 bmi .L362
1674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2159 .loc 1 1674 0
2160 015a 0028 cmp r0, #0
2161 015c 93D0 beq .L363
2162 015e 83E7 b .L340
2163 .LVL202:
2164 .L368:
1669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2165 .loc 1 1669 0
2166 0160 9B68 ldr r3, [r3, #8]
2167 0162 1B07 lsls r3, r3, #28
2168 0164 F1D4 bmi .L369
2169 .loc 1 1677 0
2170 0166 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
2171 .L421:
2172 016a 00BF .align 2
2173 .L420:
2174 016c 00200040 .word 1073750016
2175 .cfi_endproc
2176 .LFE342:
2178 .section .text.HAL_RCCEx_CRS_SyncOkCallback,"ax",%progbits
2179 .align 1
2180 .p2align 2,,3
2181 .weak HAL_RCCEx_CRS_SyncOkCallback
2182 .syntax unified
2183 .thumb
2184 .thumb_func
2185 .fpu fpv4-sp-d16
2187 HAL_RCCEx_CRS_SyncOkCallback:
2188 .LFB349:
2189 .cfi_startproc
2190 @ args = 0, pretend = 0, frame = 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 73
aggiunta cod
2021-07-02 22:19:04 +02:00
2191 @ frame_needed = 0, uses_anonymous_args = 0
2192 @ link register save eliminated.
2193 0000 7047 bx lr
2194 .cfi_endproc
2195 .LFE349:
2197 0002 00BF .section .text.HAL_RCCEx_CRS_SyncWarnCallback,"ax",%progbits
2198 .align 1
2199 .p2align 2,,3
2200 .weak HAL_RCCEx_CRS_SyncWarnCallback
2201 .syntax unified
2202 .thumb
2203 .thumb_func
2204 .fpu fpv4-sp-d16
2206 HAL_RCCEx_CRS_SyncWarnCallback:
2207 .LFB351:
2208 .cfi_startproc
2209 @ args = 0, pretend = 0, frame = 0
2210 @ frame_needed = 0, uses_anonymous_args = 0
2211 @ link register save eliminated.
2212 0000 7047 bx lr
2213 .cfi_endproc
2214 .LFE351:
2216 0002 00BF .section .text.HAL_RCCEx_CRS_ExpectedSyncCallback,"ax",%progbits
2217 .align 1
2218 .p2align 2,,3
2219 .weak HAL_RCCEx_CRS_ExpectedSyncCallback
2220 .syntax unified
2221 .thumb
2222 .thumb_func
2223 .fpu fpv4-sp-d16
2225 HAL_RCCEx_CRS_ExpectedSyncCallback:
2226 .LFB353:
2227 .cfi_startproc
2228 @ args = 0, pretend = 0, frame = 0
2229 @ frame_needed = 0, uses_anonymous_args = 0
2230 @ link register save eliminated.
2231 0000 7047 bx lr
2232 .cfi_endproc
2233 .LFE353:
2235 0002 00BF .section .text.HAL_RCCEx_CRS_ErrorCallback,"ax",%progbits
2236 .align 1
2237 .p2align 2,,3
2238 .weak HAL_RCCEx_CRS_ErrorCallback
2239 .syntax unified
2240 .thumb
2241 .thumb_func
2242 .fpu fpv4-sp-d16
2244 HAL_RCCEx_CRS_ErrorCallback:
2245 .LFB347:
1678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief Handle the Clock Recovery System interrupt request.
1681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval None
1682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** void HAL_RCCEx_CRS_IRQHandler(void)
1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t crserror = RCC_CRS_NONE;
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 74
aggiunta cod
2021-07-02 22:19:04 +02:00
1686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Get current IT flags and IT sources values */
1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t itflags = READ_REG(CRS->ISR);
1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR);
1689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS SYNCOK flag */
1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
1692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS SYNC event OK flag */
1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
1695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* user callback */
1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_SyncOkCallback();
1698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS SYNCWARN flag */
1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
1701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS SYNCWARN flag */
1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
1704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* user callback */
1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_SyncWarnCallback();
1707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS Expected SYNC flag */
1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
1710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* frequency error counter reached a zero value */
1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
1713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* user callback */
1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_ExpectedSyncCallback();
1716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Check CRS Error flags */
1718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** else
1719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
1721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
1723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crserror |= RCC_CRS_SYNCERR;
1725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
1727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crserror |= RCC_CRS_SYNCMISS;
1729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
1731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** crserror |= RCC_CRS_TRIMOVF;
1733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Clear CRS Error flags */
1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
1737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* user error callback */
1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_ErrorCallback(crserror);
1740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
opamp, peak detect
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ARM GAS /tmp/ccZxUtAY.s page 75
aggiunta cod
2021-07-02 22:19:04 +02:00
1743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
1746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval none
1747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
1749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
1751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
1752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
1757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval none
1758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
1760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
1762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
1763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
1768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval none
1769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
1771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
1772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
1773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
1774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
1776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /**
1778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System Error interrupt callback.
1779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @param Error Combination of Error status.
1780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * This parameter can be a combination of the following values:
1781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCERR
1782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCMISS
1783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TRIMOVF
1784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** * @retval none
1785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
1786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
1787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2246 .loc 1 1787 0
2247 .cfi_startproc
2248 @ args = 0, pretend = 0, frame = 0
2249 @ frame_needed = 0, uses_anonymous_args = 0
2250 @ link register save eliminated.
2251 .LVL203:
1788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* Prevent unused argument(s) compilation warning */
1789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** UNUSED(Error);
1790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
1791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
1792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
1793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** */
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 76
aggiunta cod
2021-07-02 22:19:04 +02:00
1794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2252 .loc 1 1794 0
2253 0000 7047 bx lr
2254 .cfi_endproc
2255 .LFE347:
2257 0002 00BF .section .text.HAL_RCCEx_CRS_IRQHandler,"ax",%progbits
2258 .align 1
2259 .p2align 2,,3
2260 .global HAL_RCCEx_CRS_IRQHandler
2261 .syntax unified
2262 .thumb
2263 .thumb_func
2264 .fpu fpv4-sp-d16
2266 HAL_RCCEx_CRS_IRQHandler:
2267 .LFB343:
1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t crserror = RCC_CRS_NONE;
2268 .loc 1 1684 0
2269 .cfi_startproc
2270 @ args = 0, pretend = 0, frame = 0
2271 @ frame_needed = 0, uses_anonymous_args = 0
2272 .LVL204:
1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR);
2273 .loc 1 1687 0
2274 0000 214A ldr r2, .L465
1684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t crserror = RCC_CRS_NONE;
2275 .loc 1 1684 0
2276 0002 38B5 push {r3, r4, r5, lr}
2277 .LCFI25:
2278 .cfi_def_cfa_offset 16
2279 .cfi_offset 3, -16
2280 .cfi_offset 4, -12
2281 .cfi_offset 5, -8
2282 .cfi_offset 14, -4
1687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR);
2283 .loc 1 1687 0
2284 0004 9368 ldr r3, [r2, #8]
2285 .LVL205:
1688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2286 .loc 1 1688 0
2287 0006 1168 ldr r1, [r2]
2288 .LVL206:
1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2289 .loc 1 1691 0
2290 0008 13F0010F tst r3, #1
2291 000c 02D0 beq .L427
1691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2292 .loc 1 1691 0 is_stmt 0 discriminator 1
2293 000e 11F0010F tst r1, #1
2294 0012 28D1 bne .L462
2295 .L427:
1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2296 .loc 1 1700 0 is_stmt 1
2297 0014 9A07 lsls r2, r3, #30
2298 0016 01D5 bpl .L429
1700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2299 .loc 1 1700 0 is_stmt 0 discriminator 1
2300 0018 8A07 lsls r2, r1, #30
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 77
aggiunta cod
2021-07-02 22:19:04 +02:00
2301 001a 29D4 bmi .L463
2302 .L429:
1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2303 .loc 1 1709 0 is_stmt 1
2304 001c 1A07 lsls r2, r3, #28
2305 001e 01D5 bpl .L430
1709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2306 .loc 1 1709 0 is_stmt 0 discriminator 1
2307 0020 0A07 lsls r2, r1, #28
2308 0022 2BD4 bmi .L464
2309 .L430:
1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2310 .loc 1 1720 0 is_stmt 1
2311 0024 5A07 lsls r2, r3, #29
2312 0026 1DD5 bpl .L426
1720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2313 .loc 1 1720 0 is_stmt 0 discriminator 1
2314 0028 4A07 lsls r2, r1, #29
2315 002a 1BD5 bpl .L426
1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2316 .loc 1 1722 0 is_stmt 1
2317 002c 03F48072 and r2, r3, #256
2318 0030 002A cmp r2, #0
1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2319 .loc 1 1726 0
2320 0032 03F40071 and r1, r3, #512
2321 .LVL207:
1722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2322 .loc 1 1722 0
2323 0036 1DBF ittte ne
2324 0038 2820 movne r0, #40
2325 003a 1824 movne r4, #24
2326 003c 0822 movne r2, #8
2327 003e 2020 moveq r0, #32
2328 0040 11BF iteee ne
2329 0042 3825 movne r5, #56
2330 0044 1024 moveq r4, #16
2331 0046 0022 moveq r2, #0
2332 .LVL208:
2333 0048 3025 moveq r5, #48
1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2334 .loc 1 1726 0
2335 004a 0029 cmp r1, #0
1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2336 .loc 1 1736 0
2337 004c 0E49 ldr r1, .L465
1726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2338 .loc 1 1726 0
2339 004e 1CBF itt ne
2340 0050 2246 movne r2, r4
2341 .LVL209:
2342 0052 2846 movne r0, r5
1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2343 .loc 1 1736 0
2344 0054 0424 movs r4, #4
1730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** {
2345 .loc 1 1730 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 78
aggiunta cod
2021-07-02 22:19:04 +02:00
2346 0056 13F4806F tst r3, #1024
2347 .LVL210:
1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2348 .loc 1 1739 0
2349 005a 08BF it eq
2350 005c 1046 moveq r0, r2
2351 .LVL211:
1736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2352 .loc 1 1736 0
2353 005e CC60 str r4, [r1, #12]
1739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2354 .loc 1 1739 0
2355 0060 FFF7FEFF bl HAL_RCCEx_CRS_ErrorCallback
2356 .LVL212:
2357 .L426:
1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2358 .loc 1 1742 0
2359 0064 38BD pop {r3, r4, r5, pc}
2360 .LVL213:
2361 .L462:
1694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2362 .loc 1 1694 0
2363 0066 0123 movs r3, #1
2364 .LVL214:
2365 0068 D360 str r3, [r2, #12]
1697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2366 .loc 1 1697 0
2367 006a FFF7FEFF bl HAL_RCCEx_CRS_SyncOkCallback
2368 .LVL215:
1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2369 .loc 1 1742 0
2370 006e 38BD pop {r3, r4, r5, pc}
2371 .LVL216:
2372 .L463:
1703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2373 .loc 1 1703 0
2374 0070 054B ldr r3, .L465
2375 .LVL217:
2376 0072 0222 movs r2, #2
2377 0074 DA60 str r2, [r3, #12]
1706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2378 .loc 1 1706 0
2379 0076 FFF7FEFF bl HAL_RCCEx_CRS_SyncWarnCallback
2380 .LVL218:
1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2381 .loc 1 1742 0
2382 007a 38BD pop {r3, r4, r5, pc}
2383 .LVL219:
2384 .L464:
1712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2385 .loc 1 1712 0
2386 007c 024B ldr r3, .L465
2387 .LVL220:
2388 007e 0822 movs r2, #8
2389 0080 DA60 str r2, [r3, #12]
1715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c **** }
2390 .loc 1 1715 0
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 79
aggiunta cod
2021-07-02 22:19:04 +02:00
2391 0082 FFF7FEFF bl HAL_RCCEx_CRS_ExpectedSyncCallback
2392 .LVL221:
1742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ****
2393 .loc 1 1742 0
2394 0086 38BD pop {r3, r4, r5, pc}
2395 .L466:
2396 .align 2
2397 .L465:
2398 0088 00200040 .word 1073750016
2399 .cfi_endproc
2400 .LFE343:
2402 .text
2403 .Letext0:
2404 .file 2 "/usr/include/newlib/machine/_default_types.h"
2405 .file 3 "/usr/include/newlib/sys/_stdint.h"
2406 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
2407 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
2408 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
2409 .file 7 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
2410 .file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
2411 .file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"
2412 .file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
2413 .file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
2414 .file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
2415 .file 13 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
2416 .file 14 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"
2417 .file 15 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
opamp, peak detect
2021-07-03 18:17:05 +02:00
ARM GAS /tmp/ccZxUtAY.s page 80
aggiunta cod
2021-07-02 22:19:04 +02:00
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32g4xx_hal_rcc_ex.c
opamp, peak detect
2021-07-03 18:17:05 +02:00
/tmp/ccZxUtAY.s:16 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 $t
/tmp/ccZxUtAY.s:24 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 HAL_RCCEx_PeriphCLKConfig
/tmp/ccZxUtAY.s:454 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000290 $d
/tmp/ccZxUtAY.s:460 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 $t
/tmp/ccZxUtAY.s:468 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 HAL_RCCEx_GetPeriphCLKConfig
/tmp/ccZxUtAY.s:550 .text.HAL_RCCEx_GetPeriphCLKConfig:00000000000000a8 $d
/tmp/ccZxUtAY.s:556 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 $t
/tmp/ccZxUtAY.s:564 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 HAL_RCCEx_GetPeriphCLKFreq
/tmp/ccZxUtAY.s:1039 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000318 $d
/tmp/ccZxUtAY.s:1047 .text.HAL_RCCEx_GetPeriphCLKFreq:000000000000032c $t
/tmp/ccZxUtAY.s:1250 .text.HAL_RCCEx_GetPeriphCLKFreq:000000000000042c $d
/tmp/ccZxUtAY.s:1258 .text.HAL_RCCEx_EnableLSECSS:0000000000000000 $t
/tmp/ccZxUtAY.s:1266 .text.HAL_RCCEx_EnableLSECSS:0000000000000000 HAL_RCCEx_EnableLSECSS
/tmp/ccZxUtAY.s:1283 .text.HAL_RCCEx_EnableLSECSS:0000000000000010 $d
/tmp/ccZxUtAY.s:1288 .text.HAL_RCCEx_DisableLSECSS:0000000000000000 $t
/tmp/ccZxUtAY.s:1296 .text.HAL_RCCEx_DisableLSECSS:0000000000000000 HAL_RCCEx_DisableLSECSS
/tmp/ccZxUtAY.s:1317 .text.HAL_RCCEx_DisableLSECSS:0000000000000018 $d
/tmp/ccZxUtAY.s:1322 .text.HAL_RCCEx_EnableLSECSS_IT:0000000000000000 $t
/tmp/ccZxUtAY.s:1330 .text.HAL_RCCEx_EnableLSECSS_IT:0000000000000000 HAL_RCCEx_EnableLSECSS_IT
/tmp/ccZxUtAY.s:1362 .text.HAL_RCCEx_EnableLSECSS_IT:000000000000002c $d
/tmp/ccZxUtAY.s:1368 .text.HAL_RCCEx_LSECSS_Callback:0000000000000000 $t
/tmp/ccZxUtAY.s:1376 .text.HAL_RCCEx_LSECSS_Callback:0000000000000000 HAL_RCCEx_LSECSS_Callback
/tmp/ccZxUtAY.s:1389 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000000 $t
/tmp/ccZxUtAY.s:1397 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000000 HAL_RCCEx_LSECSS_IRQHandler
/tmp/ccZxUtAY.s:1427 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000018 $d
/tmp/ccZxUtAY.s:1432 .text.HAL_RCCEx_EnableLSCO:0000000000000000 $t
/tmp/ccZxUtAY.s:1440 .text.HAL_RCCEx_EnableLSCO:0000000000000000 HAL_RCCEx_EnableLSCO
/tmp/ccZxUtAY.s:1567 .text.HAL_RCCEx_EnableLSCO:0000000000000098 $d
/tmp/ccZxUtAY.s:1573 .text.HAL_RCCEx_DisableLSCO:0000000000000000 $t
/tmp/ccZxUtAY.s:1581 .text.HAL_RCCEx_DisableLSCO:0000000000000000 HAL_RCCEx_DisableLSCO
/tmp/ccZxUtAY.s:1675 .text.HAL_RCCEx_DisableLSCO:000000000000006c $d
/tmp/ccZxUtAY.s:1681 .text.HAL_RCCEx_CRSConfig:0000000000000000 $t
/tmp/ccZxUtAY.s:1689 .text.HAL_RCCEx_CRSConfig:0000000000000000 HAL_RCCEx_CRSConfig
/tmp/ccZxUtAY.s:1756 .text.HAL_RCCEx_CRSConfig:0000000000000048 $d
/tmp/ccZxUtAY.s:1762 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:0000000000000000 $t
/tmp/ccZxUtAY.s:1770 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:0000000000000000 HAL_RCCEx_CRSSoftwareSynchronizationGenerate
/tmp/ccZxUtAY.s:1787 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:000000000000000c $d
/tmp/ccZxUtAY.s:1792 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000000 $t
/tmp/ccZxUtAY.s:1800 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000000 HAL_RCCEx_CRSGetSynchronizationInfo
/tmp/ccZxUtAY.s:1830 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000020 $d
/tmp/ccZxUtAY.s:1835 .text.HAL_RCCEx_CRSWaitSynchronization:0000000000000000 $t
/tmp/ccZxUtAY.s:1843 .text.HAL_RCCEx_CRSWaitSynchronization:0000000000000000 HAL_RCCEx_CRSWaitSynchronization
/tmp/ccZxUtAY.s:2174 .text.HAL_RCCEx_CRSWaitSynchronization:000000000000016c $d
/tmp/ccZxUtAY.s:2179 .text.HAL_RCCEx_CRS_SyncOkCallback:0000000000000000 $t
/tmp/ccZxUtAY.s:2187 .text.HAL_RCCEx_CRS_SyncOkCallback:0000000000000000 HAL_RCCEx_CRS_SyncOkCallback
/tmp/ccZxUtAY.s:2198 .text.HAL_RCCEx_CRS_SyncWarnCallback:0000000000000000 $t
/tmp/ccZxUtAY.s:2206 .text.HAL_RCCEx_CRS_SyncWarnCallback:0000000000000000 HAL_RCCEx_CRS_SyncWarnCallback
/tmp/ccZxUtAY.s:2217 .text.HAL_RCCEx_CRS_ExpectedSyncCallback:0000000000000000 $t
/tmp/ccZxUtAY.s:2225 .text.HAL_RCCEx_CRS_ExpectedSyncCallback:0000000000000000 HAL_RCCEx_CRS_ExpectedSyncCallback
/tmp/ccZxUtAY.s:2236 .text.HAL_RCCEx_CRS_ErrorCallback:0000000000000000 $t
/tmp/ccZxUtAY.s:2244 .text.HAL_RCCEx_CRS_ErrorCallback:0000000000000000 HAL_RCCEx_CRS_ErrorCallback
/tmp/ccZxUtAY.s:2258 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000000 $t
/tmp/ccZxUtAY.s:2266 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000000 HAL_RCCEx_CRS_IRQHandler
/tmp/ccZxUtAY.s:2398 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000088 $d
ARM GAS /tmp/ccZxUtAY.s page 81
aggiunta cod
2021-07-02 22:19:04 +02:00
UNDEFINED SYMBOLS
HAL_GetTick
HAL_RCC_GetPCLK1Freq
HAL_RCC_GetSysClockFreq
HAL_RCC_GetPCLK2Freq
HAL_GPIO_Init
HAL_PWR_EnableBkUpAccess
HAL_PWR_DisableBkUpAccess
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