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This commit is contained in:
nzasch
2021-12-31 04:49:55 +01:00
parent 437171f10f
commit 3552dd2273
163 changed files with 10120 additions and 745579 deletions
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523
codice/build/system_stm32g4xx.lst
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@@ -1,523 +0,0 @@
ARM GAS /tmp/ccjB19iz.s page 1
1 .cpu cortex-m4
2 .eabi_attribute 27, 1
3 .eabi_attribute 28, 1
4 .eabi_attribute 23, 1
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 2
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "system_stm32g4xx.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.SystemInit,"ax",%progbits
16 .align 1
17 .p2align 2,,3
18 .global SystemInit
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu fpv4-sp-d16
24 SystemInit:
25 .LFB329:
26 .file 1 "Core/Src/system_stm32g4xx.c"
1:Core/Src/system_stm32g4xx.c **** /**
2:Core/Src/system_stm32g4xx.c **** ******************************************************************************
3:Core/Src/system_stm32g4xx.c **** * @file system_stm32g4xx.c
4:Core/Src/system_stm32g4xx.c **** * @author MCD Application Team
5:Core/Src/system_stm32g4xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6:Core/Src/system_stm32g4xx.c **** *
7:Core/Src/system_stm32g4xx.c **** * This file provides two functions and one global variable to be called from
8:Core/Src/system_stm32g4xx.c **** * user application:
9:Core/Src/system_stm32g4xx.c **** * - SystemInit(): This function is called at startup just after reset and
10:Core/Src/system_stm32g4xx.c **** * before branch to main program. This call is made inside
11:Core/Src/system_stm32g4xx.c **** * the "startup_stm32g4xx.s" file.
12:Core/Src/system_stm32g4xx.c **** *
13:Core/Src/system_stm32g4xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14:Core/Src/system_stm32g4xx.c **** * by the user application to setup the SysTick
15:Core/Src/system_stm32g4xx.c **** * timer or configure other parameters.
16:Core/Src/system_stm32g4xx.c **** *
17:Core/Src/system_stm32g4xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18:Core/Src/system_stm32g4xx.c **** * be called whenever the core clock is changed
19:Core/Src/system_stm32g4xx.c **** * during program execution.
20:Core/Src/system_stm32g4xx.c **** *
21:Core/Src/system_stm32g4xx.c **** * After each device reset the HSI (16 MHz) is used as system clock source.
22:Core/Src/system_stm32g4xx.c **** * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
23:Core/Src/system_stm32g4xx.c **** * configure the system clock before to branch to main program.
24:Core/Src/system_stm32g4xx.c **** *
25:Core/Src/system_stm32g4xx.c **** * This file configures the system clock as follows:
26:Core/Src/system_stm32g4xx.c **** *=============================================================================
27:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
28:Core/Src/system_stm32g4xx.c **** * System Clock source | HSI
29:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
30:Core/Src/system_stm32g4xx.c **** * SYSCLK(Hz) | 16000000
31:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
32:Core/Src/system_stm32g4xx.c **** * HCLK(Hz) | 16000000
ARM GAS /tmp/ccjB19iz.s page 2
33:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
34:Core/Src/system_stm32g4xx.c **** * AHB Prescaler | 1
35:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
36:Core/Src/system_stm32g4xx.c **** * APB1 Prescaler | 1
37:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
38:Core/Src/system_stm32g4xx.c **** * APB2 Prescaler | 1
39:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
40:Core/Src/system_stm32g4xx.c **** * PLL_M | 1
41:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
42:Core/Src/system_stm32g4xx.c **** * PLL_N | 16
43:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
44:Core/Src/system_stm32g4xx.c **** * PLL_P | 7
45:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
46:Core/Src/system_stm32g4xx.c **** * PLL_Q | 2
47:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
48:Core/Src/system_stm32g4xx.c **** * PLL_R | 2
49:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
50:Core/Src/system_stm32g4xx.c **** * Require 48MHz for RNG | Disabled
51:Core/Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
52:Core/Src/system_stm32g4xx.c **** *=============================================================================
53:Core/Src/system_stm32g4xx.c **** ******************************************************************************
54:Core/Src/system_stm32g4xx.c **** * @attention
55:Core/Src/system_stm32g4xx.c **** *
56:Core/Src/system_stm32g4xx.c **** * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
57:Core/Src/system_stm32g4xx.c **** * All rights reserved.</center></h2>
58:Core/Src/system_stm32g4xx.c **** *
59:Core/Src/system_stm32g4xx.c **** * This software component is licensed by ST under BSD 3-Clause license,
60:Core/Src/system_stm32g4xx.c **** * the "License"; You may not use this file except in compliance with the
61:Core/Src/system_stm32g4xx.c **** * License. You may obtain a copy of the License at:
62:Core/Src/system_stm32g4xx.c **** * opensource.org/licenses/BSD-3-Clause
63:Core/Src/system_stm32g4xx.c **** *
64:Core/Src/system_stm32g4xx.c **** ******************************************************************************
65:Core/Src/system_stm32g4xx.c **** */
66:Core/Src/system_stm32g4xx.c ****
67:Core/Src/system_stm32g4xx.c **** /** @addtogroup CMSIS
68:Core/Src/system_stm32g4xx.c **** * @{
69:Core/Src/system_stm32g4xx.c **** */
70:Core/Src/system_stm32g4xx.c ****
71:Core/Src/system_stm32g4xx.c **** /** @addtogroup stm32g4xx_system
72:Core/Src/system_stm32g4xx.c **** * @{
73:Core/Src/system_stm32g4xx.c **** */
74:Core/Src/system_stm32g4xx.c ****
75:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Includes
76:Core/Src/system_stm32g4xx.c **** * @{
77:Core/Src/system_stm32g4xx.c **** */
78:Core/Src/system_stm32g4xx.c ****
79:Core/Src/system_stm32g4xx.c **** #include "stm32g4xx.h"
80:Core/Src/system_stm32g4xx.c ****
81:Core/Src/system_stm32g4xx.c **** #if !defined (HSE_VALUE)
82:Core/Src/system_stm32g4xx.c **** #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
83:Core/Src/system_stm32g4xx.c **** #endif /* HSE_VALUE */
84:Core/Src/system_stm32g4xx.c ****
85:Core/Src/system_stm32g4xx.c **** #if !defined (HSI_VALUE)
86:Core/Src/system_stm32g4xx.c **** #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
87:Core/Src/system_stm32g4xx.c **** #endif /* HSI_VALUE */
88:Core/Src/system_stm32g4xx.c ****
89:Core/Src/system_stm32g4xx.c **** /**
ARM GAS /tmp/ccjB19iz.s page 3
90:Core/Src/system_stm32g4xx.c **** * @}
91:Core/Src/system_stm32g4xx.c **** */
92:Core/Src/system_stm32g4xx.c ****
93:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_TypesDefinitions
94:Core/Src/system_stm32g4xx.c **** * @{
95:Core/Src/system_stm32g4xx.c **** */
96:Core/Src/system_stm32g4xx.c ****
97:Core/Src/system_stm32g4xx.c **** /**
98:Core/Src/system_stm32g4xx.c **** * @}
99:Core/Src/system_stm32g4xx.c **** */
100:Core/Src/system_stm32g4xx.c ****
101:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Defines
102:Core/Src/system_stm32g4xx.c **** * @{
103:Core/Src/system_stm32g4xx.c **** */
104:Core/Src/system_stm32g4xx.c ****
105:Core/Src/system_stm32g4xx.c **** /************************* Miscellaneous Configuration ************************/
106:Core/Src/system_stm32g4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
107:Core/Src/system_stm32g4xx.c **** Internal SRAM. */
108:Core/Src/system_stm32g4xx.c **** /* #define VECT_TAB_SRAM */
109:Core/Src/system_stm32g4xx.c **** #define VECT_TAB_OFFSET 0x00UL /*!< Vector Table base offset field.
110:Core/Src/system_stm32g4xx.c **** This value must be a multiple of 0x200. */
111:Core/Src/system_stm32g4xx.c **** /******************************************************************************/
112:Core/Src/system_stm32g4xx.c **** /**
113:Core/Src/system_stm32g4xx.c **** * @}
114:Core/Src/system_stm32g4xx.c **** */
115:Core/Src/system_stm32g4xx.c ****
116:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Macros
117:Core/Src/system_stm32g4xx.c **** * @{
118:Core/Src/system_stm32g4xx.c **** */
119:Core/Src/system_stm32g4xx.c ****
120:Core/Src/system_stm32g4xx.c **** /**
121:Core/Src/system_stm32g4xx.c **** * @}
122:Core/Src/system_stm32g4xx.c **** */
123:Core/Src/system_stm32g4xx.c ****
124:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Variables
125:Core/Src/system_stm32g4xx.c **** * @{
126:Core/Src/system_stm32g4xx.c **** */
127:Core/Src/system_stm32g4xx.c **** /* The SystemCoreClock variable is updated in three ways:
128:Core/Src/system_stm32g4xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
129:Core/Src/system_stm32g4xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
130:Core/Src/system_stm32g4xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
131:Core/Src/system_stm32g4xx.c **** Note: If you use this function to configure the system clock; then there
132:Core/Src/system_stm32g4xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
133:Core/Src/system_stm32g4xx.c **** variable is updated automatically.
134:Core/Src/system_stm32g4xx.c **** */
135:Core/Src/system_stm32g4xx.c **** uint32_t SystemCoreClock = HSI_VALUE;
136:Core/Src/system_stm32g4xx.c ****
137:Core/Src/system_stm32g4xx.c **** const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U
138:Core/Src/system_stm32g4xx.c **** const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
139:Core/Src/system_stm32g4xx.c ****
140:Core/Src/system_stm32g4xx.c **** /**
141:Core/Src/system_stm32g4xx.c **** * @}
142:Core/Src/system_stm32g4xx.c **** */
143:Core/Src/system_stm32g4xx.c ****
144:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
145:Core/Src/system_stm32g4xx.c **** * @{
146:Core/Src/system_stm32g4xx.c **** */
ARM GAS /tmp/ccjB19iz.s page 4
147:Core/Src/system_stm32g4xx.c ****
148:Core/Src/system_stm32g4xx.c **** /**
149:Core/Src/system_stm32g4xx.c **** * @}
150:Core/Src/system_stm32g4xx.c **** */
151:Core/Src/system_stm32g4xx.c ****
152:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Functions
153:Core/Src/system_stm32g4xx.c **** * @{
154:Core/Src/system_stm32g4xx.c **** */
155:Core/Src/system_stm32g4xx.c ****
156:Core/Src/system_stm32g4xx.c **** /**
157:Core/Src/system_stm32g4xx.c **** * @brief Setup the microcontroller system.
158:Core/Src/system_stm32g4xx.c **** * @param None
159:Core/Src/system_stm32g4xx.c **** * @retval None
160:Core/Src/system_stm32g4xx.c **** */
161:Core/Src/system_stm32g4xx.c ****
162:Core/Src/system_stm32g4xx.c **** void SystemInit(void)
163:Core/Src/system_stm32g4xx.c **** {
27 .loc 1 163 0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 0
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
164:Core/Src/system_stm32g4xx.c **** /* FPU settings ------------------------------------------------------------*/
165:Core/Src/system_stm32g4xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
166:Core/Src/system_stm32g4xx.c **** SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
32 .loc 1 166 0
33 0000 054B ldr r3, .L3
34 0002 D3F88820 ldr r2, [r3, #136]
167:Core/Src/system_stm32g4xx.c **** #endif
168:Core/Src/system_stm32g4xx.c ****
169:Core/Src/system_stm32g4xx.c **** /* Configure the Vector Table location add offset address ------------------*/
170:Core/Src/system_stm32g4xx.c **** #ifdef VECT_TAB_SRAM
171:Core/Src/system_stm32g4xx.c **** SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
172:Core/Src/system_stm32g4xx.c **** #else
173:Core/Src/system_stm32g4xx.c **** SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
35 .loc 1 173 0
36 0006 4FF00061 mov r1, #134217728
166:Core/Src/system_stm32g4xx.c **** #endif
37 .loc 1 166 0
38 000a 42F47002 orr r2, r2, #15728640
39 000e C3F88820 str r2, [r3, #136]
40 .loc 1 173 0
41 0012 9960 str r1, [r3, #8]
174:Core/Src/system_stm32g4xx.c **** #endif
175:Core/Src/system_stm32g4xx.c **** }
42 .loc 1 175 0
43 0014 7047 bx lr
44 .L4:
45 0016 00BF .align 2
46 .L3:
47 0018 00ED00E0 .word -536810240
48 .cfi_endproc
49 .LFE329:
51 .section .text.SystemCoreClockUpdate,"ax",%progbits
52 .align 1
53 .p2align 2,,3
54 .global SystemCoreClockUpdate
ARM GAS /tmp/ccjB19iz.s page 5
55 .syntax unified
56 .thumb
57 .thumb_func
58 .fpu fpv4-sp-d16
60 SystemCoreClockUpdate:
61 .LFB330:
176:Core/Src/system_stm32g4xx.c ****
177:Core/Src/system_stm32g4xx.c **** /**
178:Core/Src/system_stm32g4xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
179:Core/Src/system_stm32g4xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
180:Core/Src/system_stm32g4xx.c **** * be used by the user application to setup the SysTick timer or configure
181:Core/Src/system_stm32g4xx.c **** * other parameters.
182:Core/Src/system_stm32g4xx.c **** *
183:Core/Src/system_stm32g4xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
184:Core/Src/system_stm32g4xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
185:Core/Src/system_stm32g4xx.c **** * based on this variable will be incorrect.
186:Core/Src/system_stm32g4xx.c **** *
187:Core/Src/system_stm32g4xx.c **** * @note - The system frequency computed by this function is not the real
188:Core/Src/system_stm32g4xx.c **** * frequency in the chip. It is calculated based on the predefined
189:Core/Src/system_stm32g4xx.c **** * constant and the selected clock source:
190:Core/Src/system_stm32g4xx.c **** *
191:Core/Src/system_stm32g4xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
192:Core/Src/system_stm32g4xx.c **** *
193:Core/Src/system_stm32g4xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
194:Core/Src/system_stm32g4xx.c **** *
195:Core/Src/system_stm32g4xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
196:Core/Src/system_stm32g4xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
197:Core/Src/system_stm32g4xx.c **** *
198:Core/Src/system_stm32g4xx.c **** * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
199:Core/Src/system_stm32g4xx.c **** * 16 MHz) but the real value may vary depending on the variations
200:Core/Src/system_stm32g4xx.c **** * in voltage and temperature.
201:Core/Src/system_stm32g4xx.c **** *
202:Core/Src/system_stm32g4xx.c **** * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
203:Core/Src/system_stm32g4xx.c **** * 24 MHz), user has to ensure that HSE_VALUE is same as the real
204:Core/Src/system_stm32g4xx.c **** * frequency of the crystal used. Otherwise, this function may
205:Core/Src/system_stm32g4xx.c **** * have wrong result.
206:Core/Src/system_stm32g4xx.c **** *
207:Core/Src/system_stm32g4xx.c **** * - The result of this function could be not correct when using fractional
208:Core/Src/system_stm32g4xx.c **** * value for HSE crystal.
209:Core/Src/system_stm32g4xx.c **** *
210:Core/Src/system_stm32g4xx.c **** * @param None
211:Core/Src/system_stm32g4xx.c **** * @retval None
212:Core/Src/system_stm32g4xx.c **** */
213:Core/Src/system_stm32g4xx.c **** void SystemCoreClockUpdate(void)
214:Core/Src/system_stm32g4xx.c **** {
62 .loc 1 214 0
63 .cfi_startproc
64 @ args = 0, pretend = 0, frame = 0
65 @ frame_needed = 0, uses_anonymous_args = 0
66 @ link register save eliminated.
215:Core/Src/system_stm32g4xx.c **** uint32_t tmp, pllvco, pllr, pllsource, pllm;
216:Core/Src/system_stm32g4xx.c ****
217:Core/Src/system_stm32g4xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
218:Core/Src/system_stm32g4xx.c **** switch (RCC->CFGR & RCC_CFGR_SWS)
67 .loc 1 218 0
68 0000 1A4A ldr r2, .L14
69 0002 9368 ldr r3, [r2, #8]
ARM GAS /tmp/ccjB19iz.s page 6
70 0004 03F00C03 and r3, r3, #12
71 0008 082B cmp r3, #8
72 000a 10D0 beq .L12
73 000c 0C2B cmp r3, #12
74 000e 11D0 beq .L8
75 0010 042B cmp r3, #4
76 0012 13BF iteet ne
77 0014 1649 ldrne r1, .L14+4
78 0016 174B ldreq r3, .L14+8
79 0018 1549 ldreq r1, .L14+4
80 001a 0B68 ldrne r3, [r1]
81 .L7:
219:Core/Src/system_stm32g4xx.c **** {
220:Core/Src/system_stm32g4xx.c **** case 0x04: /* HSI used as system clock source */
221:Core/Src/system_stm32g4xx.c **** SystemCoreClock = HSI_VALUE;
222:Core/Src/system_stm32g4xx.c **** break;
223:Core/Src/system_stm32g4xx.c ****
224:Core/Src/system_stm32g4xx.c **** case 0x08: /* HSE used as system clock source */
225:Core/Src/system_stm32g4xx.c **** SystemCoreClock = HSE_VALUE;
226:Core/Src/system_stm32g4xx.c **** break;
227:Core/Src/system_stm32g4xx.c ****
228:Core/Src/system_stm32g4xx.c **** case 0x0C: /* PLL used as system clock source */
229:Core/Src/system_stm32g4xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
230:Core/Src/system_stm32g4xx.c **** SYSCLK = PLL_VCO / PLLR
231:Core/Src/system_stm32g4xx.c **** */
232:Core/Src/system_stm32g4xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
233:Core/Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
234:Core/Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
235:Core/Src/system_stm32g4xx.c **** {
236:Core/Src/system_stm32g4xx.c **** pllvco = (HSI_VALUE / pllm);
237:Core/Src/system_stm32g4xx.c **** }
238:Core/Src/system_stm32g4xx.c **** else /* HSE used as PLL clock source */
239:Core/Src/system_stm32g4xx.c **** {
240:Core/Src/system_stm32g4xx.c **** pllvco = (HSE_VALUE / pllm);
241:Core/Src/system_stm32g4xx.c **** }
242:Core/Src/system_stm32g4xx.c **** pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
243:Core/Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
244:Core/Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
245:Core/Src/system_stm32g4xx.c **** break;
246:Core/Src/system_stm32g4xx.c ****
247:Core/Src/system_stm32g4xx.c **** default:
248:Core/Src/system_stm32g4xx.c **** break;
249:Core/Src/system_stm32g4xx.c **** }
250:Core/Src/system_stm32g4xx.c **** /* Compute HCLK clock frequency --------------------------------------------*/
251:Core/Src/system_stm32g4xx.c **** /* Get HCLK prescaler */
252:Core/Src/system_stm32g4xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
82 .loc 1 252 0
83 001c 134A ldr r2, .L14
84 001e 1648 ldr r0, .L14+12
85 0020 9268 ldr r2, [r2, #8]
86 .LVL0:
87 0022 C2F30312 ubfx r2, r2, #4, #4
88 .LVL1:
89 0026 825C ldrb r2, [r0, r2] @ zero_extendqisi2
253:Core/Src/system_stm32g4xx.c **** /* HCLK clock frequency */
254:Core/Src/system_stm32g4xx.c **** SystemCoreClock >>= tmp;
90 .loc 1 254 0
ARM GAS /tmp/ccjB19iz.s page 7
91 0028 D340 lsrs r3, r3, r2
92 002a 0B60 str r3, [r1]
255:Core/Src/system_stm32g4xx.c **** }
93 .loc 1 255 0
94 002c 7047 bx lr
95 .L12:
218:Core/Src/system_stm32g4xx.c **** {
96 .loc 1 218 0
97 002e 134B ldr r3, .L14+16
98 0030 0F49 ldr r1, .L14+4
99 0032 F3E7 b .L7
100 .L8:
232:Core/Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
101 .loc 1 232 0
102 0034 D168 ldr r1, [r2, #12]
103 .LVL2:
233:Core/Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
104 .loc 1 233 0
105 0036 D368 ldr r3, [r2, #12]
232:Core/Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
106 .loc 1 232 0
107 0038 01F00302 and r2, r1, #3
108 .LVL3:
234:Core/Src/system_stm32g4xx.c **** {
109 .loc 1 234 0
110 003c 022A cmp r2, #2
233:Core/Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
111 .loc 1 233 0
112 003e C3F30313 ubfx r3, r3, #4, #4
236:Core/Src/system_stm32g4xx.c **** }
113 .loc 1 236 0
114 0042 0CBF ite eq
115 0044 0B4A ldreq r2, .L14+8
116 .LVL4:
240:Core/Src/system_stm32g4xx.c **** }
117 .loc 1 240 0
118 0046 0D4A ldrne r2, .L14+16
119 0048 0949 ldr r1, .L14+4
120 .LVL5:
233:Core/Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
121 .loc 1 233 0
122 004a 0133 adds r3, r3, #1
123 .LVL6:
240:Core/Src/system_stm32g4xx.c **** }
124 .loc 1 240 0
125 004c B2FBF3F3 udiv r3, r2, r3
126 .LVL7:
242:Core/Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
127 .loc 1 242 0
128 0050 064A ldr r2, .L14
129 0052 D068 ldr r0, [r2, #12]
130 .LVL8:
243:Core/Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
131 .loc 1 243 0
132 0054 D268 ldr r2, [r2, #12]
133 .LVL9:
134 0056 C2F34162 ubfx r2, r2, #25, #2
ARM GAS /tmp/ccjB19iz.s page 8
135 .LVL10:
136 005a 0132 adds r2, r2, #1
242:Core/Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
137 .loc 1 242 0
138 005c C0F30620 ubfx r0, r0, #8, #7
139 .LVL11:
243:Core/Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
140 .loc 1 243 0
141 0060 5200 lsls r2, r2, #1
242:Core/Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
142 .loc 1 242 0
143 0062 03FB00F3 mul r3, r3, r0
244:Core/Src/system_stm32g4xx.c **** break;
144 .loc 1 244 0
145 0066 B3FBF2F3 udiv r3, r3, r2
245:Core/Src/system_stm32g4xx.c ****
146 .loc 1 245 0
147 006a D7E7 b .L7
148 .L15:
149 .align 2
150 .L14:
151 006c 00100240 .word 1073876992
152 0070 00000000 .word .LANCHOR0
153 0074 0024F400 .word 16000000
154 0078 00000000 .word .LANCHOR1
155 007c 00366E01 .word 24000000
156 .cfi_endproc
157 .LFE330:
159 .global APBPrescTable
160 .global AHBPrescTable
161 .global SystemCoreClock
162 .section .data.SystemCoreClock,"aw",%progbits
163 .align 2
164 .set .LANCHOR0,. + 0
167 SystemCoreClock:
168 0000 0024F400 .word 16000000
169 .section .rodata.AHBPrescTable,"a",%progbits
170 .align 2
171 .set .LANCHOR1,. + 0
174 AHBPrescTable:
175 0000 00 .byte 0
176 0001 00 .byte 0
177 0002 00 .byte 0
178 0003 00 .byte 0
179 0004 00 .byte 0
180 0005 00 .byte 0
181 0006 00 .byte 0
182 0007 00 .byte 0
183 0008 01 .byte 1
184 0009 02 .byte 2
185 000a 03 .byte 3
186 000b 04 .byte 4
187 000c 06 .byte 6
188 000d 07 .byte 7
189 000e 08 .byte 8
190 000f 09 .byte 9
191 .section .rodata.APBPrescTable,"a",%progbits
ARM GAS /tmp/ccjB19iz.s page 9
192 .align 2
195 APBPrescTable:
196 0000 00 .byte 0
197 0001 00 .byte 0
198 0002 00 .byte 0
199 0003 00 .byte 0
200 0004 01 .byte 1
201 0005 02 .byte 2
202 0006 03 .byte 3
203 0007 04 .byte 4
204 .text
205 .Letext0:
206 .file 2 "/usr/include/newlib/machine/_default_types.h"
207 .file 3 "/usr/include/newlib/sys/_stdint.h"
208 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
209 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
210 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
211 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
212 .file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
213 .file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
214 .file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
ARM GAS /tmp/ccjB19iz.s page 10
DEFINED SYMBOLS
*ABS*:0000000000000000 system_stm32g4xx.c
/tmp/ccjB19iz.s:16 .text.SystemInit:0000000000000000 $t
/tmp/ccjB19iz.s:24 .text.SystemInit:0000000000000000 SystemInit
/tmp/ccjB19iz.s:47 .text.SystemInit:0000000000000018 $d
/tmp/ccjB19iz.s:52 .text.SystemCoreClockUpdate:0000000000000000 $t
/tmp/ccjB19iz.s:60 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
/tmp/ccjB19iz.s:151 .text.SystemCoreClockUpdate:000000000000006c $d
/tmp/ccjB19iz.s:195 .rodata.APBPrescTable:0000000000000000 APBPrescTable
/tmp/ccjB19iz.s:174 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
/tmp/ccjB19iz.s:167 .data.SystemCoreClock:0000000000000000 SystemCoreClock
/tmp/ccjB19iz.s:163 .data.SystemCoreClock:0000000000000000 $d
/tmp/ccjB19iz.s:170 .rodata.AHBPrescTable:0000000000000000 $d
/tmp/ccjB19iz.s:192 .rodata.APBPrescTable:0000000000000000 $d
NO UNDEFINED SYMBOLS