ARM GAS /tmp/ccZs0Fgx.s page 1 1 .cpu cortex-m4 2 .eabi_attribute 27, 1 3 .eabi_attribute 28, 1 4 .eabi_attribute 23, 1 5 .eabi_attribute 24, 1 6 .eabi_attribute 25, 1 7 .eabi_attribute 26, 1 8 .eabi_attribute 30, 2 9 .eabi_attribute 34, 1 10 .eabi_attribute 18, 4 11 .file "stm32g4xx_hal_pwr.c" 12 .text 13 .Ltext0: 14 .cfi_sections .debug_frame 15 .section .text.HAL_PWR_DeInit,"ax",%progbits 16 .align 1 17 .p2align 2,,3 18 .global HAL_PWR_DeInit 19 .syntax unified 20 .thumb 21 .thumb_func 22 .fpu fpv4-sp-d16 24 HAL_PWR_DeInit: 25 .LFB329: 26 .file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ****************************************************************************** 3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @file stm32g4xx_hal_pwr.c 4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @author MCD Application Team 5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief PWR HAL module driver. 6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: 8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * + Initialization/de-initialization functions 9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * + Peripheral Control functions 10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * 11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ****************************************************************************** 12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @attention 13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * 14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *

© Copyright (c) 2019 STMicroelectronics. 15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * All rights reserved.

16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * 17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, 18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the 19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * License. You may obtain a copy of the License at: 20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause 21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * 22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ****************************************************************************** 23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ 26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #include "stm32g4xx_hal.h" 27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @addtogroup STM32G4xx_HAL_Driver 29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{ 30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR PWR ARM GAS /tmp/ccZs0Fgx.s page 2 33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief PWR HAL module driver 34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{ 35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED 38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ 40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ 41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Private_Defines PWR Private Defines 43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{ 44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask 47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{ 48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD 50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD thresh 51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trig 52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD tri 53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @} 55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @} 59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ 62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ 63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ 64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Exported functions --------------------------------------------------------*/ 65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions 67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{ 68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Initialization and de-initialization functions 72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * 73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @verbatim 74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =============================================================================== 75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### 76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =============================================================================== 77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @endverbatim 80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{ 81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Deinitialize the HAL PWR peripheral registers to their default reset values. 85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DeInit(void) 88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 27 .loc 1 88 0 ARM GAS /tmp/ccZs0Fgx.s page 3 28 .cfi_startproc 29 @ args = 0, pretend = 0, frame = 0 30 @ frame_needed = 0, uses_anonymous_args = 0 31 @ link register save eliminated. 89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); 32 .loc 1 89 0 33 0000 044B ldr r3, .L3 34 0002 9A6B ldr r2, [r3, #56] 35 0004 42F08052 orr r2, r2, #268435456 36 0008 9A63 str r2, [r3, #56] 90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); 37 .loc 1 90 0 38 000a 9A6B ldr r2, [r3, #56] 39 000c 22F08052 bic r2, r2, #268435456 40 0010 9A63 str r2, [r3, #56] 91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 41 .loc 1 91 0 42 0012 7047 bx lr 43 .L4: 44 .align 2 45 .L3: 46 0014 00100240 .word 1073876992 47 .cfi_endproc 48 .LFE329: 50 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits 51 .align 1 52 .p2align 2,,3 53 .global HAL_PWR_EnableBkUpAccess 54 .syntax unified 55 .thumb 56 .thumb_func 57 .fpu fpv4-sp-d16 59 HAL_PWR_EnableBkUpAccess: 60 .LFB330: 92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable access to the backup domain 95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * (RTC registers, RTC backup data registers). 96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note After reset, the backup domain is protected against 97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * possible unwanted write accesses. 98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. 99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * In order to set or modify the RTC clock, the backup domain access must be 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * disabled. 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note LSEON bit that switches on and off the LSE crystal belongs as well to the 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * back-up domain. 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 61 .loc 1 106 0 62 .cfi_startproc 63 @ args = 0, pretend = 0, frame = 0 64 @ frame_needed = 0, uses_anonymous_args = 0 65 @ link register save eliminated. 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP); 66 .loc 1 107 0 67 0000 024A ldr r2, .L6 ARM GAS /tmp/ccZs0Fgx.s page 4 68 0002 1368 ldr r3, [r2] 69 0004 43F48073 orr r3, r3, #256 70 0008 1360 str r3, [r2] 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 71 .loc 1 108 0 72 000a 7047 bx lr 73 .L7: 74 .align 2 75 .L6: 76 000c 00700040 .word 1073770496 77 .cfi_endproc 78 .LFE330: 80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits 81 .align 1 82 .p2align 2,,3 83 .global HAL_PWR_DisableBkUpAccess 84 .syntax unified 85 .thumb 86 .thumb_func 87 .fpu fpv4-sp-d16 89 HAL_PWR_DisableBkUpAccess: 90 .LFB331: 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable access to the backup domain 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * (RTC registers, RTC backup data registers). 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 91 .loc 1 116 0 92 .cfi_startproc 93 @ args = 0, pretend = 0, frame = 0 94 @ frame_needed = 0, uses_anonymous_args = 0 95 @ link register save eliminated. 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); 96 .loc 1 117 0 97 0000 024A ldr r2, .L9 98 0002 1368 ldr r3, [r2] 99 0004 23F48073 bic r3, r3, #256 100 0008 1360 str r3, [r2] 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 101 .loc 1 118 0 102 000a 7047 bx lr 103 .L10: 104 .align 2 105 .L9: 106 000c 00700040 .word 1073770496 107 .cfi_endproc 108 .LFE331: 110 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits 111 .align 1 112 .p2align 2,,3 113 .global HAL_PWR_ConfigPVD 114 .syntax unified 115 .thumb 116 .thumb_func ARM GAS /tmp/ccZs0Fgx.s page 5 117 .fpu fpv4-sp-d16 119 HAL_PWR_ConfigPVD: 120 .LFB332: 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @} 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Low Power modes configuration functions 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @verbatim 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =============================================================================== 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ##### Peripheral Control functions ##### 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =============================================================================== 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** PVD configuration *** 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ========================= 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register). 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PVD_EXTI_ENABLE_IT() macro. 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** WakeUp pin configuration *** 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ================================ 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The polarity of these pins can be set to configure event detection on high 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** level (rising edge) or low level (falling edge). 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Low Power modes configuration *** 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ===================================== 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The devices feature 8 low-power modes: 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regul 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulato 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator of 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power reg 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserv 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. ARM GAS /tmp/ccZs0Fgx.s page 6 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Low-power run mode *** 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ========================== 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry: (from main run mode) 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the syst 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Exit: 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMod 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** then can the system clock frequency be increased above 2 MHz. 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Sleep mode / Low-power sleep mode *** 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ========================================= 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry: 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** in specifying whether or not the regulator is forced to low-power mode and if exit is int 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** In the latter case, the system clock frequency must have been decreased below 2 MHz befor 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFI Exit: 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** controller (NVIC) or any wake-up event. 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFE Exit: 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any wake-up event such as an EXTI line configured in event mode. 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** the MCU is in Low-power Run mode. 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Stop 0, Stop 1 modes *** 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =============================== 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry: 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Stop 0, Stop 1 modes are entered through the following API's: 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or fo 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_MAINREGULATOR_ON 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_LOWPOWERREGULATOR_ON 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Exit (interrupt or event-triggered, specified when entering STOP mode): 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFI Exit: 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt mode. 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** when programmed in wakeup mode. 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFE Exit: 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Event mode. 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run m ARM GAS /tmp/ccZs0Fgx.s page 7 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** depending on the LPR bit setting. 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Standby mode *** 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ==================== 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Standby mode offers two options: 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC b 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** and Standby circuitry. 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disa 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM and register contents are lost except for the RTC registers, RTC backup registers 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** and Standby circuitry. 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Entry: 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API. 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM1 and register contents are lost except for registers in the Backup domain and 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetentio 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** to set RRS bit. 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Exit: 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** external reset in NRST pin, IWDG reset. 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] After waking up from Standby mode, program execution restarts in the same way as afte 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Shutdown mode *** 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ====================== 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** In Shutdown mode, 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM and registers contents are lost except for backup domain registers. 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry: 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API. 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Exit: 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** external reset in NRST pin. 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] After waking up from Shutdown mode, program execution restarts in the same way as aft 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode *** 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ============================================= 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** Wakeup event, a tamper event or a time-stamp event, without depending on 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** an external interrupt (Auto-wakeup mode). 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ARM GAS /tmp/ccZs0Fgx.s page 8 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @endverbatim 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{ 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * configuration information. 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * more details about the voltage thresholds corresponding to each 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * detection level. 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 121 .loc 1 310 0 122 .cfi_startproc 123 @ args = 0, pretend = 0, frame = 0 124 @ frame_needed = 0, uses_anonymous_args = 0 125 @ link register save eliminated. 126 .LVL0: 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set PLS bits according to PVDLevel value */ 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); 127 .loc 1 316 0 128 0000 1C49 ldr r1, .L29 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 129 .loc 1 319 0 130 0002 1D4B ldr r3, .L29+4 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 131 .loc 1 316 0 132 0004 4A68 ldr r2, [r1, #4] 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */ 133 .loc 1 310 0 134 0006 10B4 push {r4} 135 .LCFI0: 136 .cfi_def_cfa_offset 4 137 .cfi_offset 4, -4 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 138 .loc 1 316 0 139 0008 0468 ldr r4, [r0] 140 000a 22F00E02 bic r2, r2, #14 141 000e 2243 orrs r2, r2, r4 ARM GAS /tmp/ccZs0Fgx.s page 9 142 0010 4A60 str r2, [r1, #4] 143 .loc 1 319 0 144 0012 5A68 ldr r2, [r3, #4] 145 0014 22F48032 bic r2, r2, #65536 146 0018 5A60 str r2, [r3, #4] 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); 147 .loc 1 320 0 148 001a 1A68 ldr r2, [r3] 149 001c 22F48032 bic r2, r2, #65536 150 0020 1A60 str r2, [r3] 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 151 .loc 1 321 0 152 0022 DA68 ldr r2, [r3, #12] 153 0024 22F48032 bic r2, r2, #65536 154 0028 DA60 str r2, [r3, #12] 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); 155 .loc 1 322 0 156 002a 9A68 ldr r2, [r3, #8] 157 002c 22F48032 bic r2, r2, #65536 158 0030 9A60 str r2, [r3, #8] 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Configure interrupt mode */ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 159 .loc 1 325 0 160 0032 4268 ldr r2, [r0, #4] 161 0034 D403 lsls r4, r2, #15 162 0036 03D5 bpl .L12 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); 163 .loc 1 327 0 164 0038 1968 ldr r1, [r3] 165 003a 41F48031 orr r1, r1, #65536 166 003e 1960 str r1, [r3] 167 .L12: 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Configure event mode */ 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 168 .loc 1 331 0 169 0040 9003 lsls r0, r2, #14 170 .LVL1: 171 0042 04D5 bpl .L13 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 172 .loc 1 333 0 173 0044 0C49 ldr r1, .L29+4 174 0046 4B68 ldr r3, [r1, #4] 175 0048 43F48033 orr r3, r3, #65536 176 004c 4B60 str r3, [r1, #4] 177 .L13: 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Configure the edge */ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 178 .loc 1 337 0 179 004e D107 lsls r1, r2, #31 180 0050 04D5 bpl .L14 ARM GAS /tmp/ccZs0Fgx.s page 10 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 181 .loc 1 339 0 182 0052 0949 ldr r1, .L29+4 183 0054 8B68 ldr r3, [r1, #8] 184 0056 43F48033 orr r3, r3, #65536 185 005a 8B60 str r3, [r1, #8] 186 .L14: 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 187 .loc 1 342 0 188 005c 9307 lsls r3, r2, #30 189 005e 04D5 bpl .L15 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 190 .loc 1 344 0 191 0060 054A ldr r2, .L29+4 192 0062 D368 ldr r3, [r2, #12] 193 0064 43F48033 orr r3, r3, #65536 194 0068 D360 str r3, [r2, #12] 195 .L15: 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** return HAL_OK; 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 196 .loc 1 348 0 197 006a 0020 movs r0, #0 198 006c 5DF8044B ldr r4, [sp], #4 199 .LCFI1: 200 .cfi_restore 4 201 .cfi_def_cfa_offset 0 202 0070 7047 bx lr 203 .L30: 204 0072 00BF .align 2 205 .L29: 206 0074 00700040 .word 1073770496 207 0078 00040140 .word 1073808384 208 .cfi_endproc 209 .LFE332: 211 .section .text.HAL_PWR_EnablePVD,"ax",%progbits 212 .align 1 213 .p2align 2,,3 214 .global HAL_PWR_EnablePVD 215 .syntax unified 216 .thumb 217 .thumb_func 218 .fpu fpv4-sp-d16 220 HAL_PWR_EnablePVD: 221 .LFB333: 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable the Power Voltage Detector (PVD). 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) ARM GAS /tmp/ccZs0Fgx.s page 11 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 222 .loc 1 356 0 223 .cfi_startproc 224 @ args = 0, pretend = 0, frame = 0 225 @ frame_needed = 0, uses_anonymous_args = 0 226 @ link register save eliminated. 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(PWR->CR2, PWR_CR2_PVDE); 227 .loc 1 357 0 228 0000 024A ldr r2, .L32 229 0002 5368 ldr r3, [r2, #4] 230 0004 43F00103 orr r3, r3, #1 231 0008 5360 str r3, [r2, #4] 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 232 .loc 1 358 0 233 000a 7047 bx lr 234 .L33: 235 .align 2 236 .L32: 237 000c 00700040 .word 1073770496 238 .cfi_endproc 239 .LFE333: 241 .section .text.HAL_PWR_DisablePVD,"ax",%progbits 242 .align 1 243 .p2align 2,,3 244 .global HAL_PWR_DisablePVD 245 .syntax unified 246 .thumb 247 .thumb_func 248 .fpu fpv4-sp-d16 250 HAL_PWR_DisablePVD: 251 .LFB334: 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable the Power Voltage Detector (PVD). 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 252 .loc 1 365 0 253 .cfi_startproc 254 @ args = 0, pretend = 0, frame = 0 255 @ frame_needed = 0, uses_anonymous_args = 0 256 @ link register save eliminated. 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); 257 .loc 1 366 0 258 0000 024A ldr r2, .L35 259 0002 5368 ldr r3, [r2, #4] 260 0004 23F00103 bic r3, r3, #1 261 0008 5360 str r3, [r2, #4] 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 262 .loc 1 367 0 263 000a 7047 bx lr 264 .L36: 265 .align 2 266 .L35: 267 000c 00700040 .word 1073770496 268 .cfi_endproc ARM GAS /tmp/ccZs0Fgx.s page 12 269 .LFE334: 271 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits 272 .align 1 273 .p2align 2,,3 274 .global HAL_PWR_EnableWakeUpPin 275 .syntax unified 276 .thumb 277 .thumb_func 278 .fpu fpv4-sp-d16 280 HAL_PWR_EnableWakeUpPin: 281 .LFB335: 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable the WakeUp PINx functionality. 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following legacy values which set the default polarity 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * i.e. detection on high level (rising edge): 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAK 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * or one of the following value where the user can explicitly specify the enabled pin and 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the chosen polarity: 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 282 .loc 1 390 0 283 .cfi_startproc 284 @ args = 0, pretend = 0, frame = 0 285 @ frame_needed = 0, uses_anonymous_args = 0 286 @ link register save eliminated. 287 .LVL2: 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Specifies the Wake-Up pin polarity for the event detection 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (rising or falling edge) */ 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_S 288 .loc 1 395 0 289 0000 064A ldr r2, .L38 290 0002 D368 ldr r3, [r2, #12] 291 0004 00F01F01 and r1, r0, #31 292 0008 23EA0103 bic r3, r3, r1 293 000c 43EA5010 orr r0, r3, r0, lsr #5 294 .LVL3: 295 0010 D060 str r0, [r2, #12] 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Enable wake-up pin */ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); 296 .loc 1 398 0 ARM GAS /tmp/ccZs0Fgx.s page 13 297 0012 9368 ldr r3, [r2, #8] 298 0014 1943 orrs r1, r1, r3 299 0016 9160 str r1, [r2, #8] 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 300 .loc 1 401 0 301 0018 7047 bx lr 302 .L39: 303 001a 00BF .align 2 304 .L38: 305 001c 00700040 .word 1073770496 306 .cfi_endproc 307 .LFE335: 309 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits 310 .align 1 311 .p2align 2,,3 312 .global HAL_PWR_DisableWakeUpPin 313 .syntax unified 314 .thumb 315 .thumb_func 316 .fpu fpv4-sp-d16 318 HAL_PWR_DisableWakeUpPin: 319 .LFB336: 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable the WakeUp PINx functionality. 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values: 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAK 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 320 .loc 1 411 0 321 .cfi_startproc 322 @ args = 0, pretend = 0, frame = 0 323 @ frame_needed = 0, uses_anonymous_args = 0 324 @ link register save eliminated. 325 .LVL4: 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); 326 .loc 1 414 0 327 0000 034A ldr r2, .L41 328 0002 9368 ldr r3, [r2, #8] 329 0004 00F01F00 and r0, r0, #31 330 .LVL5: 331 0008 23EA0003 bic r3, r3, r0 332 000c 9360 str r3, [r2, #8] 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 333 .loc 1 415 0 334 000e 7047 bx lr 335 .L42: 336 .align 2 337 .L41: 338 0010 00700040 .word 1073770496 ARM GAS /tmp/ccZs0Fgx.s page 14 339 .cfi_endproc 340 .LFE336: 342 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits 343 .align 1 344 .p2align 2,,3 345 .global HAL_PWR_EnterSLEEPMode 346 .syntax unified 347 .thumb 348 .thumb_func 349 .fpu fpv4-sp-d16 351 HAL_PWR_EnterSLEEPMode: 352 .LFB337: 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enter Sleep or Low-power Sleep mode. 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode. 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode. 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values: 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Additionally, the clock frequency must be reduced below 2 MHz. 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * be done before calling HAL_PWR_EnterSLEEPMode() API. 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction. 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values: 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instructio 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instructio 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When WFI entry is used, tick interrupt have to be disabled if not desired as 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the interrupt wake up source. 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 353 .loc 1 443 0 354 .cfi_startproc 355 @ args = 0, pretend = 0, frame = 0 356 @ frame_needed = 0, uses_anonymous_args = 0 357 .LVL6: 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set Regulator parameter */ 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if (Regulator == PWR_MAINREGULATOR_ON) 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* If in low-power run mode at this point, exit it */ 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) 358 .loc 1 452 0 359 0000 0D4B ldr r3, .L54 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */ ARM GAS /tmp/ccZs0Fgx.s page 15 360 .loc 1 443 0 361 0002 10B5 push {r4, lr} 362 .LCFI2: 363 .cfi_def_cfa_offset 8 364 .cfi_offset 4, -8 365 .cfi_offset 14, -4 366 .loc 1 452 0 367 0004 5B69 ldr r3, [r3, #20] 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */ 368 .loc 1 443 0 369 0006 0C46 mov r4, r1 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 370 .loc 1 449 0 371 0008 60B9 cbnz r0, .L44 372 .loc 1 452 0 373 000a 9A05 lsls r2, r3, #22 374 000c 11D4 bmi .L52 375 .LVL7: 376 .L45: 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (void)HAL_PWREx_DisableLowPowerRunMode(); 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Regulator now in main mode. */ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** else 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* If in run mode, first move to low-power run mode. 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The system clock frequency must be below 2 MHz at this point. */ 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U) 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_PWREx_EnableLowPowerRunMode(); 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 377 .loc 1 469 0 378 000e 0B4A ldr r2, .L54+4 379 0010 1369 ldr r3, [r2, #16] 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) 380 .loc 1 472 0 381 0012 012C cmp r4, #1 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 382 .loc 1 469 0 383 0014 23F00403 bic r3, r3, #4 384 0018 1361 str r3, [r2, #16] 385 .loc 1 472 0 386 001a 08D0 beq .L53 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFI(); 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** else 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Request Wait For Event */ ARM GAS /tmp/ccZs0Fgx.s page 16 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __SEV(); 387 .loc 1 480 0 388 .syntax unified 389 @ 480 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1 390 001c 40BF sev 391 @ 0 "" 2 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFE(); 392 .loc 1 481 0 393 @ 481 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1 394 001e 20BF wfe 395 @ 0 "" 2 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFE(); 396 .loc 1 482 0 397 @ 482 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1 398 0020 20BF wfe 399 @ 0 "" 2 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 400 .loc 1 485 0 401 .thumb 402 .syntax unified 403 0022 10BD pop {r4, pc} 404 .LVL8: 405 .L44: 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 406 .loc 1 462 0 407 0024 9B05 lsls r3, r3, #22 408 0026 F2D4 bmi .L45 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 409 .loc 1 464 0 410 0028 FFF7FEFF bl HAL_PWREx_EnableLowPowerRunMode 411 .LVL9: 412 002c EFE7 b .L45 413 .L53: 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 414 .loc 1 475 0 415 .syntax unified 416 @ 475 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1 417 002e 30BF wfi 418 @ 0 "" 2 419 .loc 1 485 0 420 .thumb 421 .syntax unified 422 0030 10BD pop {r4, pc} 423 .LVL10: 424 .L52: 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 425 .loc 1 454 0 426 0032 FFF7FEFF bl HAL_PWREx_DisableLowPowerRunMode 427 .LVL11: 428 0036 EAE7 b .L45 429 .L55: 430 .align 2 431 .L54: 432 0038 00700040 .word 1073770496 433 003c 00ED00E0 .word -536810240 ARM GAS /tmp/ccZs0Fgx.s page 17 434 .cfi_endproc 435 .LFE337: 437 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits 438 .align 1 439 .p2align 2,,3 440 .global HAL_PWR_EnterSTOPMode 441 .syntax unified 442 .thumb 443 .thumb_func 444 .fpu fpv4-sp-d16 446 HAL_PWR_EnterSTOPMode: 447 .LFB338: 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enter Stop mode 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * on devices where only "Stop mode" is mentioned with main or low power regulator ON. 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note All clocks in the VCORE domain are stopped; the PLL, 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capabilit 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the H 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is pr 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * only to the peripheral requesting it. 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * SRAM1, SRAM2 and register contents are preserved. 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * The BOR is available. 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Sto 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode (Stop 1), an additional 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * startup delay is incurred when waking up. 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * is higher although the startup time is reduced. 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Stop mode. 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values: 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values: 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction. 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 448 .loc 1 518 0 449 .cfi_startproc 450 @ args = 0, pretend = 0, frame = 0 451 @ frame_needed = 0, uses_anonymous_args = 0 452 @ link register save eliminated. 453 .LVL12: 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if(Regulator == PWR_LOWPOWERREGULATOR_ON) 454 .loc 1 522 0 455 0000 B0F5804F cmp r0, #16384 ARM GAS /tmp/ccZs0Fgx.s page 18 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_PWREx_EnterSTOP1Mode(STOPEntry); 456 .loc 1 524 0 457 0004 0846 mov r0, r1 458 .LVL13: 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 459 .loc 1 522 0 460 0006 01D0 beq .L58 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** else 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_PWREx_EnterSTOP0Mode(STOPEntry); 461 .loc 1 528 0 462 0008 FFF7FEBF b HAL_PWREx_EnterSTOP0Mode 463 .LVL14: 464 .L58: 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 465 .loc 1 524 0 466 000c FFF7FEBF b HAL_PWREx_EnterSTOP1Mode 467 .LVL15: 468 .cfi_endproc 469 .LFE338: 471 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits 472 .align 1 473 .p2align 2,,3 474 .global HAL_PWR_EnterSTANDBYMode 475 .syntax unified 476 .thumb 477 .thumb_func 478 .fpu fpv4-sp-d16 480 HAL_PWR_EnterSTANDBYMode: 481 .LFB339: 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enter Standby mode. 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * off. The voltage regulator is disabled, except when SRAM2 content is preserved 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * in which case the regulator is in low-power mode. 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * SRAM1 and register contents are lost except for registers in the Backup domain and 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 regis 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() A 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * to set RRS bit. 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * The BOR is available. 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog s 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disab 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * same. 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * These states are effective in Standby mode only if APC bit is set through 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * HAL_PWREx_EnablePullUpPullDownConfig() API. 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 482 .loc 1 551 0 483 .cfi_startproc ARM GAS /tmp/ccZs0Fgx.s page 19 484 @ args = 0, pretend = 0, frame = 0 485 @ frame_needed = 0, uses_anonymous_args = 0 486 @ link register save eliminated. 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set Stand-by mode */ 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY); 487 .loc 1 553 0 488 0000 0649 ldr r1, .L60 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 489 .loc 1 556 0 490 0002 074A ldr r2, .L60+4 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 491 .loc 1 553 0 492 0004 0B68 ldr r3, [r1] 493 0006 23F00703 bic r3, r3, #7 494 000a 43F00303 orr r3, r3, #3 495 000e 0B60 str r3, [r1] 496 .loc 1 556 0 497 0010 1369 ldr r3, [r2, #16] 498 0012 43F00403 orr r3, r3, #4 499 0016 1361 str r3, [r2, #16] 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #if defined ( __CC_ARM) 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __force_stores(); 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #endif 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFI(); 500 .loc 1 563 0 501 .syntax unified 502 @ 563 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1 503 0018 30BF wfi 504 @ 0 "" 2 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 505 .loc 1 564 0 506 .thumb 507 .syntax unified 508 001a 7047 bx lr 509 .L61: 510 .align 2 511 .L60: 512 001c 00700040 .word 1073770496 513 0020 00ED00E0 .word -536810240 514 .cfi_endproc 515 .LFE339: 517 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits 518 .align 1 519 .p2align 2,,3 520 .global HAL_PWR_EnableSleepOnExit 521 .syntax unified 522 .thumb 523 .thumb_func 524 .fpu fpv4-sp-d16 526 HAL_PWR_EnableSleepOnExit: 527 .LFB340: 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ARM GAS /tmp/ccZs0Fgx.s page 20 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * interruptions handling. 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 528 .loc 1 577 0 529 .cfi_startproc 530 @ args = 0, pretend = 0, frame = 0 531 @ frame_needed = 0, uses_anonymous_args = 0 532 @ link register save eliminated. 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 533 .loc 1 579 0 534 0000 024A ldr r2, .L63 535 0002 1369 ldr r3, [r2, #16] 536 0004 43F00203 orr r3, r3, #2 537 0008 1361 str r3, [r2, #16] 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 538 .loc 1 580 0 539 000a 7047 bx lr 540 .L64: 541 .align 2 542 .L63: 543 000c 00ED00E0 .word -536810240 544 .cfi_endproc 545 .LFE340: 547 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits 548 .align 1 549 .p2align 2,,3 550 .global HAL_PWR_DisableSleepOnExit 551 .syntax unified 552 .thumb 553 .thumb_func 554 .fpu fpv4-sp-d16 556 HAL_PWR_DisableSleepOnExit: 557 .LFB341: 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 558 .loc 1 590 0 559 .cfi_startproc 560 @ args = 0, pretend = 0, frame = 0 561 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccZs0Fgx.s page 21 562 @ link register save eliminated. 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 563 .loc 1 592 0 564 0000 024A ldr r2, .L66 565 0002 1369 ldr r3, [r2, #16] 566 0004 23F00203 bic r3, r3, #2 567 0008 1361 str r3, [r2, #16] 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 568 .loc 1 593 0 569 000a 7047 bx lr 570 .L67: 571 .align 2 572 .L66: 573 000c 00ED00E0 .word -536810240 574 .cfi_endproc 575 .LFE341: 577 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits 578 .align 1 579 .p2align 2,,3 580 .global HAL_PWR_EnableSEVOnPend 581 .syntax unified 582 .thumb 583 .thumb_func 584 .fpu fpv4-sp-d16 586 HAL_PWR_EnableSEVOnPend: 587 .LFB342: 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable CORTEX M4 SEVONPEND bit. 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 588 .loc 1 604 0 589 .cfi_startproc 590 @ args = 0, pretend = 0, frame = 0 591 @ frame_needed = 0, uses_anonymous_args = 0 592 @ link register save eliminated. 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 593 .loc 1 606 0 594 0000 024A ldr r2, .L69 595 0002 1369 ldr r3, [r2, #16] 596 0004 43F01003 orr r3, r3, #16 597 0008 1361 str r3, [r2, #16] 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 598 .loc 1 607 0 599 000a 7047 bx lr 600 .L70: 601 .align 2 602 .L69: 603 000c 00ED00E0 .word -536810240 ARM GAS /tmp/ccZs0Fgx.s page 22 604 .cfi_endproc 605 .LFE342: 607 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits 608 .align 1 609 .p2align 2,,3 610 .global HAL_PWR_DisableSEVOnPend 611 .syntax unified 612 .thumb 613 .thumb_func 614 .fpu fpv4-sp-d16 616 HAL_PWR_DisableSEVOnPend: 617 .LFB343: 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable CORTEX M4 SEVONPEND bit. 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 618 .loc 1 617 0 619 .cfi_startproc 620 @ args = 0, pretend = 0, frame = 0 621 @ frame_needed = 0, uses_anonymous_args = 0 622 @ link register save eliminated. 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 623 .loc 1 619 0 624 0000 024A ldr r2, .L72 625 0002 1369 ldr r3, [r2, #16] 626 0004 23F01003 bic r3, r3, #16 627 0008 1361 str r3, [r2, #16] 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 628 .loc 1 620 0 629 000a 7047 bx lr 630 .L73: 631 .align 2 632 .L72: 633 000c 00ED00E0 .word -536810240 634 .cfi_endproc 635 .LFE343: 637 .section .text.HAL_PWR_PVDCallback,"ax",%progbits 638 .align 1 639 .p2align 2,,3 640 .weak HAL_PWR_PVDCallback 641 .syntax unified 642 .thumb 643 .thumb_func 644 .fpu fpv4-sp-d16 646 HAL_PWR_PVDCallback: 647 .LFB344: 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ARM GAS /tmp/ccZs0Fgx.s page 23 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief PWR PVD interrupt callback 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** { 648 .loc 1 631 0 649 .cfi_startproc 650 @ args = 0, pretend = 0, frame = 0 651 @ frame_needed = 0, uses_anonymous_args = 0 652 @ link register save eliminated. 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* NOTE : This function should not be modified; when the callback is needed, 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** the HAL_PWR_PVDCallback can be implemented in the user file 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */ 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** } 653 .loc 1 635 0 654 0000 7047 bx lr 655 .cfi_endproc 656 .LFE344: 658 0002 00BF .text 659 .Letext0: 660 .file 2 "/usr/include/newlib/machine/_default_types.h" 661 .file 3 "/usr/include/newlib/sys/_stdint.h" 662 .file 4 "Drivers/CMSIS/Include/core_cm4.h" 663 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h" 664 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h" 665 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h" 666 .file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h" 667 .file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h" 668 .file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h" 669 .file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h" 670 .file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h" ARM GAS /tmp/ccZs0Fgx.s page 24 DEFINED SYMBOLS *ABS*:0000000000000000 stm32g4xx_hal_pwr.c /tmp/ccZs0Fgx.s:16 .text.HAL_PWR_DeInit:0000000000000000 $t /tmp/ccZs0Fgx.s:24 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit /tmp/ccZs0Fgx.s:46 .text.HAL_PWR_DeInit:0000000000000014 $d /tmp/ccZs0Fgx.s:51 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t /tmp/ccZs0Fgx.s:59 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess /tmp/ccZs0Fgx.s:76 .text.HAL_PWR_EnableBkUpAccess:000000000000000c $d /tmp/ccZs0Fgx.s:81 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t /tmp/ccZs0Fgx.s:89 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess /tmp/ccZs0Fgx.s:106 .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d /tmp/ccZs0Fgx.s:111 .text.HAL_PWR_ConfigPVD:0000000000000000 $t /tmp/ccZs0Fgx.s:119 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD /tmp/ccZs0Fgx.s:206 .text.HAL_PWR_ConfigPVD:0000000000000074 $d /tmp/ccZs0Fgx.s:212 .text.HAL_PWR_EnablePVD:0000000000000000 $t /tmp/ccZs0Fgx.s:220 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD /tmp/ccZs0Fgx.s:237 .text.HAL_PWR_EnablePVD:000000000000000c $d /tmp/ccZs0Fgx.s:242 .text.HAL_PWR_DisablePVD:0000000000000000 $t /tmp/ccZs0Fgx.s:250 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD /tmp/ccZs0Fgx.s:267 .text.HAL_PWR_DisablePVD:000000000000000c $d /tmp/ccZs0Fgx.s:272 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t /tmp/ccZs0Fgx.s:280 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin /tmp/ccZs0Fgx.s:305 .text.HAL_PWR_EnableWakeUpPin:000000000000001c $d /tmp/ccZs0Fgx.s:310 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t /tmp/ccZs0Fgx.s:318 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin /tmp/ccZs0Fgx.s:338 .text.HAL_PWR_DisableWakeUpPin:0000000000000010 $d /tmp/ccZs0Fgx.s:343 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t /tmp/ccZs0Fgx.s:351 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode /tmp/ccZs0Fgx.s:432 .text.HAL_PWR_EnterSLEEPMode:0000000000000038 $d /tmp/ccZs0Fgx.s:438 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t /tmp/ccZs0Fgx.s:446 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode /tmp/ccZs0Fgx.s:472 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t /tmp/ccZs0Fgx.s:480 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode /tmp/ccZs0Fgx.s:512 .text.HAL_PWR_EnterSTANDBYMode:000000000000001c $d /tmp/ccZs0Fgx.s:518 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t /tmp/ccZs0Fgx.s:526 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit /tmp/ccZs0Fgx.s:543 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d /tmp/ccZs0Fgx.s:548 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t /tmp/ccZs0Fgx.s:556 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit /tmp/ccZs0Fgx.s:573 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d /tmp/ccZs0Fgx.s:578 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t /tmp/ccZs0Fgx.s:586 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend /tmp/ccZs0Fgx.s:603 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d /tmp/ccZs0Fgx.s:608 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t /tmp/ccZs0Fgx.s:616 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend /tmp/ccZs0Fgx.s:633 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d /tmp/ccZs0Fgx.s:638 .text.HAL_PWR_PVDCallback:0000000000000000 $t /tmp/ccZs0Fgx.s:646 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback UNDEFINED SYMBOLS HAL_PWREx_EnableLowPowerRunMode HAL_PWREx_DisableLowPowerRunMode HAL_PWREx_EnterSTOP0Mode HAL_PWREx_EnterSTOP1Mode