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5610d2606cc96d03b74102d7740e7526fec2830c
bassofono/codice/build/main.lst
nzasch 5610d2606c opamp
2021-07-03 04:08:08 +02:00

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ARM GAS /tmp/ccX7ayIU.s page 1
1 .cpu cortex-m4
2 .eabi_attribute 27, 1
3 .eabi_attribute 28, 1
4 .eabi_attribute 23, 1
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 2
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "main.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits
16 .align 1
17 .p2align 2,,3
18 .global HAL_ADC_ConvCpltCallback
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu fpv4-sp-d16
24 HAL_ADC_ConvCpltCallback:
25 .LFB376:
26 .file 1 "Core/Src/main.c"
1:Core/Src/main.c **** /* USER CODE BEGIN Header */
2:Core/Src/main.c **** /**
3:Core/Src/main.c **** ******************************************************************************
4:Core/Src/main.c **** * @file : main.c
5:Core/Src/main.c **** * @brief : Main program body
6:Core/Src/main.c **** ******************************************************************************
7:Core/Src/main.c **** * @attention
8:Core/Src/main.c **** *
9:Core/Src/main.c **** * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
10:Core/Src/main.c **** * All rights reserved.</center></h2>
11:Core/Src/main.c **** *
12:Core/Src/main.c **** * This software component is licensed by ST under BSD 3-Clause license,
13:Core/Src/main.c **** * the "License"; You may not use this file except in compliance with the
14:Core/Src/main.c **** * License. You may obtain a copy of the License at:
15:Core/Src/main.c **** * opensource.org/licenses/BSD-3-Clause
16:Core/Src/main.c **** *
17:Core/Src/main.c **** ******************************************************************************
18:Core/Src/main.c **** */
19:Core/Src/main.c **** /* USER CODE END Header */
20:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
21:Core/Src/main.c **** #include "main.h"
22:Core/Src/main.c ****
23:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
24:Core/Src/main.c **** /* USER CODE BEGIN Includes */
25:Core/Src/main.c **** #include <stdio.h>
26:Core/Src/main.c **** #include "bassofono.h"
27:Core/Src/main.c **** #include "interface.h"
28:Core/Src/main.c ****
29:Core/Src/main.c **** /* USER CODE END Includes */
30:Core/Src/main.c ****
31:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
32:Core/Src/main.c **** /* USER CODE BEGIN PTD */
ARM GAS /tmp/ccX7ayIU.s page 2
33:Core/Src/main.c ****
34:Core/Src/main.c **** /* USER CODE END PTD */
35:Core/Src/main.c ****
36:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
37:Core/Src/main.c **** /* USER CODE BEGIN PD */
38:Core/Src/main.c **** /* USER CODE END PD */
39:Core/Src/main.c ****
40:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
41:Core/Src/main.c **** /* USER CODE BEGIN PM */
42:Core/Src/main.c ****
43:Core/Src/main.c **** /* USER CODE END PM */
44:Core/Src/main.c ****
45:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
46:Core/Src/main.c **** ADC_HandleTypeDef hadc1;
47:Core/Src/main.c **** DMA_HandleTypeDef hdma_adc1;
48:Core/Src/main.c ****
49:Core/Src/main.c **** CORDIC_HandleTypeDef hcordic;
50:Core/Src/main.c ****
51:Core/Src/main.c **** DAC_HandleTypeDef hdac1;
52:Core/Src/main.c **** DMA_HandleTypeDef hdma_dac1_ch1;
53:Core/Src/main.c **** DMA_HandleTypeDef hdma_dac1_ch2;
54:Core/Src/main.c ****
55:Core/Src/main.c **** OPAMP_HandleTypeDef hopamp1;
56:Core/Src/main.c ****
57:Core/Src/main.c **** TIM_HandleTypeDef htim6;
58:Core/Src/main.c **** TIM_HandleTypeDef htim7;
59:Core/Src/main.c **** TIM_HandleTypeDef htim8;
60:Core/Src/main.c ****
61:Core/Src/main.c **** UART_HandleTypeDef huart1;
62:Core/Src/main.c **** DMA_HandleTypeDef hdma_usart1_tx;
63:Core/Src/main.c ****
64:Core/Src/main.c **** /* USER CODE BEGIN PV */
65:Core/Src/main.c ****
66:Core/Src/main.c **** volatile uint8_t tick;
67:Core/Src/main.c ****
68:Core/Src/main.c **** // RX
69:Core/Src/main.c **** volatile uint8_t rx_adc_buffer_ready, half_rx_dac_buffer_empty;
70:Core/Src/main.c ****
71:Core/Src/main.c **** // TX
72:Core/Src/main.c **** // volatile uint8_t half_tx_dac_buffer_empty, tx_dac_buffer_toggle;
73:Core/Src/main.c ****
74:Core/Src/main.c **** /* USER CODE END PV */
75:Core/Src/main.c ****
76:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
77:Core/Src/main.c **** void SystemClock_Config(void);
78:Core/Src/main.c **** static void MX_GPIO_Init(void);
79:Core/Src/main.c **** static void MX_DMA_Init(void);
80:Core/Src/main.c **** static void MX_DAC1_Init(void);
81:Core/Src/main.c **** static void MX_ADC1_Init(void);
82:Core/Src/main.c **** static void MX_TIM7_Init(void);
83:Core/Src/main.c **** static void MX_TIM6_Init(void);
84:Core/Src/main.c **** static void MX_CORDIC_Init(void);
85:Core/Src/main.c **** static void MX_USART1_UART_Init(void);
86:Core/Src/main.c **** static void MX_TIM8_Init(void);
87:Core/Src/main.c **** static void MX_OPAMP1_Init(void);
88:Core/Src/main.c **** /* USER CODE BEGIN PFP */
89:Core/Src/main.c ****
ARM GAS /tmp/ccX7ayIU.s page 3
90:Core/Src/main.c **** /* USER CODE END PFP */
91:Core/Src/main.c ****
92:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
93:Core/Src/main.c **** /* USER CODE BEGIN 0 */
94:Core/Src/main.c ****
95:Core/Src/main.c **** // IRQ
96:Core/Src/main.c ****
97:Core/Src/main.c **** // ADC
98:Core/Src/main.c ****
99:Core/Src/main.c **** void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){
27 .loc 1 99 0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 0
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
32 .LVL0:
100:Core/Src/main.c **** if(hadc->Instance == ADC1){
33 .loc 1 100 0
34 0000 0368 ldr r3, [r0]
35 0002 B3F1A04F cmp r3, #1342177280
36 0006 02D1 bne .L1
101:Core/Src/main.c **** rx_adc_buffer_ready = 1;
37 .loc 1 101 0
38 0008 014B ldr r3, .L4
39 000a 0122 movs r2, #1
40 000c 1A70 strb r2, [r3]
41 .L1:
102:Core/Src/main.c **** }
103:Core/Src/main.c **** }
42 .loc 1 103 0
43 000e 7047 bx lr
44 .L5:
45 .align 2
46 .L4:
47 0010 00000000 .word rx_adc_buffer_ready
48 .cfi_endproc
49 .LFE376:
51 .section .text.HAL_DAC_ConvHalfCpltCallbackCh1,"ax",%progbits
52 .align 1
53 .p2align 2,,3
54 .global HAL_DAC_ConvHalfCpltCallbackCh1
55 .syntax unified
56 .thumb
57 .thumb_func
58 .fpu fpv4-sp-d16
60 HAL_DAC_ConvHalfCpltCallbackCh1:
61 .LFB377:
104:Core/Src/main.c ****
105:Core/Src/main.c **** // DAC
106:Core/Src/main.c **** // rx
107:Core/Src/main.c **** void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) {
62 .loc 1 107 0
63 .cfi_startproc
64 @ args = 0, pretend = 0, frame = 0
65 @ frame_needed = 0, uses_anonymous_args = 0
66 @ link register save eliminated.
67 .LVL1:
ARM GAS /tmp/ccX7ayIU.s page 4
108:Core/Src/main.c **** lf_buffer_toggle = 0;
68 .loc 1 108 0
69 0000 0349 ldr r1, .L7
109:Core/Src/main.c **** half_rx_dac_buffer_empty = 1;
70 .loc 1 109 0
71 0002 044B ldr r3, .L7+4
108:Core/Src/main.c **** lf_buffer_toggle = 0;
72 .loc 1 108 0
73 0004 0020 movs r0, #0
74 .LVL2:
75 .loc 1 109 0
76 0006 0122 movs r2, #1
108:Core/Src/main.c **** lf_buffer_toggle = 0;
77 .loc 1 108 0
78 0008 0870 strb r0, [r1]
79 .loc 1 109 0
80 000a 1A70 strb r2, [r3]
110:Core/Src/main.c **** }
81 .loc 1 110 0
82 000c 7047 bx lr
83 .L8:
84 000e 00BF .align 2
85 .L7:
86 0010 00000000 .word lf_buffer_toggle
87 0014 00000000 .word half_rx_dac_buffer_empty
88 .cfi_endproc
89 .LFE377:
91 .section .text.HAL_DAC_ConvCpltCallbackCh1,"ax",%progbits
92 .align 1
93 .p2align 2,,3
94 .global HAL_DAC_ConvCpltCallbackCh1
95 .syntax unified
96 .thumb
97 .thumb_func
98 .fpu fpv4-sp-d16
100 HAL_DAC_ConvCpltCallbackCh1:
101 .LFB378:
111:Core/Src/main.c ****
112:Core/Src/main.c **** void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) {
102 .loc 1 112 0
103 .cfi_startproc
104 @ args = 0, pretend = 0, frame = 0
105 @ frame_needed = 0, uses_anonymous_args = 0
106 @ link register save eliminated.
107 .LVL3:
113:Core/Src/main.c **** lf_buffer_toggle = 1;
108 .loc 1 113 0
109 0000 0249 ldr r1, .L10
114:Core/Src/main.c **** half_rx_dac_buffer_empty = 1;
110 .loc 1 114 0
111 0002 034A ldr r2, .L10+4
113:Core/Src/main.c **** lf_buffer_toggle = 1;
112 .loc 1 113 0
113 0004 0123 movs r3, #1
114 0006 0B70 strb r3, [r1]
115 .loc 1 114 0
116 0008 1370 strb r3, [r2]
ARM GAS /tmp/ccX7ayIU.s page 5
115:Core/Src/main.c **** }
117 .loc 1 115 0
118 000a 7047 bx lr
119 .L11:
120 .align 2
121 .L10:
122 000c 00000000 .word lf_buffer_toggle
123 0010 00000000 .word half_rx_dac_buffer_empty
124 .cfi_endproc
125 .LFE378:
127 .section .text.HAL_DACEx_ConvHalfCpltCallbackCh2,"ax",%progbits
128 .align 1
129 .p2align 2,,3
130 .global HAL_DACEx_ConvHalfCpltCallbackCh2
131 .syntax unified
132 .thumb
133 .thumb_func
134 .fpu fpv4-sp-d16
136 HAL_DACEx_ConvHalfCpltCallbackCh2:
137 .LFB379:
116:Core/Src/main.c ****
117:Core/Src/main.c **** // tx
118:Core/Src/main.c **** void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) {
138 .loc 1 118 0
139 .cfi_startproc
140 @ args = 0, pretend = 0, frame = 0
141 @ frame_needed = 0, uses_anonymous_args = 0
142 .LVL4:
143 0000 08B5 push {r3, lr}
144 .LCFI0:
145 .cfi_def_cfa_offset 8
146 .cfi_offset 3, -8
147 .cfi_offset 14, -4
119:Core/Src/main.c **** HAL_GPIO_TogglePin(OUT_GPIO_Port, OUT_Pin);
148 .loc 1 119 0
149 0002 2021 movs r1, #32
150 0004 0448 ldr r0, .L14
151 .LVL5:
152 0006 FFF7FEFF bl HAL_GPIO_TogglePin
153 .LVL6:
120:Core/Src/main.c **** tx_dac_buffer_toggle = 0;
154 .loc 1 120 0
155 000a 0449 ldr r1, .L14+4
121:Core/Src/main.c **** half_tx_dac_buffer_empty = 1;
156 .loc 1 121 0
157 000c 044B ldr r3, .L14+8
120:Core/Src/main.c **** tx_dac_buffer_toggle = 0;
158 .loc 1 120 0
159 000e 0020 movs r0, #0
160 .loc 1 121 0
161 0010 0122 movs r2, #1
120:Core/Src/main.c **** tx_dac_buffer_toggle = 0;
162 .loc 1 120 0
163 0012 0870 strb r0, [r1]
164 .loc 1 121 0
165 0014 1A70 strb r2, [r3]
122:Core/Src/main.c **** }
ARM GAS /tmp/ccX7ayIU.s page 6
166 .loc 1 122 0
167 0016 08BD pop {r3, pc}
168 .L15:
169 .align 2
170 .L14:
171 0018 00040048 .word 1207960576
172 001c 00000000 .word tx_dac_buffer_toggle
173 0020 00000000 .word half_tx_dac_buffer_empty
174 .cfi_endproc
175 .LFE379:
177 .section .text.HAL_DACEx_ConvCpltCallbackCh2,"ax",%progbits
178 .align 1
179 .p2align 2,,3
180 .global HAL_DACEx_ConvCpltCallbackCh2
181 .syntax unified
182 .thumb
183 .thumb_func
184 .fpu fpv4-sp-d16
186 HAL_DACEx_ConvCpltCallbackCh2:
187 .LFB380:
123:Core/Src/main.c ****
124:Core/Src/main.c **** void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) {
188 .loc 1 124 0
189 .cfi_startproc
190 @ args = 0, pretend = 0, frame = 0
191 @ frame_needed = 0, uses_anonymous_args = 0
192 .LVL7:
193 0000 08B5 push {r3, lr}
194 .LCFI1:
195 .cfi_def_cfa_offset 8
196 .cfi_offset 3, -8
197 .cfi_offset 14, -4
125:Core/Src/main.c **** HAL_GPIO_TogglePin(OUT_GPIO_Port, OUT_Pin);
198 .loc 1 125 0
199 0002 2021 movs r1, #32
200 0004 0448 ldr r0, .L18
201 .LVL8:
202 0006 FFF7FEFF bl HAL_GPIO_TogglePin
203 .LVL9:
126:Core/Src/main.c **** tx_dac_buffer_toggle = 1;
204 .loc 1 126 0
205 000a 0449 ldr r1, .L18+4
127:Core/Src/main.c **** half_tx_dac_buffer_empty = 1;
206 .loc 1 127 0
207 000c 044A ldr r2, .L18+8
126:Core/Src/main.c **** tx_dac_buffer_toggle = 1;
208 .loc 1 126 0
209 000e 0123 movs r3, #1
210 0010 0B70 strb r3, [r1]
211 .loc 1 127 0
212 0012 1370 strb r3, [r2]
128:Core/Src/main.c **** }
213 .loc 1 128 0
214 0014 08BD pop {r3, pc}
215 .L19:
216 0016 00BF .align 2
217 .L18:
ARM GAS /tmp/ccX7ayIU.s page 7
218 0018 00040048 .word 1207960576
219 001c 00000000 .word tx_dac_buffer_toggle
220 0020 00000000 .word half_tx_dac_buffer_empty
221 .cfi_endproc
222 .LFE380:
224 .section .text.HAL_TIM_PeriodElapsedCallback,"ax",%progbits
225 .align 1
226 .p2align 2,,3
227 .global HAL_TIM_PeriodElapsedCallback
228 .syntax unified
229 .thumb
230 .thumb_func
231 .fpu fpv4-sp-d16
233 HAL_TIM_PeriodElapsedCallback:
234 .LFB381:
129:Core/Src/main.c ****
130:Core/Src/main.c **** /*
131:Core/Src/main.c **** void HAL_DAC_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) {
132:Core/Src/main.c **** tx_dac_buffer_toggle = 0;
133:Core/Src/main.c **** half_tx_dac_buffer_empty = 1;
134:Core/Src/main.c **** }
135:Core/Src/main.c ****
136:Core/Src/main.c **** void HAL_DAC_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) {
137:Core/Src/main.c **** tx_dac_buffer_toggle = 1;
138:Core/Src/main.c **** half_tx_dac_buffer_empty = 1;
139:Core/Src/main.c **** }
140:Core/Src/main.c **** */
141:Core/Src/main.c ****
142:Core/Src/main.c **** // TIMERZ
143:Core/Src/main.c **** // 10 ms
144:Core/Src/main.c **** void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim){
235 .loc 1 144 0
236 .cfi_startproc
237 @ args = 0, pretend = 0, frame = 0
238 @ frame_needed = 0, uses_anonymous_args = 0
239 @ link register save eliminated.
240 .LVL10:
145:Core/Src/main.c **** if (htim->Instance == TIM7){
241 .loc 1 145 0
242 0000 0268 ldr r2, [r0]
243 0002 034B ldr r3, .L22
244 0004 9A42 cmp r2, r3
245 0006 02D1 bne .L20
146:Core/Src/main.c **** tick = 1;
246 .loc 1 146 0
247 0008 024B ldr r3, .L22+4
248 000a 0122 movs r2, #1
249 000c 1A70 strb r2, [r3]
250 .L20:
147:Core/Src/main.c **** }
148:Core/Src/main.c **** }
251 .loc 1 148 0
252 000e 7047 bx lr
253 .L23:
254 .align 2
255 .L22:
256 0010 00140040 .word 1073746944
ARM GAS /tmp/ccX7ayIU.s page 8
257 0014 00000000 .word tick
258 .cfi_endproc
259 .LFE381:
261 .section .text.HAL_UART_RxCpltCallback,"ax",%progbits
262 .align 1
263 .p2align 2,,3
264 .global HAL_UART_RxCpltCallback
265 .syntax unified
266 .thumb
267 .thumb_func
268 .fpu fpv4-sp-d16
270 HAL_UART_RxCpltCallback:
271 .LFB382:
149:Core/Src/main.c ****
150:Core/Src/main.c **** // uart
151:Core/Src/main.c **** void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){
272 .loc 1 151 0
273 .cfi_startproc
274 @ args = 0, pretend = 0, frame = 0
275 @ frame_needed = 0, uses_anonymous_args = 0
276 .LVL11:
277 0000 38B5 push {r3, r4, r5, lr}
278 .LCFI2:
279 .cfi_def_cfa_offset 16
280 .cfi_offset 3, -16
281 .cfi_offset 4, -12
282 .cfi_offset 5, -8
283 .cfi_offset 14, -4
152:Core/Src/main.c **** if (huart == &huart1){
284 .loc 1 152 0
285 0002 084B ldr r3, .L28
286 0004 9842 cmp r0, r3
287 0006 00D0 beq .L27
153:Core/Src/main.c **** enqueue_cmd(uart_rx_buf[0]);
154:Core/Src/main.c **** HAL_UART_Receive_IT(&huart1, uart_rx_buf, 1);
155:Core/Src/main.c **** }
156:Core/Src/main.c **** /*
157:Core/Src/main.c **** if (huart == &huart2){
158:Core/Src/main.c **** enqueue_cmd(uart_rx_buf[0]);
159:Core/Src/main.c **** HAL_UART_Receive_IT(&huart2, uart_rx_buf, 1);
160:Core/Src/main.c **** }
161:Core/Src/main.c **** */
162:Core/Src/main.c **** }
288 .loc 1 162 0
289 0008 38BD pop {r3, r4, r5, pc}
290 .L27:
291 .LBB96:
153:Core/Src/main.c **** enqueue_cmd(uart_rx_buf[0]);
292 .loc 1 153 0
293 000a 074D ldr r5, .L28+4
294 000c 0446 mov r4, r0
295 000e 2878 ldrb r0, [r5] @ zero_extendqisi2
296 .LVL12:
297 0010 FFF7FEFF bl enqueue_cmd
298 .LVL13:
154:Core/Src/main.c **** }
299 .loc 1 154 0
ARM GAS /tmp/ccX7ayIU.s page 9
300 0014 2946 mov r1, r5
301 0016 2046 mov r0, r4
302 0018 0122 movs r2, #1
303 .LBE96:
304 .loc 1 162 0
305 001a BDE83840 pop {r3, r4, r5, lr}
306 .LCFI3:
307 .cfi_restore 14
308 .cfi_restore 5
309 .cfi_restore 4
310 .cfi_restore 3
311 .cfi_def_cfa_offset 0
312 .LVL14:
313 .LBB97:
154:Core/Src/main.c **** }
314 .loc 1 154 0
315 001e FFF7FEBF b HAL_UART_Receive_IT
316 .LVL15:
317 .L29:
318 0022 00BF .align 2
319 .L28:
320 0024 00000000 .word huart1
321 0028 00000000 .word uart_rx_buf
322 .LBE97:
323 .cfi_endproc
324 .LFE382:
326 .section .text.__io_putchar,"ax",%progbits
327 .align 1
328 .p2align 2,,3
329 .global __io_putchar
330 .syntax unified
331 .thumb
332 .thumb_func
333 .fpu fpv4-sp-d16
335 __io_putchar:
336 .LFB383:
163:Core/Src/main.c ****
164:Core/Src/main.c **** // non-DMA
165:Core/Src/main.c **** int __io_putchar(int ch){
337 .loc 1 165 0
338 .cfi_startproc
339 @ args = 0, pretend = 0, frame = 8
340 @ frame_needed = 0, uses_anonymous_args = 0
341 .LVL16:
342 0000 10B5 push {r4, lr}
343 .LCFI4:
344 .cfi_def_cfa_offset 8
345 .cfi_offset 4, -8
346 .cfi_offset 14, -4
347 0002 82B0 sub sp, sp, #8
348 .LCFI5:
349 .cfi_def_cfa_offset 16
166:Core/Src/main.c **** uint8_t c[1];
167:Core/Src/main.c **** c[0] = ch & 0x00FF;
350 .loc 1 167 0
351 0004 02A9 add r1, sp, #8
165:Core/Src/main.c **** uint8_t c[1];
ARM GAS /tmp/ccX7ayIU.s page 10
352 .loc 1 165 0
353 0006 0446 mov r4, r0
354 .loc 1 167 0
355 0008 01F8040D strb r0, [r1, #-4]!
168:Core/Src/main.c **** HAL_UART_Transmit(&huart1, &*c, 1, 10);
356 .loc 1 168 0
357 000c 0A23 movs r3, #10
358 000e 0122 movs r2, #1
359 0010 0248 ldr r0, .L32
360 .LVL17:
361 0012 FFF7FEFF bl HAL_UART_Transmit
362 .LVL18:
169:Core/Src/main.c **** // HAL_UART_Transmit(&huart2, &*c, 1, 10);
170:Core/Src/main.c **** return ch;
171:Core/Src/main.c **** }
363 .loc 1 171 0
364 0016 2046 mov r0, r4
365 0018 02B0 add sp, sp, #8
366 .LCFI6:
367 .cfi_def_cfa_offset 8
368 @ sp needed
369 001a 10BD pop {r4, pc}
370 .LVL19:
371 .L33:
372 .align 2
373 .L32:
374 001c 00000000 .word huart1
375 .cfi_endproc
376 .LFE383:
378 .section .text._write,"ax",%progbits
379 .align 1
380 .p2align 2,,3
381 .global _write
382 .syntax unified
383 .thumb
384 .thumb_func
385 .fpu fpv4-sp-d16
387 _write:
388 .LFB384:
172:Core/Src/main.c ****
173:Core/Src/main.c **** int _write(int file,char *ptr, int len){
389 .loc 1 173 0
390 .cfi_startproc
391 @ args = 0, pretend = 0, frame = 0
392 @ frame_needed = 0, uses_anonymous_args = 0
393 .LVL20:
394 0000 10B5 push {r4, lr}
395 .LCFI7:
396 .cfi_def_cfa_offset 8
397 .cfi_offset 4, -8
398 .cfi_offset 14, -4
174:Core/Src/main.c **** HAL_UART_Transmit_DMA(&huart1, ptr, len);
399 .loc 1 174 0
400 0002 0348 ldr r0, .L36
401 .LVL21:
173:Core/Src/main.c **** HAL_UART_Transmit_DMA(&huart1, ptr, len);
402 .loc 1 173 0
ARM GAS /tmp/ccX7ayIU.s page 11
403 0004 1446 mov r4, r2
404 .loc 1 174 0
405 0006 92B2 uxth r2, r2
406 .LVL22:
407 0008 FFF7FEFF bl HAL_UART_Transmit_DMA
408 .LVL23:
175:Core/Src/main.c **** // HAL_UART_Transmit_DMA(&huart2, ptr, len);
176:Core/Src/main.c **** /* int DataIdx;
177:Core/Src/main.c **** for(DataIdx= 0; DataIdx< len; DataIdx++) {
178:Core/Src/main.c **** __io_putchar(*ptr++);
179:Core/Src/main.c **** }*/
180:Core/Src/main.c **** return len;
181:Core/Src/main.c **** }
409 .loc 1 181 0
410 000c 2046 mov r0, r4
411 000e 10BD pop {r4, pc}
412 .LVL24:
413 .L37:
414 .align 2
415 .L36:
416 0010 00000000 .word huart1
417 .cfi_endproc
418 .LFE384:
420 .section .text.display_write,"ax",%progbits
421 .align 1
422 .p2align 2,,3
423 .global display_write
424 .syntax unified
425 .thumb
426 .thumb_func
427 .fpu fpv4-sp-d16
429 display_write:
430 .LFB385:
182:Core/Src/main.c ****
183:Core/Src/main.c **** int display_write(char *ptr, int len){
431 .loc 1 183 0
432 .cfi_startproc
433 @ args = 0, pretend = 0, frame = 0
434 @ frame_needed = 0, uses_anonymous_args = 0
435 .LVL25:
436 0000 10B5 push {r4, lr}
437 .LCFI8:
438 .cfi_def_cfa_offset 8
439 .cfi_offset 4, -8
440 .cfi_offset 14, -4
184:Core/Src/main.c **** HAL_UART_Transmit_DMA(&huart1, ptr, len);
441 .loc 1 184 0
442 0002 8AB2 uxth r2, r1
183:Core/Src/main.c **** HAL_UART_Transmit_DMA(&huart1, ptr, len);
443 .loc 1 183 0
444 0004 0C46 mov r4, r1
445 .loc 1 184 0
446 0006 0146 mov r1, r0
447 .LVL26:
448 0008 0248 ldr r0, .L40
449 .LVL27:
450 000a FFF7FEFF bl HAL_UART_Transmit_DMA
ARM GAS /tmp/ccX7ayIU.s page 12
451 .LVL28:
185:Core/Src/main.c **** // HAL_UART_Transmit_DMA(&huart2, ptr, len);
186:Core/Src/main.c **** return len;
187:Core/Src/main.c **** }
452 .loc 1 187 0
453 000e 2046 mov r0, r4
454 0010 10BD pop {r4, pc}
455 .LVL29:
456 .L41:
457 0012 00BF .align 2
458 .L40:
459 0014 00000000 .word huart1
460 .cfi_endproc
461 .LFE385:
463 .section .text.start_transmit,"ax",%progbits
464 .align 1
465 .p2align 2,,3
466 .global start_transmit
467 .syntax unified
468 .thumb
469 .thumb_func
470 .fpu fpv4-sp-d16
472 start_transmit:
473 .LFB386:
188:Core/Src/main.c ****
189:Core/Src/main.c **** void start_transmit(void){
474 .loc 1 189 0
475 .cfi_startproc
476 @ args = 0, pretend = 0, frame = 0
477 @ frame_needed = 0, uses_anonymous_args = 0
478 0000 10B5 push {r4, lr}
479 .LCFI9:
480 .cfi_def_cfa_offset 8
481 .cfi_offset 4, -8
482 .cfi_offset 14, -4
190:Core/Src/main.c **** transmit = 1;
483 .loc 1 190 0
484 0002 0B4B ldr r3, .L44
191:Core/Src/main.c **** // ADC
192:Core/Src/main.c **** // HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buffer, ADC_BUFFER_SIZE);
193:Core/Src/main.c ****
194:Core/Src/main.c **** // DAC
195:Core/Src/main.c **** HAL_TIM_Base_Start(&htim8);
196:Core/Src/main.c **** HAL_DAC_Start(&hdac1,DAC_CHANNEL_2);
485 .loc 1 196 0
486 0004 0B4C ldr r4, .L44+4
195:Core/Src/main.c **** HAL_DAC_Start(&hdac1,DAC_CHANNEL_2);
487 .loc 1 195 0
488 0006 0C48 ldr r0, .L44+8
189:Core/Src/main.c **** transmit = 1;
489 .loc 1 189 0
490 0008 82B0 sub sp, sp, #8
491 .LCFI10:
492 .cfi_def_cfa_offset 16
190:Core/Src/main.c **** // ADC
493 .loc 1 190 0
494 000a 0122 movs r2, #1
ARM GAS /tmp/ccX7ayIU.s page 13
495 000c 1A70 strb r2, [r3]
195:Core/Src/main.c **** HAL_DAC_Start(&hdac1,DAC_CHANNEL_2);
496 .loc 1 195 0
497 000e FFF7FEFF bl HAL_TIM_Base_Start
498 .LVL30:
499 .loc 1 196 0
500 0012 2046 mov r0, r4
501 0014 1021 movs r1, #16
502 0016 FFF7FEFF bl HAL_DAC_Start
503 .LVL31:
197:Core/Src/main.c **** HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_2, tx_dac_buffer, (TX_DAC_BUFFER_SIZE * 2), DAC_ALIGN
504 .loc 1 197 0
505 001a 0023 movs r3, #0
506 001c 0093 str r3, [sp]
507 001e 2046 mov r0, r4
508 0020 4FF40063 mov r3, #2048
509 0024 054A ldr r2, .L44+12
510 0026 1021 movs r1, #16
511 0028 FFF7FEFF bl HAL_DAC_Start_DMA
512 .LVL32:
198:Core/Src/main.c **** }
513 .loc 1 198 0
514 002c 02B0 add sp, sp, #8
515 .LCFI11:
516 .cfi_def_cfa_offset 8
517 @ sp needed
518 002e 10BD pop {r4, pc}
519 .L45:
520 .align 2
521 .L44:
522 0030 00000000 .word transmit
523 0034 00000000 .word hdac1
524 0038 00000000 .word htim8
525 003c 00000000 .word tx_dac_buffer
526 .cfi_endproc
527 .LFE386:
529 .section .text.stop_transmit,"ax",%progbits
530 .align 1
531 .p2align 2,,3
532 .global stop_transmit
533 .syntax unified
534 .thumb
535 .thumb_func
536 .fpu fpv4-sp-d16
538 stop_transmit:
539 .LFB387:
199:Core/Src/main.c ****
200:Core/Src/main.c **** void stop_transmit(void){
540 .loc 1 200 0
541 .cfi_startproc
542 @ args = 0, pretend = 0, frame = 0
543 @ frame_needed = 0, uses_anonymous_args = 0
544 0000 10B5 push {r4, lr}
545 .LCFI12:
546 .cfi_def_cfa_offset 8
547 .cfi_offset 4, -8
548 .cfi_offset 14, -4
ARM GAS /tmp/ccX7ayIU.s page 14
201:Core/Src/main.c **** transmit = 0;
549 .loc 1 201 0
550 0002 084B ldr r3, .L48
202:Core/Src/main.c **** // ADC
203:Core/Src/main.c **** // HAL_ADC_Stop_DMA(&hadc1);
204:Core/Src/main.c ****
205:Core/Src/main.c **** // DAC
206:Core/Src/main.c **** HAL_TIM_Base_Stop(&htim8);
207:Core/Src/main.c **** HAL_DAC_Stop(&hdac1,DAC_CHANNEL_2);
551 .loc 1 207 0
552 0004 084C ldr r4, .L48+4
206:Core/Src/main.c **** HAL_DAC_Stop(&hdac1,DAC_CHANNEL_2);
553 .loc 1 206 0
554 0006 0948 ldr r0, .L48+8
201:Core/Src/main.c **** transmit = 0;
555 .loc 1 201 0
556 0008 0022 movs r2, #0
557 000a 1A70 strb r2, [r3]
206:Core/Src/main.c **** HAL_DAC_Stop(&hdac1,DAC_CHANNEL_2);
558 .loc 1 206 0
559 000c FFF7FEFF bl HAL_TIM_Base_Stop
560 .LVL33:
561 .loc 1 207 0
562 0010 2046 mov r0, r4
563 0012 1021 movs r1, #16
564 0014 FFF7FEFF bl HAL_DAC_Stop
565 .LVL34:
208:Core/Src/main.c **** HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_2);
566 .loc 1 208 0
567 0018 2046 mov r0, r4
568 001a 1021 movs r1, #16
209:Core/Src/main.c **** }
569 .loc 1 209 0
570 001c BDE81040 pop {r4, lr}
571 .LCFI13:
572 .cfi_restore 14
573 .cfi_restore 4
574 .cfi_def_cfa_offset 0
208:Core/Src/main.c **** HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_2);
575 .loc 1 208 0
576 0020 FFF7FEBF b HAL_DAC_Stop_DMA
577 .LVL35:
578 .L49:
579 .align 2
580 .L48:
581 0024 00000000 .word transmit
582 0028 00000000 .word hdac1
583 002c 00000000 .word htim8
584 .cfi_endproc
585 .LFE387:
587 .section .text.start_receive,"ax",%progbits
588 .align 1
589 .p2align 2,,3
590 .global start_receive
591 .syntax unified
592 .thumb
593 .thumb_func
ARM GAS /tmp/ccX7ayIU.s page 15
594 .fpu fpv4-sp-d16
596 start_receive:
597 .LFB388:
210:Core/Src/main.c ****
211:Core/Src/main.c **** void start_receive(void){
598 .loc 1 211 0
599 .cfi_startproc
600 @ args = 0, pretend = 0, frame = 0
601 @ frame_needed = 0, uses_anonymous_args = 0
602 0000 30B5 push {r4, r5, lr}
603 .LCFI14:
604 .cfi_def_cfa_offset 12
605 .cfi_offset 4, -12
606 .cfi_offset 5, -8
607 .cfi_offset 14, -4
212:Core/Src/main.c **** receive = 1;
608 .loc 1 212 0
609 0002 0D4B ldr r3, .L52
213:Core/Src/main.c **** // ADC
214:Core/Src/main.c **** HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buffer, ADC_BUFFER_SIZE);
610 .loc 1 214 0
611 0004 0D49 ldr r1, .L52+4
215:Core/Src/main.c ****
216:Core/Src/main.c **** // DAC
217:Core/Src/main.c **** HAL_TIM_Base_Start(&htim6);
218:Core/Src/main.c **** HAL_DAC_Start(&hdac1,DAC_CHANNEL_1);
612 .loc 1 218 0
613 0006 0E4C ldr r4, .L52+8
214:Core/Src/main.c ****
614 .loc 1 214 0
615 0008 0E48 ldr r0, .L52+12
211:Core/Src/main.c **** receive = 1;
616 .loc 1 211 0
617 000a 83B0 sub sp, sp, #12
618 .LCFI15:
619 .cfi_def_cfa_offset 24
214:Core/Src/main.c ****
620 .loc 1 214 0
621 000c 4FF48062 mov r2, #1024
212:Core/Src/main.c **** // ADC
622 .loc 1 212 0
623 0010 0125 movs r5, #1
624 0012 1D70 strb r5, [r3]
214:Core/Src/main.c ****
625 .loc 1 214 0
626 0014 FFF7FEFF bl HAL_ADC_Start_DMA
627 .LVL36:
217:Core/Src/main.c **** HAL_DAC_Start(&hdac1,DAC_CHANNEL_1);
628 .loc 1 217 0
629 0018 0B48 ldr r0, .L52+16
630 001a FFF7FEFF bl HAL_TIM_Base_Start
631 .LVL37:
632 .loc 1 218 0
633 001e 2046 mov r0, r4
634 0020 0021 movs r1, #0
635 0022 FFF7FEFF bl HAL_DAC_Start
636 .LVL38:
ARM GAS /tmp/ccX7ayIU.s page 16
219:Core/Src/main.c **** HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, lf_buffer, (LF_BUFFER_SIZE * 2), DAC_ALIGN_12B_R);
637 .loc 1 219 0
638 0026 0021 movs r1, #0
639 0028 2046 mov r0, r4
640 002a 0091 str r1, [sp]
641 002c 8023 movs r3, #128
642 002e 074A ldr r2, .L52+20
643 0030 FFF7FEFF bl HAL_DAC_Start_DMA
644 .LVL39:
220:Core/Src/main.c **** }
645 .loc 1 220 0
646 0034 03B0 add sp, sp, #12
647 .LCFI16:
648 .cfi_def_cfa_offset 12
649 @ sp needed
650 0036 30BD pop {r4, r5, pc}
651 .L53:
652 .align 2
653 .L52:
654 0038 00000000 .word receive
655 003c 00000000 .word adc_buffer
656 0040 00000000 .word hdac1
657 0044 00000000 .word hadc1
658 0048 00000000 .word htim6
659 004c 00000000 .word lf_buffer
660 .cfi_endproc
661 .LFE388:
663 .section .text.stop_receive,"ax",%progbits
664 .align 1
665 .p2align 2,,3
666 .global stop_receive
667 .syntax unified
668 .thumb
669 .thumb_func
670 .fpu fpv4-sp-d16
672 stop_receive:
673 .LFB389:
221:Core/Src/main.c ****
222:Core/Src/main.c **** void stop_receive(void){
674 .loc 1 222 0
675 .cfi_startproc
676 @ args = 0, pretend = 0, frame = 0
677 @ frame_needed = 0, uses_anonymous_args = 0
678 0000 38B5 push {r3, r4, r5, lr}
679 .LCFI17:
680 .cfi_def_cfa_offset 16
681 .cfi_offset 3, -16
682 .cfi_offset 4, -12
683 .cfi_offset 5, -8
684 .cfi_offset 14, -4
223:Core/Src/main.c **** receive = 0;
685 .loc 1 223 0
686 0002 0A4B ldr r3, .L56
224:Core/Src/main.c **** // ADC
225:Core/Src/main.c **** HAL_ADC_Stop_DMA(&hadc1);
226:Core/Src/main.c ****
227:Core/Src/main.c **** // DAC
ARM GAS /tmp/ccX7ayIU.s page 17
228:Core/Src/main.c **** HAL_TIM_Base_Stop(&htim6);
229:Core/Src/main.c **** HAL_DAC_Stop(&hdac1,DAC_CHANNEL_1);
687 .loc 1 229 0
688 0004 0A4D ldr r5, .L56+4
225:Core/Src/main.c ****
689 .loc 1 225 0
690 0006 0B48 ldr r0, .L56+8
223:Core/Src/main.c **** receive = 0;
691 .loc 1 223 0
692 0008 0024 movs r4, #0
693 000a 1C70 strb r4, [r3]
225:Core/Src/main.c ****
694 .loc 1 225 0
695 000c FFF7FEFF bl HAL_ADC_Stop_DMA
696 .LVL40:
228:Core/Src/main.c **** HAL_DAC_Stop(&hdac1,DAC_CHANNEL_1);
697 .loc 1 228 0
698 0010 0948 ldr r0, .L56+12
699 0012 FFF7FEFF bl HAL_TIM_Base_Stop
700 .LVL41:
701 .loc 1 229 0
702 0016 2146 mov r1, r4
703 0018 2846 mov r0, r5
704 001a FFF7FEFF bl HAL_DAC_Stop
705 .LVL42:
230:Core/Src/main.c **** HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_1);
706 .loc 1 230 0
707 001e 2146 mov r1, r4
708 0020 2846 mov r0, r5
231:Core/Src/main.c **** }
709 .loc 1 231 0
710 0022 BDE83840 pop {r3, r4, r5, lr}
711 .LCFI18:
712 .cfi_restore 14
713 .cfi_restore 5
714 .cfi_restore 4
715 .cfi_restore 3
716 .cfi_def_cfa_offset 0
230:Core/Src/main.c **** HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_1);
717 .loc 1 230 0
718 0026 FFF7FEBF b HAL_DAC_Stop_DMA
719 .LVL43:
720 .L57:
721 002a 00BF .align 2
722 .L56:
723 002c 00000000 .word receive
724 0030 00000000 .word hdac1
725 0034 00000000 .word hadc1
726 0038 00000000 .word htim6
727 .cfi_endproc
728 .LFE389:
730 .section .text.set_gain,"ax",%progbits
731 .align 1
732 .p2align 2,,3
733 .global set_gain
734 .syntax unified
735 .thumb
ARM GAS /tmp/ccX7ayIU.s page 18
736 .thumb_func
737 .fpu fpv4-sp-d16
739 set_gain:
740 .LFB390:
232:Core/Src/main.c ****
233:Core/Src/main.c **** void set_gain(void){
741 .loc 1 233 0
742 .cfi_startproc
743 @ args = 0, pretend = 0, frame = 0
744 @ frame_needed = 0, uses_anonymous_args = 0
745 0000 08B5 push {r3, lr}
746 .LCFI19:
747 .cfi_def_cfa_offset 8
748 .cfi_offset 3, -8
749 .cfi_offset 14, -4
234:Core/Src/main.c **** HAL_OPAMP_Stop(&hopamp1);
750 .loc 1 234 0
751 0002 2148 ldr r0, .L68
752 0004 FFF7FEFF bl HAL_OPAMP_Stop
753 .LVL44:
235:Core/Src/main.c **** switch (gain){
754 .loc 1 235 0
755 0008 204B ldr r3, .L68+4
756 000a 1B68 ldr r3, [r3]
757 000c 023B subs r3, r3, #2
758 000e 042B cmp r3, #4
759 0010 04D8 bhi .L59
760 0012 DFE803F0 tbb [pc, r3]
761 .L61:
762 0016 14 .byte (.L60-.L61)/2
763 0017 1D .byte (.L62-.L61)/2
764 0018 26 .byte (.L63-.L61)/2
765 0019 0B .byte (.L64-.L61)/2
766 001a 2F .byte (.L65-.L61)/2
767 001b 00 .p2align 1
768 .L59:
236:Core/Src/main.c **** case 1:
237:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_2_OR_MINUS_1;
769 .loc 1 237 0
770 001c 1A4B ldr r3, .L68
238:Core/Src/main.c **** break;
239:Core/Src/main.c **** case 2:
240:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_4_OR_MINUS_3;
241:Core/Src/main.c **** break;
242:Core/Src/main.c **** case 3:
243:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_8_OR_MINUS_7;
244:Core/Src/main.c **** break;
245:Core/Src/main.c **** case 4:
246:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_16_OR_MINUS_15;
247:Core/Src/main.c **** break;
248:Core/Src/main.c **** case 5:
249:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_32_OR_MINUS_31;
250:Core/Src/main.c **** break;
251:Core/Src/main.c **** case 6:
252:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_64_OR_MINUS_63;
253:Core/Src/main.c **** break;
254:Core/Src/main.c **** default:
ARM GAS /tmp/ccX7ayIU.s page 19
255:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_2_OR_MINUS_1;
256:Core/Src/main.c **** break;
257:Core/Src/main.c **** }
258:Core/Src/main.c **** HAL_OPAMP_Start(&hopamp1);
771 .loc 1 258 0
772 001e 1A48 ldr r0, .L68
237:Core/Src/main.c **** break;
773 .loc 1 237 0
774 0020 0022 movs r2, #0
775 0022 9A62 str r2, [r3, #40]
259:Core/Src/main.c ****
260:Core/Src/main.c **** }
776 .loc 1 260 0
777 0024 BDE80840 pop {r3, lr}
258:Core/Src/main.c ****
778 .loc 1 258 0
779 0028 FFF7FEBF b HAL_OPAMP_Start
780 .LVL45:
781 .L64:
249:Core/Src/main.c **** break;
782 .loc 1 249 0
783 002c 164B ldr r3, .L68
258:Core/Src/main.c ****
784 .loc 1 258 0
785 002e 1648 ldr r0, .L68
249:Core/Src/main.c **** break;
786 .loc 1 249 0
787 0030 4FF48032 mov r2, #65536
788 0034 9A62 str r2, [r3, #40]
789 .loc 1 260 0
790 0036 BDE80840 pop {r3, lr}
791 .LCFI20:
792 .cfi_remember_state
793 .cfi_restore 14
794 .cfi_restore 3
795 .cfi_def_cfa_offset 0
258:Core/Src/main.c ****
796 .loc 1 258 0
797 003a FFF7FEBF b HAL_OPAMP_Start
798 .LVL46:
799 .L60:
800 .LCFI21:
801 .cfi_restore_state
240:Core/Src/main.c **** break;
802 .loc 1 240 0
803 003e 124B ldr r3, .L68
258:Core/Src/main.c ****
804 .loc 1 258 0
805 0040 1148 ldr r0, .L68
240:Core/Src/main.c **** break;
806 .loc 1 240 0
807 0042 4FF48042 mov r2, #16384
808 0046 9A62 str r2, [r3, #40]
809 .loc 1 260 0
810 0048 BDE80840 pop {r3, lr}
811 .LCFI22:
812 .cfi_remember_state
ARM GAS /tmp/ccX7ayIU.s page 20
813 .cfi_restore 14
814 .cfi_restore 3
815 .cfi_def_cfa_offset 0
258:Core/Src/main.c ****
816 .loc 1 258 0
817 004c FFF7FEBF b HAL_OPAMP_Start
818 .LVL47:
819 .L62:
820 .LCFI23:
821 .cfi_restore_state
243:Core/Src/main.c **** break;
822 .loc 1 243 0
823 0050 0D4B ldr r3, .L68
258:Core/Src/main.c ****
824 .loc 1 258 0
825 0052 0D48 ldr r0, .L68
243:Core/Src/main.c **** break;
826 .loc 1 243 0
827 0054 4FF40042 mov r2, #32768
828 0058 9A62 str r2, [r3, #40]
829 .loc 1 260 0
830 005a BDE80840 pop {r3, lr}
831 .LCFI24:
832 .cfi_remember_state
833 .cfi_restore 14
834 .cfi_restore 3
835 .cfi_def_cfa_offset 0
258:Core/Src/main.c ****
836 .loc 1 258 0
837 005e FFF7FEBF b HAL_OPAMP_Start
838 .LVL48:
839 .L63:
840 .LCFI25:
841 .cfi_restore_state
246:Core/Src/main.c **** break;
842 .loc 1 246 0
843 0062 094B ldr r3, .L68
258:Core/Src/main.c ****
844 .loc 1 258 0
845 0064 0848 ldr r0, .L68
246:Core/Src/main.c **** break;
846 .loc 1 246 0
847 0066 4FF44042 mov r2, #49152
848 006a 9A62 str r2, [r3, #40]
849 .loc 1 260 0
850 006c BDE80840 pop {r3, lr}
851 .LCFI26:
852 .cfi_remember_state
853 .cfi_restore 14
854 .cfi_restore 3
855 .cfi_def_cfa_offset 0
258:Core/Src/main.c ****
856 .loc 1 258 0
857 0070 FFF7FEBF b HAL_OPAMP_Start
858 .LVL49:
859 .L65:
860 .LCFI27:
ARM GAS /tmp/ccX7ayIU.s page 21
861 .cfi_restore_state
252:Core/Src/main.c **** break;
862 .loc 1 252 0
863 0074 044B ldr r3, .L68
258:Core/Src/main.c ****
864 .loc 1 258 0
865 0076 0448 ldr r0, .L68
252:Core/Src/main.c **** break;
866 .loc 1 252 0
867 0078 4FF4A032 mov r2, #81920
868 007c 9A62 str r2, [r3, #40]
869 .loc 1 260 0
870 007e BDE80840 pop {r3, lr}
871 .LCFI28:
872 .cfi_restore 14
873 .cfi_restore 3
874 .cfi_def_cfa_offset 0
258:Core/Src/main.c ****
875 .loc 1 258 0
876 0082 FFF7FEBF b HAL_OPAMP_Start
877 .LVL50:
878 .L69:
879 0086 00BF .align 2
880 .L68:
881 0088 00000000 .word hopamp1
882 008c 00000000 .word gain
883 .cfi_endproc
884 .LFE390:
886 .section .text.SystemClock_Config,"ax",%progbits
887 .align 1
888 .p2align 2,,3
889 .global SystemClock_Config
890 .syntax unified
891 .thumb
892 .thumb_func
893 .fpu fpv4-sp-d16
895 SystemClock_Config:
896 .LFB392:
261:Core/Src/main.c ****
262:Core/Src/main.c ****
263:Core/Src/main.c **** /* USER CODE END 0 */
264:Core/Src/main.c ****
265:Core/Src/main.c **** /**
266:Core/Src/main.c **** * @brief The application entry point.
267:Core/Src/main.c **** * @retval int
268:Core/Src/main.c **** */
269:Core/Src/main.c **** int main(void)
270:Core/Src/main.c **** {
271:Core/Src/main.c **** /* USER CODE BEGIN 1 */
272:Core/Src/main.c **** state_changed = 0;
273:Core/Src/main.c **** display_init();
274:Core/Src/main.c **** state_set_default();
275:Core/Src/main.c **** interface_set_default();
276:Core/Src/main.c **** display_update_mode();
277:Core/Src/main.c **** display_update_state();
278:Core/Src/main.c **** /* USER CODE END 1 */
279:Core/Src/main.c ****
ARM GAS /tmp/ccX7ayIU.s page 22
280:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/
281:Core/Src/main.c ****
282:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
283:Core/Src/main.c **** HAL_Init();
284:Core/Src/main.c ****
285:Core/Src/main.c **** /* USER CODE BEGIN Init */
286:Core/Src/main.c ****
287:Core/Src/main.c **** /* USER CODE END Init */
288:Core/Src/main.c ****
289:Core/Src/main.c **** /* Configure the system clock */
290:Core/Src/main.c **** SystemClock_Config();
291:Core/Src/main.c ****
292:Core/Src/main.c **** /* USER CODE BEGIN SysInit */
293:Core/Src/main.c ****
294:Core/Src/main.c **** /* USER CODE END SysInit */
295:Core/Src/main.c ****
296:Core/Src/main.c **** /* Initialize all configured peripherals */
297:Core/Src/main.c **** MX_GPIO_Init();
298:Core/Src/main.c **** MX_DMA_Init();
299:Core/Src/main.c **** MX_DAC1_Init();
300:Core/Src/main.c **** MX_ADC1_Init();
301:Core/Src/main.c **** MX_TIM7_Init();
302:Core/Src/main.c **** MX_TIM6_Init();
303:Core/Src/main.c **** MX_CORDIC_Init();
304:Core/Src/main.c **** MX_USART1_UART_Init();
305:Core/Src/main.c **** MX_TIM8_Init();
306:Core/Src/main.c **** MX_OPAMP1_Init();
307:Core/Src/main.c **** /* USER CODE BEGIN 2 */
308:Core/Src/main.c **** st2_filter_init();
309:Core/Src/main.c **** audio_filter_init();
310:Core/Src/main.c **** // diag();
311:Core/Src/main.c **** HAL_OPAMP_Start(&hopamp1);
312:Core/Src/main.c **** HAL_TIM_Base_Start_IT(&htim7);
313:Core/Src/main.c **** HAL_UART_Receive_IT(&huart1, uart_rx_buf, 1);
314:Core/Src/main.c **** // HAL_UART_Receive_IT(&huart2, uart_rx_buf, 1);
315:Core/Src/main.c ****
316:Core/Src/main.c **** start_receive();
317:Core/Src/main.c **** /* USER CODE END 2 */
318:Core/Src/main.c ****
319:Core/Src/main.c **** /* Infinite loop */
320:Core/Src/main.c **** /* USER CODE BEGIN WHILE */
321:Core/Src/main.c **** while (1){
322:Core/Src/main.c **** /* USER CODE END WHILE */
323:Core/Src/main.c ****
324:Core/Src/main.c **** /* USER CODE BEGIN 3 */
325:Core/Src/main.c **** if(receive){
326:Core/Src/main.c **** if(rx_adc_buffer_ready){
327:Core/Src/main.c **** HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, SET);
328:Core/Src/main.c **** rx_mixer(adc_buffer, ADC_BUFFER_SIZE, if_I, if_Q, nco1_increment);
329:Core/Src/main.c **** HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, RESET);
330:Core/Src/main.c **** rx_adc_buffer_ready = 0;
331:Core/Src/main.c **** }
332:Core/Src/main.c **** if(half_rx_dac_buffer_empty){
333:Core/Src/main.c **** if (modulation == MOD_DC) dc_demodulator(if_I, LF_BUFFER_SIZE, prefilter_lf_buffer);
334:Core/Src/main.c **** else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_demodulator(if_I, if_Q, LF_BUFFER_SI
335:Core/Src/main.c **** else if (modulation == MOD_AM) am_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer);
336:Core/Src/main.c **** arm_fir_q31(&audio_filter_struct, prefilter_lf_buffer, lf_buffer[lf_buffer_toggle], AUDIO_FILTER
ARM GAS /tmp/ccX7ayIU.s page 23
337:Core/Src/main.c **** half_rx_dac_buffer_empty = 0;
338:Core/Src/main.c **** }
339:Core/Src/main.c **** }
340:Core/Src/main.c **** if (transmit){
341:Core/Src/main.c **** if(half_tx_dac_buffer_empty){
342:Core/Src/main.c **** // HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, SET);
343:Core/Src/main.c **** tx_mixer(tx_dac_buffer[tx_dac_buffer_toggle], TX_DAC_BUFFER_SIZE, if_I, if_Q, nco1_increment);
344:Core/Src/main.c **** half_tx_dac_buffer_empty = 0;
345:Core/Src/main.c **** // HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, RESET);
346:Core/Src/main.c **** }
347:Core/Src/main.c **** if(tx_adc_buffer_ready){
348:Core/Src/main.c **** if (modulation == MOD_DC) dc_modulator(if_I, LF_BUFFER_SIZE, prefilter_lf_buffer);
349:Core/Src/main.c **** else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_modulator(if_I,
350:Core/Src/main.c **** else if (modulation == MOD_AM) am_modulator(if_I, if_Q, LF_BUFFER_SIZE, pre
351:Core/Src/main.c **** }
352:Core/Src/main.c **** }
353:Core/Src/main.c **** if(tick){
354:Core/Src/main.c **** if(receive){
355:Core/Src/main.c **** // TODO
356:Core/Src/main.c **** rx_measure_signal(if_I, LF_BUFFER_SIZE);
357:Core/Src/main.c **** }
358:Core/Src/main.c **** // HAL_GPIO_TogglePin(LD2_GPIO_Port, LD2_Pin);
359:Core/Src/main.c **** while(rx_cmd_rb_in_idx != rx_cmd_rb_out_idx) dequeue_cmd();
360:Core/Src/main.c **** if(state_changed) display_update_state();
361:Core/Src/main.c **** if(uart_tx_buf_in_idx){
362:Core/Src/main.c **** display_write(uart_tx_buf, uart_tx_buf_in_idx);
363:Core/Src/main.c **** uart_tx_buf_in_idx = 0;
364:Core/Src/main.c **** }
365:Core/Src/main.c ****
366:Core/Src/main.c **** tick = 0;
367:Core/Src/main.c **** }
368:Core/Src/main.c **** }
369:Core/Src/main.c **** /* USER CODE END 3 */
370:Core/Src/main.c **** }
371:Core/Src/main.c ****
372:Core/Src/main.c **** /**
373:Core/Src/main.c **** * @brief System Clock Configuration
374:Core/Src/main.c **** * @retval None
375:Core/Src/main.c **** */
376:Core/Src/main.c **** void SystemClock_Config(void)
377:Core/Src/main.c **** {
897 .loc 1 377 0
898 .cfi_startproc
899 @ args = 0, pretend = 0, frame = 144
900 @ frame_needed = 0, uses_anonymous_args = 0
901 0000 30B5 push {r4, r5, lr}
902 .LCFI29:
903 .cfi_def_cfa_offset 12
904 .cfi_offset 4, -12
905 .cfi_offset 5, -8
906 .cfi_offset 14, -4
378:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
907 .loc 1 378 0
908 0002 0021 movs r1, #0
377:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
909 .loc 1 377 0
910 0004 A5B0 sub sp, sp, #148
ARM GAS /tmp/ccX7ayIU.s page 24
911 .LCFI30:
912 .cfi_def_cfa_offset 160
379:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
913 .loc 1 379 0
914 0006 0C46 mov r4, r1
378:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
915 .loc 1 378 0
916 0008 3822 movs r2, #56
917 000a 05A8 add r0, sp, #20
918 000c FFF7FEFF bl memset
919 .LVL51:
380:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
920 .loc 1 380 0
921 0010 2146 mov r1, r4
922 0012 4422 movs r2, #68
923 0014 13A8 add r0, sp, #76
379:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
924 .loc 1 379 0
925 0016 CDE90044 strd r4, r4, [sp]
926 001a CDE90244 strd r4, r4, [sp, #8]
927 001e 0494 str r4, [sp, #16]
928 .loc 1 380 0
929 0020 FFF7FEFF bl memset
930 .LVL52:
381:Core/Src/main.c ****
382:Core/Src/main.c **** /** Configure the main internal regulator output voltage
383:Core/Src/main.c **** */
384:Core/Src/main.c **** HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
931 .loc 1 384 0
932 0024 2046 mov r0, r4
933 0026 FFF7FEFF bl HAL_PWREx_ControlVoltageScaling
934 .LVL53:
385:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters
386:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure.
387:Core/Src/main.c **** */
388:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
389:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
390:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
391:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
935 .loc 1 391 0
936 002a 0324 movs r4, #3
390:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
937 .loc 1 390 0
938 002c 0223 movs r3, #2
388:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
939 .loc 1 388 0
940 002e 0125 movs r5, #1
389:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
941 .loc 1 389 0
942 0030 4FF48031 mov r1, #65536
392:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
393:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 28;
943 .loc 1 393 0
944 0034 1C22 movs r2, #28
394:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
395:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
396:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
ARM GAS /tmp/ccX7ayIU.s page 25
397:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
945 .loc 1 397 0
946 0036 05A8 add r0, sp, #20
389:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
947 .loc 1 389 0
948 0038 CDE90551 strd r5, r1, [sp, #20]
390:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
949 .loc 1 390 0
950 003c 0C93 str r3, [sp, #48]
392:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 28;
951 .loc 1 392 0
952 003e 0E93 str r3, [sp, #56]
395:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
953 .loc 1 395 0
954 0040 CDE91033 strd r3, r3, [sp, #64]
396:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
955 .loc 1 396 0
956 0044 1293 str r3, [sp, #72]
391:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
957 .loc 1 391 0
958 0046 0D94 str r4, [sp, #52]
393:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
959 .loc 1 393 0
960 0048 0F92 str r2, [sp, #60]
961 .loc 1 397 0
962 004a FFF7FEFF bl HAL_RCC_OscConfig
963 .LVL54:
964 004e 08B1 cbz r0, .L71
965 .LBB98:
966 .LBB99:
967 .LBB100:
968 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
ARM GAS /tmp/ccX7ayIU.s page 26
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
ARM GAS /tmp/ccX7ayIU.s page 27
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER
117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
119:Drivers/CMSIS/Include/cmsis_gcc.h ****
120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */
121:Drivers/CMSIS/Include/cmsis_gcc.h ****
122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss
127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly
128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script.
129:Drivers/CMSIS/Include/cmsis_gcc.h ****
130:Drivers/CMSIS/Include/cmsis_gcc.h **** */
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN;
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src;
137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t;
ARM GAS /tmp/ccX7ayIU.s page 28
140:Drivers/CMSIS/Include/cmsis_gcc.h ****
141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t;
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__;
147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__;
148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__;
149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__;
150:Drivers/CMSIS/Include/cmsis_gcc.h ****
151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i];
154:Drivers/CMSIS/Include/cmsis_gcc.h **** }
155:Drivers/CMSIS/Include/cmsis_gcc.h **** }
156:Drivers/CMSIS/Include/cmsis_gcc.h ****
157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u;
160:Drivers/CMSIS/Include/cmsis_gcc.h **** }
161:Drivers/CMSIS/Include/cmsis_gcc.h **** }
162:Drivers/CMSIS/Include/cmsis_gcc.h ****
163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start();
164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
165:Drivers/CMSIS/Include/cmsis_gcc.h ****
166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start
167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
168:Drivers/CMSIS/Include/cmsis_gcc.h ****
169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop
171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
172:Drivers/CMSIS/Include/cmsis_gcc.h ****
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit
175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors
179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
180:Drivers/CMSIS/Include/cmsis_gcc.h ****
181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
184:Drivers/CMSIS/Include/cmsis_gcc.h ****
185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
189:Drivers/CMSIS/Include/cmsis_gcc.h **** */
190:Drivers/CMSIS/Include/cmsis_gcc.h ****
191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
195:Drivers/CMSIS/Include/cmsis_gcc.h **** */
196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
ARM GAS /tmp/ccX7ayIU.s page 29
197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
200:Drivers/CMSIS/Include/cmsis_gcc.h ****
201:Drivers/CMSIS/Include/cmsis_gcc.h ****
202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
206:Drivers/CMSIS/Include/cmsis_gcc.h **** */
207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
969 .loc 2 209 0
970 .syntax unified
971 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
972 0050 72B6 cpsid i
973 @ 0 "" 2
974 .thumb
975 .syntax unified
976 .L72:
977 0052 FEE7 b .L72
978 .L71:
979 0054 0346 mov r3, r0
980 .LBE100:
981 .LBE99:
982 .LBE98:
398:Core/Src/main.c **** {
399:Core/Src/main.c **** Error_Handler();
400:Core/Src/main.c **** }
401:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks
402:Core/Src/main.c **** */
403:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
983 .loc 1 403 0
984 0056 0F22 movs r2, #15
404:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
405:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
406:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
407:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
408:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
409:Core/Src/main.c ****
410:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
985 .loc 1 410 0
986 0058 6846 mov r0, sp
987 005a 0421 movs r1, #4
406:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
988 .loc 1 406 0
989 005c CDE90143 strd r4, r3, [sp, #4]
408:Core/Src/main.c ****
990 .loc 1 408 0
991 0060 CDE90333 strd r3, r3, [sp, #12]
403:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
992 .loc 1 403 0
993 0064 0092 str r2, [sp]
994 .loc 1 410 0
995 0066 FFF7FEFF bl HAL_RCC_ClockConfig
996 .LVL55:
ARM GAS /tmp/ccX7ayIU.s page 30
997 006a 0346 mov r3, r0
998 006c 08B1 cbz r0, .L73
999 .LBB101:
1000 .LBB102:
1001 .LBB103:
1002 .loc 2 209 0
1003 .syntax unified
1004 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1005 006e 72B6 cpsid i
1006 @ 0 "" 2
1007 .thumb
1008 .syntax unified
1009 .L74:
1010 0070 FEE7 b .L74
1011 .L73:
1012 .LBE103:
1013 .LBE102:
1014 .LBE101:
411:Core/Src/main.c **** {
412:Core/Src/main.c **** Error_Handler();
413:Core/Src/main.c **** }
414:Core/Src/main.c **** /** Initializes the peripherals clocks
415:Core/Src/main.c **** */
416:Core/Src/main.c **** PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_ADC12;
1015 .loc 1 416 0
1016 0072 48F20101 movw r1, #32769
417:Core/Src/main.c **** PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
418:Core/Src/main.c **** PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
1017 .loc 1 418 0
1018 0076 4FF00052 mov r2, #536870912
419:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
1019 .loc 1 419 0
1020 007a 13A8 add r0, sp, #76
416:Core/Src/main.c **** PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
1021 .loc 1 416 0
1022 007c CDE91313 strd r1, r3, [sp, #76]
418:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
1023 .loc 1 418 0
1024 0080 2292 str r2, [sp, #136]
1025 .loc 1 419 0
1026 0082 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig
1027 .LVL56:
1028 0086 08B1 cbz r0, .L70
1029 .LBB104:
1030 .LBB105:
1031 .LBB106:
1032 .loc 2 209 0
1033 .syntax unified
1034 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1035 0088 72B6 cpsid i
1036 @ 0 "" 2
1037 .thumb
1038 .syntax unified
1039 .L76:
1040 008a FEE7 b .L76
1041 .L70:
1042 .LBE106:
ARM GAS /tmp/ccX7ayIU.s page 31
1043 .LBE105:
1044 .LBE104:
420:Core/Src/main.c **** {
421:Core/Src/main.c **** Error_Handler();
422:Core/Src/main.c **** }
423:Core/Src/main.c **** }
1045 .loc 1 423 0
1046 008c 25B0 add sp, sp, #148
1047 .LCFI31:
1048 .cfi_def_cfa_offset 12
1049 @ sp needed
1050 008e 30BD pop {r4, r5, pc}
1051 .cfi_endproc
1052 .LFE392:
1054 .section .text.startup.main,"ax",%progbits
1055 .align 1
1056 .p2align 2,,3
1057 .global main
1058 .syntax unified
1059 .thumb
1060 .thumb_func
1061 .fpu fpv4-sp-d16
1063 main:
1064 .LFB391:
270:Core/Src/main.c **** /* USER CODE BEGIN 1 */
1065 .loc 1 270 0
1066 .cfi_startproc
1067 @ Volatile: function does not return.
1068 @ args = 0, pretend = 0, frame = 80
1069 @ frame_needed = 0, uses_anonymous_args = 0
1070 0000 2DE98048 push {r7, fp, lr}
1071 .LCFI32:
1072 .cfi_def_cfa_offset 12
1073 .cfi_offset 7, -12
1074 .cfi_offset 11, -8
1075 .cfi_offset 14, -4
272:Core/Src/main.c **** display_init();
1076 .loc 1 272 0
1077 0004 DFF8F4A2 ldr r10, .L166+52
1078 .LBB193:
1079 .LBB194:
1080 .LBB195:
424:Core/Src/main.c ****
425:Core/Src/main.c **** /**
426:Core/Src/main.c **** * @brief ADC1 Initialization Function
427:Core/Src/main.c **** * @param None
428:Core/Src/main.c **** * @retval None
429:Core/Src/main.c **** */
430:Core/Src/main.c **** static void MX_ADC1_Init(void)
431:Core/Src/main.c **** {
432:Core/Src/main.c ****
433:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */
434:Core/Src/main.c ****
435:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */
436:Core/Src/main.c ****
437:Core/Src/main.c **** ADC_MultiModeTypeDef multimode = {0};
438:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
ARM GAS /tmp/ccX7ayIU.s page 32
439:Core/Src/main.c ****
440:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */
441:Core/Src/main.c ****
442:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */
443:Core/Src/main.c **** /** Common config
444:Core/Src/main.c **** */
445:Core/Src/main.c **** hadc1.Instance = ADC1;
446:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
447:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
448:Core/Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
449:Core/Src/main.c **** hadc1.Init.GainCompensation = 0;
450:Core/Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
451:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
452:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
453:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = ENABLE;
454:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
455:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
456:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
457:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
458:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE;
459:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
460:Core/Src/main.c **** hadc1.Init.OversamplingMode = ENABLE;
461:Core/Src/main.c **** hadc1.Init.Oversampling.Ratio = ADC_OVERSAMPLING_RATIO_2;
462:Core/Src/main.c **** hadc1.Init.Oversampling.RightBitShift = ADC_RIGHTBITSHIFT_NONE;
463:Core/Src/main.c **** hadc1.Init.Oversampling.TriggeredMode = ADC_TRIGGEREDMODE_SINGLE_TRIGGER;
464:Core/Src/main.c **** hadc1.Init.Oversampling.OversamplingStopReset = ADC_REGOVERSAMPLING_CONTINUED_MODE;
465:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
466:Core/Src/main.c **** {
467:Core/Src/main.c **** Error_Handler();
468:Core/Src/main.c **** }
469:Core/Src/main.c **** /** Configure the ADC multi-mode
470:Core/Src/main.c **** */
471:Core/Src/main.c **** multimode.Mode = ADC_MODE_INDEPENDENT;
472:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
473:Core/Src/main.c **** {
474:Core/Src/main.c **** Error_Handler();
475:Core/Src/main.c **** }
476:Core/Src/main.c **** /** Configure Regular Channel
477:Core/Src/main.c **** */
478:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_VOPAMP1;
479:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
480:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
481:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
482:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
483:Core/Src/main.c **** sConfig.Offset = 0;
484:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
485:Core/Src/main.c **** {
486:Core/Src/main.c **** Error_Handler();
487:Core/Src/main.c **** }
488:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */
489:Core/Src/main.c ****
490:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */
491:Core/Src/main.c ****
492:Core/Src/main.c **** }
493:Core/Src/main.c ****
494:Core/Src/main.c **** /**
495:Core/Src/main.c **** * @brief CORDIC Initialization Function
ARM GAS /tmp/ccX7ayIU.s page 33
496:Core/Src/main.c **** * @param None
497:Core/Src/main.c **** * @retval None
498:Core/Src/main.c **** */
499:Core/Src/main.c **** static void MX_CORDIC_Init(void)
500:Core/Src/main.c **** {
501:Core/Src/main.c ****
502:Core/Src/main.c **** /* USER CODE BEGIN CORDIC_Init 0 */
503:Core/Src/main.c **** // CORDIC_HandleTypeDef hcordic = {0};
504:Core/Src/main.c **** CORDIC_ConfigTypeDef sConfig = {0};
505:Core/Src/main.c **** sConfig.Function = CORDIC_FUNCTION_SINE;
506:Core/Src/main.c **** sConfig.Precision = CORDIC_PRECISION_4CYCLES;
507:Core/Src/main.c **** sConfig.Scale = CORDIC_SCALE_0;
508:Core/Src/main.c **** sConfig.NbWrite = CORDIC_NBWRITE_1;
509:Core/Src/main.c **** sConfig.NbRead = CORDIC_NBREAD_1;
510:Core/Src/main.c **** sConfig.InSize = CORDIC_INSIZE_32BITS;
511:Core/Src/main.c **** sConfig.OutSize = CORDIC_OUTSIZE_16BITS;
512:Core/Src/main.c **** /* USER CODE END CORDIC_Init 0 */
513:Core/Src/main.c ****
514:Core/Src/main.c **** /* USER CODE BEGIN CORDIC_Init 1 */
515:Core/Src/main.c **** /* USER CODE END CORDIC_Init 1 */
516:Core/Src/main.c **** hcordic.Instance = CORDIC;
517:Core/Src/main.c **** if (HAL_CORDIC_Init(&hcordic) != HAL_OK)
518:Core/Src/main.c **** {
519:Core/Src/main.c **** Error_Handler();
520:Core/Src/main.c **** }
521:Core/Src/main.c **** /* USER CODE BEGIN CORDIC_Init 2 */
522:Core/Src/main.c **** HAL_CORDIC_Configure(&hcordic, &sConfig);
523:Core/Src/main.c **** /* USER CODE END CORDIC_Init 2 */
524:Core/Src/main.c ****
525:Core/Src/main.c **** }
526:Core/Src/main.c ****
527:Core/Src/main.c **** /**
528:Core/Src/main.c **** * @brief DAC1 Initialization Function
529:Core/Src/main.c **** * @param None
530:Core/Src/main.c **** * @retval None
531:Core/Src/main.c **** */
532:Core/Src/main.c **** static void MX_DAC1_Init(void)
533:Core/Src/main.c **** {
534:Core/Src/main.c ****
535:Core/Src/main.c **** /* USER CODE BEGIN DAC1_Init 0 */
536:Core/Src/main.c ****
537:Core/Src/main.c **** /* USER CODE END DAC1_Init 0 */
538:Core/Src/main.c ****
539:Core/Src/main.c **** DAC_ChannelConfTypeDef sConfig = {0};
540:Core/Src/main.c ****
541:Core/Src/main.c **** /* USER CODE BEGIN DAC1_Init 1 */
542:Core/Src/main.c ****
543:Core/Src/main.c **** /* USER CODE END DAC1_Init 1 */
544:Core/Src/main.c **** /** DAC Initialization
545:Core/Src/main.c **** */
546:Core/Src/main.c **** hdac1.Instance = DAC1;
547:Core/Src/main.c **** if (HAL_DAC_Init(&hdac1) != HAL_OK)
548:Core/Src/main.c **** {
549:Core/Src/main.c **** Error_Handler();
550:Core/Src/main.c **** }
551:Core/Src/main.c **** /** DAC channel OUT1 config
552:Core/Src/main.c **** */
ARM GAS /tmp/ccX7ayIU.s page 34
553:Core/Src/main.c **** sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC;
554:Core/Src/main.c **** sConfig.DAC_DMADoubleDataMode = DISABLE;
555:Core/Src/main.c **** sConfig.DAC_SignedFormat = ENABLE;
556:Core/Src/main.c **** sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
557:Core/Src/main.c **** sConfig.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
558:Core/Src/main.c **** sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE;
559:Core/Src/main.c **** sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
560:Core/Src/main.c **** sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_EXTERNAL;
561:Core/Src/main.c **** sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
562:Core/Src/main.c **** if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK)
563:Core/Src/main.c **** {
564:Core/Src/main.c **** Error_Handler();
565:Core/Src/main.c **** }
566:Core/Src/main.c **** /** DAC channel OUT2 config
567:Core/Src/main.c **** */
568:Core/Src/main.c **** sConfig.DAC_SignedFormat = DISABLE;
569:Core/Src/main.c **** sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
570:Core/Src/main.c **** if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
571:Core/Src/main.c **** {
572:Core/Src/main.c **** Error_Handler();
573:Core/Src/main.c **** }
574:Core/Src/main.c **** /* USER CODE BEGIN DAC1_Init 2 */
575:Core/Src/main.c ****
576:Core/Src/main.c **** /* USER CODE END DAC1_Init 2 */
577:Core/Src/main.c ****
578:Core/Src/main.c **** }
579:Core/Src/main.c ****
580:Core/Src/main.c **** /**
581:Core/Src/main.c **** * @brief OPAMP1 Initialization Function
582:Core/Src/main.c **** * @param None
583:Core/Src/main.c **** * @retval None
584:Core/Src/main.c **** */
585:Core/Src/main.c **** static void MX_OPAMP1_Init(void)
586:Core/Src/main.c **** {
587:Core/Src/main.c ****
588:Core/Src/main.c **** /* USER CODE BEGIN OPAMP1_Init 0 */
589:Core/Src/main.c ****
590:Core/Src/main.c **** /* USER CODE END OPAMP1_Init 0 */
591:Core/Src/main.c ****
592:Core/Src/main.c **** /* USER CODE BEGIN OPAMP1_Init 1 */
593:Core/Src/main.c ****
594:Core/Src/main.c **** /* USER CODE END OPAMP1_Init 1 */
595:Core/Src/main.c **** hopamp1.Instance = OPAMP1;
596:Core/Src/main.c **** hopamp1.Init.PowerMode = OPAMP_POWERMODE_HIGHSPEED;
597:Core/Src/main.c **** hopamp1.Init.Mode = OPAMP_PGA_MODE;
598:Core/Src/main.c **** hopamp1.Init.NonInvertingInput = OPAMP_NONINVERTINGINPUT_IO0;
599:Core/Src/main.c **** hopamp1.Init.InternalOutput = ENABLE;
600:Core/Src/main.c **** hopamp1.Init.TimerControlledMuxmode = OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE;
601:Core/Src/main.c **** hopamp1.Init.PgaConnect = OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS;
602:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_64_OR_MINUS_63;
603:Core/Src/main.c **** hopamp1.Init.UserTrimming = OPAMP_TRIMMING_FACTORY;
604:Core/Src/main.c **** if (HAL_OPAMP_Init(&hopamp1) != HAL_OK)
605:Core/Src/main.c **** {
606:Core/Src/main.c **** Error_Handler();
607:Core/Src/main.c **** }
608:Core/Src/main.c **** /* USER CODE BEGIN OPAMP1_Init 2 */
609:Core/Src/main.c ****
ARM GAS /tmp/ccX7ayIU.s page 35
610:Core/Src/main.c **** /* USER CODE END OPAMP1_Init 2 */
611:Core/Src/main.c ****
612:Core/Src/main.c **** }
613:Core/Src/main.c ****
614:Core/Src/main.c **** /**
615:Core/Src/main.c **** * @brief TIM6 Initialization Function
616:Core/Src/main.c **** * @param None
617:Core/Src/main.c **** * @retval None
618:Core/Src/main.c **** */
619:Core/Src/main.c **** static void MX_TIM6_Init(void)
620:Core/Src/main.c **** {
621:Core/Src/main.c ****
622:Core/Src/main.c **** /* USER CODE BEGIN TIM6_Init 0 */
623:Core/Src/main.c ****
624:Core/Src/main.c **** /* USER CODE END TIM6_Init 0 */
625:Core/Src/main.c ****
626:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
627:Core/Src/main.c ****
628:Core/Src/main.c **** /* USER CODE BEGIN TIM6_Init 1 */
629:Core/Src/main.c ****
630:Core/Src/main.c **** /* USER CODE END TIM6_Init 1 */
631:Core/Src/main.c **** htim6.Instance = TIM6;
632:Core/Src/main.c **** htim6.Init.Prescaler = 0;
633:Core/Src/main.c **** htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
634:Core/Src/main.c **** htim6.Init.Period = 7679;
635:Core/Src/main.c **** htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
636:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
637:Core/Src/main.c **** {
638:Core/Src/main.c **** Error_Handler();
639:Core/Src/main.c **** }
640:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
641:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
642:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
643:Core/Src/main.c **** {
644:Core/Src/main.c **** Error_Handler();
645:Core/Src/main.c **** }
646:Core/Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */
647:Core/Src/main.c ****
648:Core/Src/main.c **** /* USER CODE END TIM6_Init 2 */
649:Core/Src/main.c ****
650:Core/Src/main.c **** }
651:Core/Src/main.c ****
652:Core/Src/main.c **** /**
653:Core/Src/main.c **** * @brief TIM7 Initialization Function
654:Core/Src/main.c **** * @param None
655:Core/Src/main.c **** * @retval None
656:Core/Src/main.c **** */
657:Core/Src/main.c **** static void MX_TIM7_Init(void)
658:Core/Src/main.c **** {
659:Core/Src/main.c ****
660:Core/Src/main.c **** /* USER CODE BEGIN TIM7_Init 0 */
661:Core/Src/main.c ****
662:Core/Src/main.c **** /* USER CODE END TIM7_Init 0 */
663:Core/Src/main.c ****
664:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
665:Core/Src/main.c ****
666:Core/Src/main.c **** /* USER CODE BEGIN TIM7_Init 1 */
ARM GAS /tmp/ccX7ayIU.s page 36
667:Core/Src/main.c ****
668:Core/Src/main.c **** /* USER CODE END TIM7_Init 1 */
669:Core/Src/main.c **** htim7.Instance = TIM7;
670:Core/Src/main.c **** htim7.Init.Prescaler = 1679;
671:Core/Src/main.c **** htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
672:Core/Src/main.c **** htim7.Init.Period = 999;
673:Core/Src/main.c **** htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
674:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
675:Core/Src/main.c **** {
676:Core/Src/main.c **** Error_Handler();
677:Core/Src/main.c **** }
678:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
679:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
680:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
681:Core/Src/main.c **** {
682:Core/Src/main.c **** Error_Handler();
683:Core/Src/main.c **** }
684:Core/Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */
685:Core/Src/main.c ****
686:Core/Src/main.c **** /* USER CODE END TIM7_Init 2 */
687:Core/Src/main.c ****
688:Core/Src/main.c **** }
689:Core/Src/main.c ****
690:Core/Src/main.c **** /**
691:Core/Src/main.c **** * @brief TIM8 Initialization Function
692:Core/Src/main.c **** * @param None
693:Core/Src/main.c **** * @retval None
694:Core/Src/main.c **** */
695:Core/Src/main.c **** static void MX_TIM8_Init(void)
696:Core/Src/main.c **** {
697:Core/Src/main.c ****
698:Core/Src/main.c **** /* USER CODE BEGIN TIM8_Init 0 */
699:Core/Src/main.c ****
700:Core/Src/main.c **** /* USER CODE END TIM8_Init 0 */
701:Core/Src/main.c ****
702:Core/Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0};
703:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
704:Core/Src/main.c ****
705:Core/Src/main.c **** /* USER CODE BEGIN TIM8_Init 1 */
706:Core/Src/main.c ****
707:Core/Src/main.c **** /* USER CODE END TIM8_Init 1 */
708:Core/Src/main.c **** htim8.Instance = TIM8;
709:Core/Src/main.c **** htim8.Init.Prescaler = 0;
710:Core/Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
711:Core/Src/main.c **** htim8.Init.Period = 239;
712:Core/Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
713:Core/Src/main.c **** htim8.Init.RepetitionCounter = 0;
714:Core/Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
715:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
716:Core/Src/main.c **** {
717:Core/Src/main.c **** Error_Handler();
718:Core/Src/main.c **** }
719:Core/Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
720:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
721:Core/Src/main.c **** {
722:Core/Src/main.c **** Error_Handler();
723:Core/Src/main.c **** }
ARM GAS /tmp/ccX7ayIU.s page 37
724:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
725:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
726:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
727:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
728:Core/Src/main.c **** {
729:Core/Src/main.c **** Error_Handler();
730:Core/Src/main.c **** }
731:Core/Src/main.c **** /* USER CODE BEGIN TIM8_Init 2 */
732:Core/Src/main.c ****
733:Core/Src/main.c **** /* USER CODE END TIM8_Init 2 */
734:Core/Src/main.c ****
735:Core/Src/main.c **** }
736:Core/Src/main.c ****
737:Core/Src/main.c **** /**
738:Core/Src/main.c **** * @brief USART1 Initialization Function
739:Core/Src/main.c **** * @param None
740:Core/Src/main.c **** * @retval None
741:Core/Src/main.c **** */
742:Core/Src/main.c **** static void MX_USART1_UART_Init(void)
743:Core/Src/main.c **** {
744:Core/Src/main.c ****
745:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */
746:Core/Src/main.c ****
747:Core/Src/main.c **** /* USER CODE END USART1_Init 0 */
748:Core/Src/main.c ****
749:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */
750:Core/Src/main.c ****
751:Core/Src/main.c **** /* USER CODE END USART1_Init 1 */
752:Core/Src/main.c **** huart1.Instance = USART1;
753:Core/Src/main.c **** huart1.Init.BaudRate = 115200;
754:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B;
755:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1;
756:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE;
757:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX;
758:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
759:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16;
760:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
761:Core/Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
762:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
763:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK)
764:Core/Src/main.c **** {
765:Core/Src/main.c **** Error_Handler();
766:Core/Src/main.c **** }
767:Core/Src/main.c **** if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
768:Core/Src/main.c **** {
769:Core/Src/main.c **** Error_Handler();
770:Core/Src/main.c **** }
771:Core/Src/main.c **** if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
772:Core/Src/main.c **** {
773:Core/Src/main.c **** Error_Handler();
774:Core/Src/main.c **** }
775:Core/Src/main.c **** if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
776:Core/Src/main.c **** {
777:Core/Src/main.c **** Error_Handler();
778:Core/Src/main.c **** }
779:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */
780:Core/Src/main.c ****
ARM GAS /tmp/ccX7ayIU.s page 38
781:Core/Src/main.c **** /* USER CODE END USART1_Init 2 */
782:Core/Src/main.c ****
783:Core/Src/main.c **** }
784:Core/Src/main.c ****
785:Core/Src/main.c **** /**
786:Core/Src/main.c **** * Enable DMA controller clock
787:Core/Src/main.c **** */
788:Core/Src/main.c **** static void MX_DMA_Init(void)
789:Core/Src/main.c **** {
790:Core/Src/main.c ****
791:Core/Src/main.c **** /* DMA controller clock enable */
792:Core/Src/main.c **** __HAL_RCC_DMAMUX1_CLK_ENABLE();
793:Core/Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
794:Core/Src/main.c ****
795:Core/Src/main.c **** /* DMA interrupt init */
796:Core/Src/main.c **** /* DMA1_Channel1_IRQn interrupt configuration */
797:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
798:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
799:Core/Src/main.c **** /* DMA1_Channel2_IRQn interrupt configuration */
800:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
801:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
802:Core/Src/main.c **** /* DMA1_Channel4_IRQn interrupt configuration */
803:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
804:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
805:Core/Src/main.c **** /* DMA1_Channel5_IRQn interrupt configuration */
806:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
807:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
808:Core/Src/main.c ****
809:Core/Src/main.c **** }
810:Core/Src/main.c ****
811:Core/Src/main.c **** /**
812:Core/Src/main.c **** * @brief GPIO Initialization Function
813:Core/Src/main.c **** * @param None
814:Core/Src/main.c **** * @retval None
815:Core/Src/main.c **** */
816:Core/Src/main.c **** static void MX_GPIO_Init(void)
817:Core/Src/main.c **** {
818:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
819:Core/Src/main.c ****
820:Core/Src/main.c **** /* GPIO Ports Clock Enable */
821:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE();
1081 .loc 1 821 0
1082 0008 AF4D ldr r5, .L166
1083 .LBE195:
1084 .LBE194:
1085 .LBE193:
1086 .LBB202:
1087 .LBB203:
546:Core/Src/main.c **** if (HAL_DAC_Init(&hdac1) != HAL_OK)
1088 .loc 1 546 0
1089 000a DFF8F482 ldr r8, .L166+56
1090 .LBE203:
1091 .LBE202:
270:Core/Src/main.c **** /* USER CODE BEGIN 1 */
1092 .loc 1 270 0
1093 000e 97B0 sub sp, sp, #92
1094 .LCFI33:
ARM GAS /tmp/ccX7ayIU.s page 39
1095 .cfi_def_cfa_offset 104
272:Core/Src/main.c **** display_init();
1096 .loc 1 272 0
1097 0010 0024 movs r4, #0
1098 0012 AAF80040 strh r4, [r10] @ movhi
273:Core/Src/main.c **** state_set_default();
1099 .loc 1 273 0
1100 0016 FFF7FEFF bl display_init
1101 .LVL57:
274:Core/Src/main.c **** interface_set_default();
1102 .loc 1 274 0
1103 001a FFF7FEFF bl state_set_default
1104 .LVL58:
275:Core/Src/main.c **** display_update_mode();
1105 .loc 1 275 0
1106 001e FFF7FEFF bl interface_set_default
1107 .LVL59:
276:Core/Src/main.c **** display_update_state();
1108 .loc 1 276 0
1109 0022 FFF7FEFF bl display_update_mode
1110 .LVL60:
277:Core/Src/main.c **** /* USER CODE END 1 */
1111 .loc 1 277 0
1112 0026 FFF7FEFF bl display_update_state
1113 .LVL61:
283:Core/Src/main.c ****
1114 .loc 1 283 0
1115 002a FFF7FEFF bl HAL_Init
1116 .LVL62:
290:Core/Src/main.c ****
1117 .loc 1 290 0
1118 002e FFF7FEFF bl SystemClock_Config
1119 .LVL63:
1120 .LBB214:
1121 .LBB201:
818:Core/Src/main.c ****
1122 .loc 1 818 0
1123 0032 CDE90A44 strd r4, r4, [sp, #40]
1124 0036 CDE90C44 strd r4, r4, [sp, #48]
1125 003a 0E94 str r4, [sp, #56]
1126 .LBB196:
1127 .loc 1 821 0
1128 003c EB6C ldr r3, [r5, #76]
1129 .LBE196:
822:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
823:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
824:Core/Src/main.c ****
825:Core/Src/main.c **** /*Configure GPIO pin Output Level */
826:Core/Src/main.c **** HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, GPIO_PIN_RESET);
1130 .loc 1 826 0
1131 003e A348 ldr r0, .L166+4
1132 .LBB197:
821:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
1133 .loc 1 821 0
1134 0040 43F02003 orr r3, r3, #32
1135 0044 EB64 str r3, [r5, #76]
1136 0046 EB6C ldr r3, [r5, #76]
ARM GAS /tmp/ccX7ayIU.s page 40
1137 0048 03F02003 and r3, r3, #32
1138 004c 0493 str r3, [sp, #16]
1139 004e 049B ldr r3, [sp, #16]
1140 .LBE197:
1141 .LBB198:
822:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
1142 .loc 1 822 0
1143 0050 EB6C ldr r3, [r5, #76]
1144 0052 43F00103 orr r3, r3, #1
1145 0056 EB64 str r3, [r5, #76]
1146 0058 EB6C ldr r3, [r5, #76]
1147 005a 03F00103 and r3, r3, #1
1148 005e 0593 str r3, [sp, #20]
1149 0060 059B ldr r3, [sp, #20]
1150 .LBE198:
1151 .LBB199:
823:Core/Src/main.c ****
1152 .loc 1 823 0
1153 0062 EB6C ldr r3, [r5, #76]
1154 0064 43F00203 orr r3, r3, #2
1155 0068 EB64 str r3, [r5, #76]
1156 006a EB6C ldr r3, [r5, #76]
1157 006c 03F00203 and r3, r3, #2
1158 .LBE199:
1159 .loc 1 826 0
1160 0070 2246 mov r2, r4
1161 0072 2021 movs r1, #32
1162 .LBB200:
823:Core/Src/main.c ****
1163 .loc 1 823 0
1164 0074 0693 str r3, [sp, #24]
1165 0076 069B ldr r3, [sp, #24]
1166 .LBE200:
827:Core/Src/main.c ****
828:Core/Src/main.c **** /*Configure GPIO pin : OUT_Pin */
829:Core/Src/main.c **** GPIO_InitStruct.Pin = OUT_Pin;
1167 .loc 1 829 0
1168 0078 0E46 mov r6, r1
830:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
1169 .loc 1 830 0
1170 007a 0127 movs r7, #1
826:Core/Src/main.c ****
1171 .loc 1 826 0
1172 007c FFF7FEFF bl HAL_GPIO_WritePin
1173 .LVL64:
831:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
832:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
833:Core/Src/main.c **** HAL_GPIO_Init(OUT_GPIO_Port, &GPIO_InitStruct);
1174 .loc 1 833 0
1175 0080 0AA9 add r1, sp, #40
1176 0082 9248 ldr r0, .L166+4
832:Core/Src/main.c **** HAL_GPIO_Init(OUT_GPIO_Port, &GPIO_InitStruct);
1177 .loc 1 832 0
1178 0084 CDE90C44 strd r4, r4, [sp, #48]
830:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1179 .loc 1 830 0
1180 0088 CDE90A67 strd r6, r7, [sp, #40]
ARM GAS /tmp/ccX7ayIU.s page 41
1181 .loc 1 833 0
1182 008c FFF7FEFF bl HAL_GPIO_Init
1183 .LVL65:
1184 .LBE201:
1185 .LBE214:
1186 .LBB215:
1187 .LBB216:
1188 .LBB217:
792:Core/Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
1189 .loc 1 792 0
1190 0090 AB6C ldr r3, [r5, #72]
1191 0092 43F00403 orr r3, r3, #4
1192 0096 AB64 str r3, [r5, #72]
1193 0098 AB6C ldr r3, [r5, #72]
1194 009a 03F00403 and r3, r3, #4
1195 009e 0293 str r3, [sp, #8]
1196 00a0 029B ldr r3, [sp, #8]
1197 .LBE217:
1198 .LBB218:
793:Core/Src/main.c ****
1199 .loc 1 793 0
1200 00a2 AB6C ldr r3, [r5, #72]
1201 00a4 3B43 orrs r3, r3, r7
1202 00a6 AB64 str r3, [r5, #72]
1203 00a8 AB6C ldr r3, [r5, #72]
1204 00aa 3B40 ands r3, r3, r7
1205 .LBE218:
797:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
1206 .loc 1 797 0
1207 00ac 2246 mov r2, r4
1208 00ae 2146 mov r1, r4
1209 .LBB219:
793:Core/Src/main.c ****
1210 .loc 1 793 0
1211 00b0 0393 str r3, [sp, #12]
1212 .LBE219:
797:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
1213 .loc 1 797 0
1214 00b2 0B20 movs r0, #11
1215 .LBB220:
793:Core/Src/main.c ****
1216 .loc 1 793 0
1217 00b4 039B ldr r3, [sp, #12]
1218 .LBE220:
797:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
1219 .loc 1 797 0
1220 00b6 FFF7FEFF bl HAL_NVIC_SetPriority
1221 .LVL66:
798:Core/Src/main.c **** /* DMA1_Channel2_IRQn interrupt configuration */
1222 .loc 1 798 0
1223 00ba 0B20 movs r0, #11
1224 00bc FFF7FEFF bl HAL_NVIC_EnableIRQ
1225 .LVL67:
800:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
1226 .loc 1 800 0
1227 00c0 2246 mov r2, r4
1228 00c2 2146 mov r1, r4
ARM GAS /tmp/ccX7ayIU.s page 42
1229 00c4 0C20 movs r0, #12
1230 00c6 FFF7FEFF bl HAL_NVIC_SetPriority
1231 .LVL68:
801:Core/Src/main.c **** /* DMA1_Channel4_IRQn interrupt configuration */
1232 .loc 1 801 0
1233 00ca 0C20 movs r0, #12
1234 00cc FFF7FEFF bl HAL_NVIC_EnableIRQ
1235 .LVL69:
803:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
1236 .loc 1 803 0
1237 00d0 2246 mov r2, r4
1238 00d2 2146 mov r1, r4
1239 00d4 0E20 movs r0, #14
1240 00d6 FFF7FEFF bl HAL_NVIC_SetPriority
1241 .LVL70:
804:Core/Src/main.c **** /* DMA1_Channel5_IRQn interrupt configuration */
1242 .loc 1 804 0
1243 00da 0E20 movs r0, #14
1244 00dc FFF7FEFF bl HAL_NVIC_EnableIRQ
1245 .LVL71:
806:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
1246 .loc 1 806 0
1247 00e0 2246 mov r2, r4
1248 00e2 2146 mov r1, r4
1249 00e4 0F20 movs r0, #15
1250 00e6 FFF7FEFF bl HAL_NVIC_SetPriority
1251 .LVL72:
807:Core/Src/main.c ****
1252 .loc 1 807 0
1253 00ea 0F20 movs r0, #15
1254 00ec FFF7FEFF bl HAL_NVIC_EnableIRQ
1255 .LVL73:
1256 .LBE216:
1257 .LBE215:
1258 .LBB221:
1259 .LBB213:
539:Core/Src/main.c ****
1260 .loc 1 539 0
1261 00f0 2146 mov r1, r4
1262 00f2 0AA8 add r0, sp, #40
1263 00f4 3022 movs r2, #48
1264 00f6 FFF7FEFF bl memset
1265 .LVL74:
546:Core/Src/main.c **** if (HAL_DAC_Init(&hdac1) != HAL_OK)
1266 .loc 1 546 0
1267 00fa 754B ldr r3, .L166+8
1268 00fc C8F80030 str r3, [r8]
547:Core/Src/main.c **** {
1269 .loc 1 547 0
1270 0100 4046 mov r0, r8
1271 0102 FFF7FEFF bl HAL_DAC_Init
1272 .LVL75:
1273 0106 08B1 cbz r0, .L79
1274 .LBB204:
1275 .LBB205:
1276 .LBB206:
1277 .loc 2 209 0
ARM GAS /tmp/ccX7ayIU.s page 43
1278 .syntax unified
1279 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1280 0108 72B6 cpsid i
1281 @ 0 "" 2
1282 .thumb
1283 .syntax unified
1284 .L80:
1285 010a FEE7 b .L80
1286 .L79:
1287 .LBE206:
1288 .LBE205:
1289 .LBE204:
556:Core/Src/main.c **** sConfig.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
1290 .loc 1 556 0
1291 010c 0024 movs r4, #0
1292 010e 1E25 movs r5, #30
1293 0110 CDE90C45 strd r4, [sp, #48]
1294 0114 0024 movs r4, #0
1295 0116 0025 movs r5, #0
553:Core/Src/main.c **** sConfig.DAC_DMADoubleDataMode = DISABLE;
1296 .loc 1 553 0
1297 0118 0223 movs r3, #2
556:Core/Src/main.c **** sConfig.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
1298 .loc 1 556 0
1299 011a CDE90E45 strd r4, [sp, #56]
562:Core/Src/main.c **** {
1300 .loc 1 562 0
1301 011e 0246 mov r2, r0
554:Core/Src/main.c **** sConfig.DAC_SignedFormat = ENABLE;
1302 .loc 1 554 0
1303 0120 8DF82C00 strb r0, [sp, #44]
562:Core/Src/main.c **** {
1304 .loc 1 562 0
1305 0124 0AA9 add r1, sp, #40
556:Core/Src/main.c **** sConfig.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
1306 .loc 1 556 0
1307 0126 0124 movs r4, #1
1308 0128 0025 movs r5, #0
562:Core/Src/main.c **** {
1309 .loc 1 562 0
1310 012a 4046 mov r0, r8
553:Core/Src/main.c **** sConfig.DAC_DMADoubleDataMode = DISABLE;
1311 .loc 1 553 0
1312 012c 0A93 str r3, [sp, #40]
555:Core/Src/main.c **** sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
1313 .loc 1 555 0
1314 012e 8DF82D70 strb r7, [sp, #45]
556:Core/Src/main.c **** sConfig.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
1315 .loc 1 556 0
1316 0132 CDE91045 strd r4, [sp, #64]
562:Core/Src/main.c **** {
1317 .loc 1 562 0
1318 0136 FFF7FEFF bl HAL_DAC_ConfigChannel
1319 .LVL76:
1320 013a 0346 mov r3, r0
1321 013c 08B1 cbz r0, .L81
1322 .LBB207:
ARM GAS /tmp/ccX7ayIU.s page 44
1323 .LBB208:
1324 .LBB209:
1325 .loc 2 209 0
1326 .syntax unified
1327 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1328 013e 72B6 cpsid i
1329 @ 0 "" 2
1330 .thumb
1331 .syntax unified
1332 .L82:
1333 0140 FEE7 b .L82
1334 .L81:
1335 .LBE209:
1336 .LBE208:
1337 .LBE207:
570:Core/Src/main.c **** {
1338 .loc 1 570 0
1339 0142 4046 mov r0, r8
1340 0144 1022 movs r2, #16
1341 0146 0AA9 add r1, sp, #40
568:Core/Src/main.c **** sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
1342 .loc 1 568 0
1343 0148 8DF82D30 strb r3, [sp, #45]
569:Core/Src/main.c **** if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
1344 .loc 1 569 0
1345 014c 0D93 str r3, [sp, #52]
570:Core/Src/main.c **** {
1346 .loc 1 570 0
1347 014e FFF7FEFF bl HAL_DAC_ConfigChannel
1348 .LVL77:
1349 0152 0546 mov r5, r0
1350 0154 08B1 cbz r0, .L83
1351 .LBB210:
1352 .LBB211:
1353 .LBB212:
1354 .loc 2 209 0
1355 .syntax unified
1356 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1357 0156 72B6 cpsid i
1358 @ 0 "" 2
1359 .thumb
1360 .syntax unified
1361 .L84:
1362 0158 FEE7 b .L84
1363 .L83:
1364 .LBE212:
1365 .LBE211:
1366 .LBE210:
1367 .LBE213:
1368 .LBE221:
1369 .LBB222:
1370 .LBB223:
445:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
1371 .loc 1 445 0
1372 015a 5E4C ldr r4, .L166+12
437:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
1373 .loc 1 437 0
ARM GAS /tmp/ccX7ayIU.s page 45
1374 015c 0790 str r0, [sp, #28]
438:Core/Src/main.c ****
1375 .loc 1 438 0
1376 015e 0146 mov r1, r0
1377 0160 3246 mov r2, r6
1378 0162 0AA8 add r0, sp, #40
437:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
1379 .loc 1 437 0
1380 0164 CDE90855 strd r5, r5, [sp, #32]
451:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
1381 .loc 1 451 0
1382 0168 4FF00408 mov r8, #4
438:Core/Src/main.c ****
1383 .loc 1 438 0
1384 016c FFF7FEFF bl memset
1385 .LVL78:
446:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
1386 .loc 1 446 0
1387 0170 4FF44033 mov r3, #196608
445:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
1388 .loc 1 445 0
1389 0174 4FF0A042 mov r2, #1342177280
465:Core/Src/main.c **** {
1390 .loc 1 465 0
1391 0178 2046 mov r0, r4
446:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
1392 .loc 1 446 0
1393 017a C4E90023 strd r2, r3, [r4]
448:Core/Src/main.c **** hadc1.Init.GainCompensation = 0;
1394 .loc 1 448 0
1395 017e C4E90255 strd r5, r5, [r4, #8]
450:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
1396 .loc 1 450 0
1397 0182 C4E90455 strd r5, r5, [r4, #16]
452:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = ENABLE;
1398 .loc 1 452 0
1399 0186 2577 strb r5, [r4, #28]
453:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
1400 .loc 1 453 0
1401 0188 6777 strb r7, [r4, #29]
454:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
1402 .loc 1 454 0
1403 018a 2762 str r7, [r4, #32]
455:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
1404 .loc 1 455 0
1405 018c 84F82450 strb r5, [r4, #36]
457:Core/Src/main.c **** hadc1.Init.DMAContinuousRequests = ENABLE;
1406 .loc 1 457 0
1407 0190 C4E90B55 strd r5, r5, [r4, #44]
458:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
1408 .loc 1 458 0
1409 0194 84F83870 strb r7, [r4, #56]
459:Core/Src/main.c **** hadc1.Init.OversamplingMode = ENABLE;
1410 .loc 1 459 0
1411 0198 E563 str r5, [r4, #60]
460:Core/Src/main.c **** hadc1.Init.Oversampling.Ratio = ADC_OVERSAMPLING_RATIO_2;
1412 .loc 1 460 0
ARM GAS /tmp/ccX7ayIU.s page 46
1413 019a 84F84070 strb r7, [r4, #64]
462:Core/Src/main.c **** hadc1.Init.Oversampling.TriggeredMode = ADC_TRIGGEREDMODE_SINGLE_TRIGGER;
1414 .loc 1 462 0
1415 019e C4E91155 strd r5, r5, [r4, #68]
463:Core/Src/main.c **** hadc1.Init.Oversampling.OversamplingStopReset = ADC_REGOVERSAMPLING_CONTINUED_MODE;
1416 .loc 1 463 0
1417 01a2 E564 str r5, [r4, #76]
464:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
1418 .loc 1 464 0
1419 01a4 2765 str r7, [r4, #80]
451:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
1420 .loc 1 451 0
1421 01a6 C4F81880 str r8, [r4, #24]
465:Core/Src/main.c **** {
1422 .loc 1 465 0
1423 01aa FFF7FEFF bl HAL_ADC_Init
1424 .LVL79:
1425 01ae 0346 mov r3, r0
1426 01b0 08B1 cbz r0, .L85
1427 .LBB224:
1428 .LBB225:
1429 .LBB226:
1430 .loc 2 209 0
1431 .syntax unified
1432 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1433 01b2 72B6 cpsid i
1434 @ 0 "" 2
1435 .thumb
1436 .syntax unified
1437 .L86:
1438 01b4 FEE7 b .L86
1439 .L85:
1440 .LBE226:
1441 .LBE225:
1442 .LBE224:
472:Core/Src/main.c **** {
1443 .loc 1 472 0
1444 01b6 07A9 add r1, sp, #28
1445 01b8 2046 mov r0, r4
471:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
1446 .loc 1 471 0
1447 01ba 0793 str r3, [sp, #28]
472:Core/Src/main.c **** {
1448 .loc 1 472 0
1449 01bc FFF7FEFF bl HAL_ADCEx_MultiModeConfigChannel
1450 .LVL80:
1451 01c0 0346 mov r3, r0
1452 01c2 08B1 cbz r0, .L87
1453 .LBB227:
1454 .LBB228:
1455 .LBB229:
1456 .loc 2 209 0
1457 .syntax unified
1458 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1459 01c4 72B6 cpsid i
1460 @ 0 "" 2
1461 .thumb
ARM GAS /tmp/ccX7ayIU.s page 47
1462 .syntax unified
1463 .L88:
1464 01c6 FEE7 b .L88
1465 .L87:
1466 .LBE229:
1467 .LBE228:
1468 .LBE227:
478:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
1469 .loc 1 478 0
1470 01c8 4349 ldr r1, .L166+16
483:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
1471 .loc 1 483 0
1472 01ca 0F93 str r3, [sp, #60]
479:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
1473 .loc 1 479 0
1474 01cc 0622 movs r2, #6
481:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
1475 .loc 1 481 0
1476 01ce 7F23 movs r3, #127
478:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
1477 .loc 1 478 0
1478 01d0 0A91 str r1, [sp, #40]
484:Core/Src/main.c **** {
1479 .loc 1 484 0
1480 01d2 2046 mov r0, r4
1481 01d4 0AA9 add r1, sp, #40
480:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
1482 .loc 1 480 0
1483 01d6 CDF83080 str r8, [sp, #48]
482:Core/Src/main.c **** sConfig.Offset = 0;
1484 .loc 1 482 0
1485 01da CDF83880 str r8, [sp, #56]
479:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
1486 .loc 1 479 0
1487 01de 0B92 str r2, [sp, #44]
481:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
1488 .loc 1 481 0
1489 01e0 0D93 str r3, [sp, #52]
484:Core/Src/main.c **** {
1490 .loc 1 484 0
1491 01e2 FFF7FEFF bl HAL_ADC_ConfigChannel
1492 .LVL81:
1493 01e6 08B1 cbz r0, .L89
1494 .LBB230:
1495 .LBB231:
1496 .LBB232:
1497 .loc 2 209 0
1498 .syntax unified
1499 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1500 01e8 72B6 cpsid i
1501 @ 0 "" 2
1502 .thumb
1503 .syntax unified
1504 .L90:
1505 01ea FEE7 b .L90
1506 .L89:
1507 .LBE232:
ARM GAS /tmp/ccX7ayIU.s page 48
1508 .LBE231:
1509 .LBE230:
1510 .LBE223:
1511 .LBE222:
1512 .LBB233:
1513 .LBB234:
669:Core/Src/main.c **** htim7.Init.Prescaler = 1679;
1514 .loc 1 669 0
1515 01ec 3B4C ldr r4, .L166+20
1516 01ee 3C49 ldr r1, .L166+24
664:Core/Src/main.c ****
1517 .loc 1 664 0
1518 01f0 0A90 str r0, [sp, #40]
672:Core/Src/main.c **** htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1519 .loc 1 672 0
1520 01f2 40F2E733 movw r3, #999
670:Core/Src/main.c **** htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
1521 .loc 1 670 0
1522 01f6 40F28F62 movw r2, #1679
664:Core/Src/main.c ****
1523 .loc 1 664 0
1524 01fa CDE90B00 strd r0, r0, [sp, #44]
671:Core/Src/main.c **** htim7.Init.Period = 999;
1525 .loc 1 671 0
1526 01fe A060 str r0, [r4, #8]
673:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
1527 .loc 1 673 0
1528 0200 A061 str r0, [r4, #24]
674:Core/Src/main.c **** {
1529 .loc 1 674 0
1530 0202 2046 mov r0, r4
672:Core/Src/main.c **** htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1531 .loc 1 672 0
1532 0204 E360 str r3, [r4, #12]
669:Core/Src/main.c **** htim7.Init.Prescaler = 1679;
1533 .loc 1 669 0
1534 0206 2160 str r1, [r4]
670:Core/Src/main.c **** htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
1535 .loc 1 670 0
1536 0208 6260 str r2, [r4, #4]
674:Core/Src/main.c **** {
1537 .loc 1 674 0
1538 020a FFF7FEFF bl HAL_TIM_Base_Init
1539 .LVL82:
1540 020e 0346 mov r3, r0
1541 0210 08B1 cbz r0, .L91
1542 .LBB235:
1543 .LBB236:
1544 .LBB237:
1545 .loc 2 209 0
1546 .syntax unified
1547 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1548 0212 72B6 cpsid i
1549 @ 0 "" 2
1550 .thumb
1551 .syntax unified
1552 .L92:
ARM GAS /tmp/ccX7ayIU.s page 49
1553 0214 FEE7 b .L92
1554 .L91:
1555 .LBE237:
1556 .LBE236:
1557 .LBE235:
680:Core/Src/main.c **** {
1558 .loc 1 680 0
1559 0216 2046 mov r0, r4
1560 0218 0AA9 add r1, sp, #40
678:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1561 .loc 1 678 0
1562 021a 0A93 str r3, [sp, #40]
679:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
1563 .loc 1 679 0
1564 021c 0C93 str r3, [sp, #48]
680:Core/Src/main.c **** {
1565 .loc 1 680 0
1566 021e FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1567 .LVL83:
1568 0222 08B1 cbz r0, .L93
1569 .LBB238:
1570 .LBB239:
1571 .LBB240:
1572 .loc 2 209 0
1573 .syntax unified
1574 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1575 0224 72B6 cpsid i
1576 @ 0 "" 2
1577 .thumb
1578 .syntax unified
1579 .L94:
1580 0226 FEE7 b .L94
1581 .L93:
1582 .LBE240:
1583 .LBE239:
1584 .LBE238:
1585 .LBE234:
1586 .LBE233:
1587 .LBB241:
1588 .LBB242:
631:Core/Src/main.c **** htim6.Init.Prescaler = 0;
1589 .loc 1 631 0
1590 0228 2E4C ldr r4, .L166+28
1591 022a 2F4A ldr r2, .L166+32
626:Core/Src/main.c ****
1592 .loc 1 626 0
1593 022c 0A90 str r0, [sp, #40]
634:Core/Src/main.c **** htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1594 .loc 1 634 0
1595 022e 41F6FF53 movw r3, #7679
626:Core/Src/main.c ****
1596 .loc 1 626 0
1597 0232 CDE90B00 strd r0, r0, [sp, #44]
633:Core/Src/main.c **** htim6.Init.Period = 7679;
1598 .loc 1 633 0
1599 0236 C4E90100 strd r0, r0, [r4, #4]
635:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
ARM GAS /tmp/ccX7ayIU.s page 50
1600 .loc 1 635 0
1601 023a A061 str r0, [r4, #24]
636:Core/Src/main.c **** {
1602 .loc 1 636 0
1603 023c 2046 mov r0, r4
634:Core/Src/main.c **** htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1604 .loc 1 634 0
1605 023e E360 str r3, [r4, #12]
631:Core/Src/main.c **** htim6.Init.Prescaler = 0;
1606 .loc 1 631 0
1607 0240 2260 str r2, [r4]
636:Core/Src/main.c **** {
1608 .loc 1 636 0
1609 0242 FFF7FEFF bl HAL_TIM_Base_Init
1610 .LVL84:
1611 0246 0346 mov r3, r0
1612 0248 08B1 cbz r0, .L95
1613 .LBB243:
1614 .LBB244:
1615 .LBB245:
1616 .loc 2 209 0
1617 .syntax unified
1618 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1619 024a 72B6 cpsid i
1620 @ 0 "" 2
1621 .thumb
1622 .syntax unified
1623 .L96:
1624 024c FEE7 b .L96
1625 .L95:
1626 .LBE245:
1627 .LBE244:
1628 .LBE243:
642:Core/Src/main.c **** {
1629 .loc 1 642 0
1630 024e 2046 mov r0, r4
1631 0250 0AA9 add r1, sp, #40
640:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1632 .loc 1 640 0
1633 0252 0A96 str r6, [sp, #40]
641:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
1634 .loc 1 641 0
1635 0254 0C93 str r3, [sp, #48]
642:Core/Src/main.c **** {
1636 .loc 1 642 0
1637 0256 FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1638 .LVL85:
1639 025a 08B1 cbz r0, .L97
1640 .LBB246:
1641 .LBB247:
1642 .LBB248:
1643 .loc 2 209 0
1644 .syntax unified
1645 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1646 025c 72B6 cpsid i
1647 @ 0 "" 2
1648 .thumb
ARM GAS /tmp/ccX7ayIU.s page 51
1649 .syntax unified
1650 .L98:
1651 025e FEE7 b .L98
1652 .L97:
1653 .LBE248:
1654 .LBE247:
1655 .LBE246:
1656 .LBE242:
1657 .LBE241:
1658 .LBB249:
1659 .LBB250:
516:Core/Src/main.c **** if (HAL_CORDIC_Init(&hcordic) != HAL_OK)
1660 .loc 1 516 0
1661 0260 224F ldr r7, .L166+36
1662 0262 234B ldr r3, .L166+40
1663 0264 3B60 str r3, [r7]
504:Core/Src/main.c **** sConfig.Function = CORDIC_FUNCTION_SINE;
1664 .loc 1 504 0
1665 0266 0023 movs r3, #0
1666 0268 CDE90B33 strd r3, r3, [sp, #44]
1667 026c CDE90E33 strd r3, r3, [sp, #56]
517:Core/Src/main.c **** {
1668 .loc 1 517 0
1669 0270 3846 mov r0, r7
511:Core/Src/main.c **** /* USER CODE END CORDIC_Init 0 */
1670 .loc 1 511 0
1671 0272 4FF40013 mov r3, #2097152
505:Core/Src/main.c **** sConfig.Precision = CORDIC_PRECISION_4CYCLES;
1672 .loc 1 505 0
1673 0276 4FF0010B mov fp, #1
506:Core/Src/main.c **** sConfig.Scale = CORDIC_SCALE_0;
1674 .loc 1 506 0
1675 027a 4026 movs r6, #64
505:Core/Src/main.c **** sConfig.Precision = CORDIC_PRECISION_4CYCLES;
1676 .loc 1 505 0
1677 027c CDF828B0 str fp, [sp, #40]
506:Core/Src/main.c **** sConfig.Scale = CORDIC_SCALE_0;
1678 .loc 1 506 0
1679 0280 1096 str r6, [sp, #64]
511:Core/Src/main.c **** /* USER CODE END CORDIC_Init 0 */
1680 .loc 1 511 0
1681 0282 0D93 str r3, [sp, #52]
517:Core/Src/main.c **** {
1682 .loc 1 517 0
1683 0284 FFF7FEFF bl HAL_CORDIC_Init
1684 .LVL86:
1685 0288 0546 mov r5, r0
1686 028a 08B1 cbz r0, .L99
1687 .LBB251:
1688 .LBB252:
1689 .LBB253:
1690 .loc 2 209 0
1691 .syntax unified
1692 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1693 028c 72B6 cpsid i
1694 @ 0 "" 2
1695 .thumb
ARM GAS /tmp/ccX7ayIU.s page 52
1696 .syntax unified
1697 .L100:
1698 028e FEE7 b .L100
1699 .L99:
1700 .LBE253:
1701 .LBE252:
1702 .LBE251:
1703 .LBE250:
1704 .LBE249:
1705 .LBB255:
1706 .LBB256:
752:Core/Src/main.c **** huart1.Init.BaudRate = 115200;
1707 .loc 1 752 0
1708 0290 184C ldr r4, .L166+44
1709 .LBE256:
1710 .LBE255:
1711 .LBB270:
1712 .LBB254:
522:Core/Src/main.c **** /* USER CODE END CORDIC_Init 2 */
1713 .loc 1 522 0
1714 0292 0AA9 add r1, sp, #40
1715 0294 3846 mov r0, r7
1716 0296 FFF7FEFF bl HAL_CORDIC_Configure
1717 .LVL87:
1718 .LBE254:
1719 .LBE270:
1720 .LBB271:
1721 .LBB269:
752:Core/Src/main.c **** huart1.Init.BaudRate = 115200;
1722 .loc 1 752 0
1723 029a 1749 ldr r1, .L166+48
1724 029c 2160 str r1, [r4]
753:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B;
1725 .loc 1 753 0
1726 029e 4FF4E132 mov r2, #115200
757:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
1727 .loc 1 757 0
1728 02a2 0C23 movs r3, #12
763:Core/Src/main.c **** {
1729 .loc 1 763 0
1730 02a4 2046 mov r0, r4
754:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1;
1731 .loc 1 754 0
1732 02a6 A560 str r5, [r4, #8]
756:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX;
1733 .loc 1 756 0
1734 02a8 C4E90355 strd r5, r5, [r4, #12]
759:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
1735 .loc 1 759 0
1736 02ac C4E90655 strd r5, r5, [r4, #24]
761:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
1737 .loc 1 761 0
1738 02b0 C4E90855 strd r5, r5, [r4, #32]
762:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK)
1739 .loc 1 762 0
1740 02b4 A562 str r5, [r4, #40]
753:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B;
ARM GAS /tmp/ccX7ayIU.s page 53
1741 .loc 1 753 0
1742 02b6 6260 str r2, [r4, #4]
757:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
1743 .loc 1 757 0
1744 02b8 6361 str r3, [r4, #20]
763:Core/Src/main.c **** {
1745 .loc 1 763 0
1746 02ba FFF7FEFF bl HAL_UART_Init
1747 .LVL88:
1748 02be 0146 mov r1, r0
1749 02c0 00B3 cbz r0, .L101
1750 .LBB257:
1751 .LBB258:
1752 .LBB259:
1753 .loc 2 209 0
1754 .syntax unified
1755 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1756 02c2 72B6 cpsid i
1757 @ 0 "" 2
1758 .thumb
1759 .syntax unified
1760 .L102:
1761 02c4 FEE7 b .L102
1762 .L167:
1763 02c6 00BF .align 2
1764 .L166:
1765 02c8 00100240 .word 1073876992
1766 02cc 00040048 .word 1207960576
1767 02d0 00080050 .word 1342179328
1768 02d4 00000000 .word hadc1
1769 02d8 002090B6 .word -1232068608
1770 02dc 00000000 .word htim7
1771 02e0 00140040 .word 1073746944
1772 02e4 00000000 .word htim6
1773 02e8 00100040 .word 1073745920
1774 02ec 00000000 .word hcordic
1775 02f0 000C0240 .word 1073875968
1776 02f4 00000000 .word huart1
1777 02f8 00380140 .word 1073821696
1778 02fc 00000000 .word state_changed
1779 0300 00000000 .word hdac1
1780 .L101:
1781 .LBE259:
1782 .LBE258:
1783 .LBE257:
767:Core/Src/main.c **** {
1784 .loc 1 767 0
1785 0304 2046 mov r0, r4
1786 0306 FFF7FEFF bl HAL_UARTEx_SetTxFifoThreshold
1787 .LVL89:
1788 030a 0146 mov r1, r0
1789 030c 08B1 cbz r0, .L103
1790 .LBB260:
1791 .LBB261:
1792 .LBB262:
1793 .loc 2 209 0
1794 .syntax unified
ARM GAS /tmp/ccX7ayIU.s page 54
1795 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1796 030e 72B6 cpsid i
1797 @ 0 "" 2
1798 .thumb
1799 .syntax unified
1800 .L104:
1801 0310 FEE7 b .L104
1802 .L103:
1803 .LBE262:
1804 .LBE261:
1805 .LBE260:
771:Core/Src/main.c **** {
1806 .loc 1 771 0
1807 0312 2046 mov r0, r4
1808 0314 FFF7FEFF bl HAL_UARTEx_SetRxFifoThreshold
1809 .LVL90:
1810 0318 08B1 cbz r0, .L105
1811 .LBB263:
1812 .LBB264:
1813 .LBB265:
1814 .loc 2 209 0
1815 .syntax unified
1816 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1817 031a 72B6 cpsid i
1818 @ 0 "" 2
1819 .thumb
1820 .syntax unified
1821 .L106:
1822 031c FEE7 b .L106
1823 .L105:
1824 .LBE265:
1825 .LBE264:
1826 .LBE263:
775:Core/Src/main.c **** {
1827 .loc 1 775 0
1828 031e 2046 mov r0, r4
1829 0320 FFF7FEFF bl HAL_UARTEx_DisableFifoMode
1830 .LVL91:
1831 0324 08B1 cbz r0, .L107
1832 .LBB266:
1833 .LBB267:
1834 .LBB268:
1835 .loc 2 209 0
1836 .syntax unified
1837 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1838 0326 72B6 cpsid i
1839 @ 0 "" 2
1840 .thumb
1841 .syntax unified
1842 .L108:
1843 0328 FEE7 b .L108
1844 .L107:
1845 .LBE268:
1846 .LBE267:
1847 .LBE266:
1848 .LBE269:
1849 .LBE271:
ARM GAS /tmp/ccX7ayIU.s page 55
1850 .LBB272:
1851 .LBB273:
708:Core/Src/main.c **** htim8.Init.Prescaler = 0;
1852 .loc 1 708 0
1853 032a 814D ldr r5, .L168
1854 032c 814A ldr r2, .L168+4
703:Core/Src/main.c ****
1855 .loc 1 703 0
1856 032e 0990 str r0, [sp, #36]
702:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
1857 .loc 1 702 0
1858 0330 CDE90A00 strd r0, r0, [sp, #40]
1859 0334 CDE90C00 strd r0, r0, [sp, #48]
703:Core/Src/main.c ****
1860 .loc 1 703 0
1861 0338 CDE90700 strd r0, r0, [sp, #28]
710:Core/Src/main.c **** htim8.Init.Period = 239;
1862 .loc 1 710 0
1863 033c C5E90100 strd r0, r0, [r5, #4]
713:Core/Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1864 .loc 1 713 0
1865 0340 C5E90400 strd r0, r0, [r5, #16]
714:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
1866 .loc 1 714 0
1867 0344 A861 str r0, [r5, #24]
711:Core/Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1868 .loc 1 711 0
1869 0346 EF23 movs r3, #239
715:Core/Src/main.c **** {
1870 .loc 1 715 0
1871 0348 2846 mov r0, r5
708:Core/Src/main.c **** htim8.Init.Prescaler = 0;
1872 .loc 1 708 0
1873 034a 2A60 str r2, [r5]
711:Core/Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1874 .loc 1 711 0
1875 034c EB60 str r3, [r5, #12]
715:Core/Src/main.c **** {
1876 .loc 1 715 0
1877 034e FFF7FEFF bl HAL_TIM_Base_Init
1878 .LVL92:
1879 0352 08B1 cbz r0, .L109
1880 .LBB274:
1881 .LBB275:
1882 .LBB276:
1883 .loc 2 209 0
1884 .syntax unified
1885 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1886 0354 72B6 cpsid i
1887 @ 0 "" 2
1888 .thumb
1889 .syntax unified
1890 .L110:
1891 0356 FEE7 b .L110
1892 .L109:
1893 .LBE276:
1894 .LBE275:
ARM GAS /tmp/ccX7ayIU.s page 56
1895 .LBE274:
719:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
1896 .loc 1 719 0
1897 0358 4FF48053 mov r3, #4096
720:Core/Src/main.c **** {
1898 .loc 1 720 0
1899 035c 0AA9 add r1, sp, #40
1900 035e 2846 mov r0, r5
719:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
1901 .loc 1 719 0
1902 0360 0A93 str r3, [sp, #40]
720:Core/Src/main.c **** {
1903 .loc 1 720 0
1904 0362 FFF7FEFF bl HAL_TIM_ConfigClockSource
1905 .LVL93:
1906 0366 0346 mov r3, r0
1907 0368 08B1 cbz r0, .L111
1908 .LBB277:
1909 .LBB278:
1910 .LBB279:
1911 .loc 2 209 0
1912 .syntax unified
1913 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1914 036a 72B6 cpsid i
1915 @ 0 "" 2
1916 .thumb
1917 .syntax unified
1918 .L112:
1919 036c FEE7 b .L112
1920 .L111:
1921 .LBE279:
1922 .LBE278:
1923 .LBE277:
724:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
1924 .loc 1 724 0
1925 036e 2022 movs r2, #32
727:Core/Src/main.c **** {
1926 .loc 1 727 0
1927 0370 07A9 add r1, sp, #28
1928 0372 2846 mov r0, r5
726:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
1929 .loc 1 726 0
1930 0374 CDE90833 strd r3, r3, [sp, #32]
724:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
1931 .loc 1 724 0
1932 0378 0792 str r2, [sp, #28]
727:Core/Src/main.c **** {
1933 .loc 1 727 0
1934 037a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1935 .LVL94:
1936 037e 08B1 cbz r0, .L113
1937 .LBB280:
1938 .LBB281:
1939 .LBB282:
1940 .loc 2 209 0
1941 .syntax unified
1942 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
ARM GAS /tmp/ccX7ayIU.s page 57
1943 0380 72B6 cpsid i
1944 @ 0 "" 2
1945 .thumb
1946 .syntax unified
1947 .L114:
1948 0382 FEE7 b .L114
1949 .L113:
1950 .LBE282:
1951 .LBE281:
1952 .LBE280:
1953 .LBE273:
1954 .LBE272:
1955 .LBB283:
1956 .LBB284:
595:Core/Src/main.c **** hopamp1.Init.PowerMode = OPAMP_POWERMODE_HIGHSPEED;
1957 .loc 1 595 0
1958 0384 6C4D ldr r5, .L168+8
1959 0386 6D4B ldr r3, .L168+12
598:Core/Src/main.c **** hopamp1.Init.InternalOutput = ENABLE;
1960 .loc 1 598 0
1961 0388 2861 str r0, [r5, #16]
596:Core/Src/main.c **** hopamp1.Init.Mode = OPAMP_PGA_MODE;
1962 .loc 1 596 0
1963 038a 8021 movs r1, #128
600:Core/Src/main.c **** hopamp1.Init.PgaConnect = OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS;
1964 .loc 1 600 0
1965 038c A861 str r0, [r5, #24]
603:Core/Src/main.c **** if (HAL_OPAMP_Init(&hopamp1) != HAL_OK)
1966 .loc 1 603 0
1967 038e E862 str r0, [r5, #44]
601:Core/Src/main.c **** hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_64_OR_MINUS_63;
1968 .loc 1 601 0
1969 0390 4FF40032 mov r2, #131072
595:Core/Src/main.c **** hopamp1.Init.PowerMode = OPAMP_POWERMODE_HIGHSPEED;
1970 .loc 1 595 0
1971 0394 2B60 str r3, [r5]
604:Core/Src/main.c **** {
1972 .loc 1 604 0
1973 0396 2846 mov r0, r5
602:Core/Src/main.c **** hopamp1.Init.UserTrimming = OPAMP_TRIMMING_FACTORY;
1974 .loc 1 602 0
1975 0398 4FF4A033 mov r3, #81920
597:Core/Src/main.c **** hopamp1.Init.NonInvertingInput = OPAMP_NONINVERTINGINPUT_IO0;
1976 .loc 1 597 0
1977 039c AE60 str r6, [r5, #8]
599:Core/Src/main.c **** hopamp1.Init.TimerControlledMuxmode = OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE;
1978 .loc 1 599 0
1979 039e 85F814B0 strb fp, [r5, #20]
596:Core/Src/main.c **** hopamp1.Init.Mode = OPAMP_PGA_MODE;
1980 .loc 1 596 0
1981 03a2 6960 str r1, [r5, #4]
602:Core/Src/main.c **** hopamp1.Init.UserTrimming = OPAMP_TRIMMING_FACTORY;
1982 .loc 1 602 0
1983 03a4 C5E90923 strd r2, r3, [r5, #36]
604:Core/Src/main.c **** {
1984 .loc 1 604 0
1985 03a8 FFF7FEFF bl HAL_OPAMP_Init
ARM GAS /tmp/ccX7ayIU.s page 58
1986 .LVL95:
1987 03ac 08B1 cbz r0, .L115
1988 .LBB285:
1989 .LBB286:
1990 .LBB287:
1991 .loc 2 209 0
1992 .syntax unified
1993 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1994 03ae 72B6 cpsid i
1995 @ 0 "" 2
1996 .thumb
1997 .syntax unified
1998 .L116:
1999 03b0 FEE7 b .L116
2000 .L115:
2001 .LBE287:
2002 .LBE286:
2003 .LBE285:
2004 .LBE284:
2005 .LBE283:
308:Core/Src/main.c **** audio_filter_init();
2006 .loc 1 308 0
2007 03b2 FFF7FEFF bl st2_filter_init
2008 .LVL96:
309:Core/Src/main.c **** // diag();
2009 .loc 1 309 0
2010 03b6 FFF7FEFF bl audio_filter_init
2011 .LVL97:
311:Core/Src/main.c **** HAL_TIM_Base_Start_IT(&htim7);
2012 .loc 1 311 0
2013 03ba 2846 mov r0, r5
2014 03bc FFF7FEFF bl HAL_OPAMP_Start
2015 .LVL98:
312:Core/Src/main.c **** HAL_UART_Receive_IT(&huart1, uart_rx_buf, 1);
2016 .loc 1 312 0
2017 03c0 5F48 ldr r0, .L168+16
2018 03c2 DFF8DC91 ldr r9, .L168+112
2019 03c6 DFF8DC81 ldr r8, .L168+116
2020 03ca 5E4F ldr r7, .L168+20
2021 03cc 5E4E ldr r6, .L168+24
2022 03ce 5F4D ldr r5, .L168+28
2023 03d0 FFF7FEFF bl HAL_TIM_Base_Start_IT
2024 .LVL99:
313:Core/Src/main.c **** // HAL_UART_Receive_IT(&huart2, uart_rx_buf, 1);
2025 .loc 1 313 0
2026 03d4 5A46 mov r2, fp
2027 03d6 2046 mov r0, r4
2028 03d8 5D49 ldr r1, .L168+32
336:Core/Src/main.c **** half_rx_dac_buffer_empty = 0;
2029 .loc 1 336 0
2030 03da 5E4C ldr r4, .L168+36
334:Core/Src/main.c **** else if (modulation == MOD_AM) am_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer);
2031 .loc 1 334 0
2032 03dc DFF8C8B1 ldr fp, .L168+120
313:Core/Src/main.c **** // HAL_UART_Receive_IT(&huart2, uart_rx_buf, 1);
2033 .loc 1 313 0
2034 03e0 FFF7FEFF bl HAL_UART_Receive_IT
ARM GAS /tmp/ccX7ayIU.s page 59
2035 .LVL100:
316:Core/Src/main.c **** /* USER CODE END 2 */
2036 .loc 1 316 0
2037 03e4 FFF7FEFF bl start_receive
2038 .LVL101:
2039 .L130:
325:Core/Src/main.c **** if(rx_adc_buffer_ready){
2040 .loc 1 325 0
2041 03e8 99F80030 ldrb r3, [r9] @ zero_extendqisi2
2042 03ec 002B cmp r3, #0
2043 03ee 34D0 beq .L118
326:Core/Src/main.c **** HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, SET);
2044 .loc 1 326 0
2045 03f0 98F80030 ldrb r3, [r8] @ zero_extendqisi2
2046 03f4 ABB1 cbz r3, .L119
327:Core/Src/main.c **** rx_mixer(adc_buffer, ADC_BUFFER_SIZE, if_I, if_Q, nco1_increment);
2047 .loc 1 327 0
2048 03f6 0122 movs r2, #1
2049 03f8 2021 movs r1, #32
2050 03fa 5748 ldr r0, .L168+40
2051 03fc FFF7FEFF bl HAL_GPIO_WritePin
2052 .LVL102:
328:Core/Src/main.c **** HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, RESET);
2053 .loc 1 328 0
2054 0400 3B68 ldr r3, [r7]
2055 0402 0093 str r3, [sp]
2056 0404 554A ldr r2, .L168+44
2057 0406 564B ldr r3, .L168+48
2058 0408 5648 ldr r0, .L168+52
2059 040a 4FF48061 mov r1, #1024
2060 040e FFF7FEFF bl rx_mixer
2061 .LVL103:
329:Core/Src/main.c **** rx_adc_buffer_ready = 0;
2062 .loc 1 329 0
2063 0412 0022 movs r2, #0
2064 0414 2021 movs r1, #32
2065 0416 5048 ldr r0, .L168+40
2066 0418 FFF7FEFF bl HAL_GPIO_WritePin
2067 .LVL104:
330:Core/Src/main.c **** }
2068 .loc 1 330 0
2069 041c 0023 movs r3, #0
2070 041e 88F80030 strb r3, [r8]
2071 .L119:
332:Core/Src/main.c **** if (modulation == MOD_DC) dc_demodulator(if_I, LF_BUFFER_SIZE, prefilter_lf_buffer);
2072 .loc 1 332 0
2073 0422 3378 ldrb r3, [r6] @ zero_extendqisi2
2074 0424 CBB1 cbz r3, .L118
333:Core/Src/main.c **** else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_demodulator(if_I, if_Q, LF_BUFFER_SI
2075 .loc 1 333 0
2076 0426 2B68 ldr r3, [r5]
2077 0428 002B cmp r3, #0
2078 042a 72D0 beq .L161
334:Core/Src/main.c **** else if (modulation == MOD_AM) am_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer);
2079 .loc 1 334 0
2080 042c 5A1E subs r2, r3, #1
2081 042e 012A cmp r2, #1
ARM GAS /tmp/ccX7ayIU.s page 60
2082 0430 75D9 bls .L162
335:Core/Src/main.c **** arm_fir_q31(&audio_filter_struct, prefilter_lf_buffer, lf_buffer[lf_buffer_toggle], AUDIO_FILTER
2083 .loc 1 335 0
2084 0432 032B cmp r3, #3
2085 0434 05D1 bne .L122
335:Core/Src/main.c **** arm_fir_q31(&audio_filter_struct, prefilter_lf_buffer, lf_buffer[lf_buffer_toggle], AUDIO_FILTER
2086 .loc 1 335 0 is_stmt 0 discriminator 1
2087 0436 2346 mov r3, r4
2088 0438 4022 movs r2, #64
2089 043a 4949 ldr r1, .L168+48
2090 043c 4748 ldr r0, .L168+44
2091 043e FFF7FEFF bl am_demodulator
2092 .LVL105:
2093 .L122:
336:Core/Src/main.c **** half_rx_dac_buffer_empty = 0;
2094 .loc 1 336 0 is_stmt 1
2095 0442 494B ldr r3, .L168+56
2096 0444 4949 ldr r1, .L168+60
2097 0446 1A78 ldrb r2, [r3] @ zero_extendqisi2
2098 0448 4948 ldr r0, .L168+64
2099 044a 4023 movs r3, #64
2100 044c 01EB0222 add r2, r1, r2, lsl #8
2101 0450 2146 mov r1, r4
2102 0452 FFF7FEFF bl arm_fir_q31
2103 .LVL106:
337:Core/Src/main.c **** }
2104 .loc 1 337 0
2105 0456 0023 movs r3, #0
2106 0458 3370 strb r3, [r6]
2107 .L118:
340:Core/Src/main.c **** if(half_tx_dac_buffer_empty){
2108 .loc 1 340 0
2109 045a 464B ldr r3, .L168+68
2110 045c 1B78 ldrb r3, [r3] @ zero_extendqisi2
2111 045e 13B3 cbz r3, .L125
341:Core/Src/main.c **** // HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, SET);
2112 .loc 1 341 0
2113 0460 454B ldr r3, .L168+72
2114 0462 1B78 ldrb r3, [r3] @ zero_extendqisi2
2115 0464 7BB1 cbz r3, .L126
2116 .LBB288:
343:Core/Src/main.c **** half_tx_dac_buffer_empty = 0;
2117 .loc 1 343 0
2118 0466 454B ldr r3, .L168+76
2119 0468 3C4A ldr r2, .L168+44
2120 046a 1878 ldrb r0, [r3] @ zero_extendqisi2
2121 046c 3B68 ldr r3, [r7]
2122 046e 0093 str r3, [sp]
2123 0470 434B ldr r3, .L168+80
2124 0472 4FF48061 mov r1, #1024
2125 0476 03EB0030 add r0, r3, r0, lsl #12
2126 047a 394B ldr r3, .L168+48
2127 047c FFF7FEFF bl tx_mixer
2128 .LVL107:
344:Core/Src/main.c **** // HAL_GPIO_WritePin(OUT_GPIO_Port, OUT_Pin, RESET);
2129 .loc 1 344 0
2130 0480 3D4A ldr r2, .L168+72
ARM GAS /tmp/ccX7ayIU.s page 61
2131 0482 0023 movs r3, #0
2132 0484 1370 strb r3, [r2]
2133 .L126:
2134 .LBE288:
347:Core/Src/main.c **** if (modulation == MOD_DC) dc_modulator(if_I, LF_BUFFER_SIZE, prefilter_lf_buffer);
2135 .loc 1 347 0
2136 0486 3F4B ldr r3, .L168+84
2137 0488 1B78 ldrb r3, [r3] @ zero_extendqisi2
2138 048a 63B1 cbz r3, .L125
348:Core/Src/main.c **** else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_modulator(if_I,
2139 .loc 1 348 0
2140 048c 2B68 ldr r3, [r5]
2141 048e 3BB3 cbz r3, .L163
349:Core/Src/main.c **** else if (modulation == MOD_AM) am_modulator(if_I, if_Q, LF_BUFFER_SIZE, pre
2142 .loc 1 349 0
2143 0490 5A1E subs r2, r3, #1
2144 0492 012A cmp r2, #1
2145 0494 1BD9 bls .L164
350:Core/Src/main.c **** }
2146 .loc 1 350 0
2147 0496 032B cmp r3, #3
2148 0498 05D1 bne .L125
350:Core/Src/main.c **** }
2149 .loc 1 350 0 is_stmt 0 discriminator 1
2150 049a 2346 mov r3, r4
2151 049c 4022 movs r2, #64
2152 049e 3049 ldr r1, .L168+48
2153 04a0 2E48 ldr r0, .L168+44
2154 04a2 FFF7FEFF bl am_modulator
2155 .LVL108:
2156 .L125:
353:Core/Src/main.c **** if(receive){
2157 .loc 1 353 0 is_stmt 1
2158 04a6 384B ldr r3, .L168+88
2159 04a8 1B78 ldrb r3, [r3] @ zero_extendqisi2
2160 04aa 002B cmp r3, #0
2161 04ac 9CD0 beq .L130
354:Core/Src/main.c **** // TODO
2162 .loc 1 354 0
2163 04ae 99F80030 ldrb r3, [r9] @ zero_extendqisi2
2164 04b2 1BB1 cbz r3, .L132
356:Core/Src/main.c **** }
2165 .loc 1 356 0
2166 04b4 4021 movs r1, #64
2167 04b6 2948 ldr r0, .L168+44
2168 04b8 FFF7FEFF bl rx_measure_signal
2169 .LVL109:
2170 .L132:
359:Core/Src/main.c **** if(state_changed) display_update_state();
2171 .loc 1 359 0 discriminator 1
2172 04bc 334B ldr r3, .L168+92
2173 04be 1A78 ldrb r2, [r3] @ zero_extendqisi2
2174 04c0 334B ldr r3, .L168+96
2175 04c2 1B78 ldrb r3, [r3] @ zero_extendqisi2
2176 04c4 9A42 cmp r2, r3
2177 04c6 11D0 beq .L165
2178 .LBB289:
ARM GAS /tmp/ccX7ayIU.s page 62
359:Core/Src/main.c **** if(state_changed) display_update_state();
2179 .loc 1 359 0 is_stmt 0 discriminator 2
2180 04c8 FFF7FEFF bl dequeue_cmd
2181 .LVL110:
2182 04cc F6E7 b .L132
2183 .L164:
2184 .LBE289:
349:Core/Src/main.c **** else if (modulation == MOD_AM) am_modulator(if_I, if_Q, LF_BUFFER_SIZE, pre
2185 .loc 1 349 0 is_stmt 1 discriminator 1
2186 04ce CDF800B0 str fp, [sp]
2187 04d2 2346 mov r3, r4
2188 04d4 4022 movs r2, #64
2189 04d6 2249 ldr r1, .L168+48
2190 04d8 2048 ldr r0, .L168+44
2191 04da FFF7FEFF bl ssb_modulator
2192 .LVL111:
2193 04de E2E7 b .L125
2194 .L163:
348:Core/Src/main.c **** else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_modulator(if_I,
2195 .loc 1 348 0 discriminator 1
2196 04e0 2246 mov r2, r4
2197 04e2 4021 movs r1, #64
2198 04e4 1D48 ldr r0, .L168+44
2199 04e6 FFF7FEFF bl dc_modulator
2200 .LVL112:
2201 04ea DCE7 b .L125
2202 .L165:
360:Core/Src/main.c **** if(uart_tx_buf_in_idx){
2203 .loc 1 360 0
2204 04ec BAF80030 ldrh r3, [r10]
2205 04f0 0BB1 cbz r3, .L134
360:Core/Src/main.c **** if(uart_tx_buf_in_idx){
2206 .loc 1 360 0 is_stmt 0 discriminator 1
2207 04f2 FFF7FEFF bl display_update_state
2208 .LVL113:
2209 .L134:
361:Core/Src/main.c **** display_write(uart_tx_buf, uart_tx_buf_in_idx);
2210 .loc 1 361 0 is_stmt 1
2211 04f6 274B ldr r3, .L168+100
2212 04f8 1A88 ldrh r2, [r3]
2213 04fa 32B1 cbz r2, .L135
2214 .LVL114:
2215 .LBB290:
2216 .LBB291:
184:Core/Src/main.c **** // HAL_UART_Transmit_DMA(&huart2, ptr, len);
2217 .loc 1 184 0
2218 04fc 2649 ldr r1, .L168+104
2219 04fe 2748 ldr r0, .L168+108
2220 0500 FFF7FEFF bl HAL_UART_Transmit_DMA
2221 .LVL115:
2222 .LBE291:
2223 .LBE290:
363:Core/Src/main.c **** }
2224 .loc 1 363 0
2225 0504 234A ldr r2, .L168+100
2226 0506 0023 movs r3, #0
2227 0508 1380 strh r3, [r2] @ movhi
ARM GAS /tmp/ccX7ayIU.s page 63
2228 .L135:
366:Core/Src/main.c **** }
2229 .loc 1 366 0
2230 050a 1F4A ldr r2, .L168+88
2231 050c 0023 movs r3, #0
2232 050e 1370 strb r3, [r2]
2233 0510 6AE7 b .L130
2234 .L161:
333:Core/Src/main.c **** else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_demodulator(if_I, if_Q, LF_BUFFER_SI
2235 .loc 1 333 0 discriminator 1
2236 0512 2246 mov r2, r4
2237 0514 4021 movs r1, #64
2238 0516 1148 ldr r0, .L168+44
2239 0518 FFF7FEFF bl dc_demodulator
2240 .LVL116:
2241 051c 91E7 b .L122
2242 .L162:
334:Core/Src/main.c **** else if (modulation == MOD_AM) am_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer);
2243 .loc 1 334 0 discriminator 1
2244 051e CDF800B0 str fp, [sp]
2245 0522 2346 mov r3, r4
2246 0524 4022 movs r2, #64
2247 0526 0E49 ldr r1, .L168+48
2248 0528 0C48 ldr r0, .L168+44
2249 052a FFF7FEFF bl ssb_demodulator
2250 .LVL117:
2251 052e 88E7 b .L122
2252 .L169:
2253 .align 2
2254 .L168:
2255 0530 00000000 .word htim8
2256 0534 00340140 .word 1073820672
2257 0538 00000000 .word hopamp1
2258 053c 00030140 .word 1073808128
2259 0540 00000000 .word htim7
2260 0544 00000000 .word nco1_increment
2261 0548 00000000 .word half_rx_dac_buffer_empty
2262 054c 00000000 .word modulation
2263 0550 00000000 .word uart_rx_buf
2264 0554 00000000 .word prefilter_lf_buffer
2265 0558 00040048 .word 1207960576
2266 055c 00000000 .word if_I
2267 0560 00000000 .word if_Q
2268 0564 00000000 .word adc_buffer
2269 0568 00000000 .word lf_buffer_toggle
2270 056c 00000000 .word lf_buffer
2271 0570 00000000 .word audio_filter_struct
2272 0574 00000000 .word transmit
2273 0578 00000000 .word half_tx_dac_buffer_empty
2274 057c 00000000 .word tx_dac_buffer_toggle
2275 0580 00000000 .word tx_dac_buffer
2276 0584 00000000 .word tx_adc_buffer_ready
2277 0588 00000000 .word tick
2278 058c 00000000 .word rx_cmd_rb_in_idx
2279 0590 00000000 .word rx_cmd_rb_out_idx
2280 0594 00000000 .word uart_tx_buf_in_idx
2281 0598 00000000 .word uart_tx_buf
ARM GAS /tmp/ccX7ayIU.s page 64
2282 059c 00000000 .word huart1
2283 05a0 00000000 .word receive
2284 05a4 00000000 .word rx_adc_buffer_ready
2285 05a8 47E17A14 .word 343597383
2286 .cfi_endproc
2287 .LFE391:
2289 .section .text.Error_Handler,"ax",%progbits
2290 .align 1
2291 .p2align 2,,3
2292 .global Error_Handler
2293 .syntax unified
2294 .thumb
2295 .thumb_func
2296 .fpu fpv4-sp-d16
2298 Error_Handler:
2299 .LFB403:
834:Core/Src/main.c ****
835:Core/Src/main.c **** }
836:Core/Src/main.c ****
837:Core/Src/main.c **** /* USER CODE BEGIN 4 */
838:Core/Src/main.c ****
839:Core/Src/main.c **** /* USER CODE END 4 */
840:Core/Src/main.c ****
841:Core/Src/main.c **** /**
842:Core/Src/main.c **** * @brief This function is executed in case of error occurrence.
843:Core/Src/main.c **** * @retval None
844:Core/Src/main.c **** */
845:Core/Src/main.c **** void Error_Handler(void)
846:Core/Src/main.c **** {
2300 .loc 1 846 0
2301 .cfi_startproc
2302 @ Volatile: function does not return.
2303 @ args = 0, pretend = 0, frame = 0
2304 @ frame_needed = 0, uses_anonymous_args = 0
2305 @ link register save eliminated.
2306 .LBB292:
2307 .LBB293:
2308 .loc 2 209 0
2309 .syntax unified
2310 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
2311 0000 72B6 cpsid i
2312 @ 0 "" 2
2313 .thumb
2314 .syntax unified
2315 .L171:
2316 0002 FEE7 b .L171
2317 .LBE293:
2318 .LBE292:
2319 .cfi_endproc
2320 .LFE403:
2322 .comm half_rx_dac_buffer_empty,1,1
2323 .comm rx_adc_buffer_ready,1,1
2324 .comm tick,1,1
2325 .comm hdma_usart1_tx,96,4
2326 .comm huart1,144,4
2327 .comm htim8,76,4
2328 .comm htim7,76,4
ARM GAS /tmp/ccX7ayIU.s page 65
2329 .comm htim6,76,4
2330 .comm hopamp1,60,4
2331 .comm hdma_dac1_ch2,96,4
2332 .comm hdma_dac1_ch1,96,4
2333 .comm hdac1,20,4
2334 .comm hcordic,40,4
2335 .comm hdma_adc1,96,4
2336 .comm hadc1,108,4
2337 .text
2338 .Letext0:
2339 .file 3 "/usr/include/newlib/machine/_default_types.h"
2340 .file 4 "/usr/include/newlib/sys/_stdint.h"
2341 .file 5 "Drivers/CMSIS/Include/core_cm4.h"
2342 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
2343 .file 7 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
2344 .file 8 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
2345 .file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
2346 .file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
2347 .file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"
2348 .file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
2349 .file 13 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
2350 .file 14 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h"
2351 .file 15 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h"
2352 .file 16 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h"
2353 .file 17 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h"
2354 .file 18 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
2355 .file 19 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h"
2356 .file 20 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
2357 .file 21 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
2358 .file 22 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
2359 .file 23 "/usr/include/newlib/sys/lock.h"
2360 .file 24 "/usr/include/newlib/sys/_types.h"
2361 .file 25 "/usr/lib/gcc/arm-none-eabi/7.3.1/include/stddef.h"
2362 .file 26 "/usr/include/newlib/sys/reent.h"
2363 .file 27 "/usr/include/newlib/math.h"
2364 .file 28 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h"
2365 .file 29 "Core/Inc/rx.h"
2366 .file 30 "Core/Inc/tx.h"
2367 .file 31 "Core/Inc/bassofono.h"
2368 .file 32 "Core/Inc/interface.h"
2369 .file 33 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
2370 .file 34 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
2371 .file 35 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
2372 .file 36 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h"
2373 .file 37 "<built-in>"
ARM GAS /tmp/ccX7ayIU.s page 66
DEFINED SYMBOLS
*ABS*:0000000000000000 main.c
/tmp/ccX7ayIU.s:16 .text.HAL_ADC_ConvCpltCallback:0000000000000000 $t
/tmp/ccX7ayIU.s:24 .text.HAL_ADC_ConvCpltCallback:0000000000000000 HAL_ADC_ConvCpltCallback
/tmp/ccX7ayIU.s:47 .text.HAL_ADC_ConvCpltCallback:0000000000000010 $d
*COM*:0000000000000001 rx_adc_buffer_ready
/tmp/ccX7ayIU.s:52 .text.HAL_DAC_ConvHalfCpltCallbackCh1:0000000000000000 $t
/tmp/ccX7ayIU.s:60 .text.HAL_DAC_ConvHalfCpltCallbackCh1:0000000000000000 HAL_DAC_ConvHalfCpltCallbackCh1
/tmp/ccX7ayIU.s:86 .text.HAL_DAC_ConvHalfCpltCallbackCh1:0000000000000010 $d
*COM*:0000000000000001 half_rx_dac_buffer_empty
/tmp/ccX7ayIU.s:92 .text.HAL_DAC_ConvCpltCallbackCh1:0000000000000000 $t
/tmp/ccX7ayIU.s:100 .text.HAL_DAC_ConvCpltCallbackCh1:0000000000000000 HAL_DAC_ConvCpltCallbackCh1
/tmp/ccX7ayIU.s:122 .text.HAL_DAC_ConvCpltCallbackCh1:000000000000000c $d
/tmp/ccX7ayIU.s:128 .text.HAL_DACEx_ConvHalfCpltCallbackCh2:0000000000000000 $t
/tmp/ccX7ayIU.s:136 .text.HAL_DACEx_ConvHalfCpltCallbackCh2:0000000000000000 HAL_DACEx_ConvHalfCpltCallbackCh2
/tmp/ccX7ayIU.s:171 .text.HAL_DACEx_ConvHalfCpltCallbackCh2:0000000000000018 $d
/tmp/ccX7ayIU.s:178 .text.HAL_DACEx_ConvCpltCallbackCh2:0000000000000000 $t
/tmp/ccX7ayIU.s:186 .text.HAL_DACEx_ConvCpltCallbackCh2:0000000000000000 HAL_DACEx_ConvCpltCallbackCh2
/tmp/ccX7ayIU.s:218 .text.HAL_DACEx_ConvCpltCallbackCh2:0000000000000018 $d
/tmp/ccX7ayIU.s:225 .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 $t
/tmp/ccX7ayIU.s:233 .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 HAL_TIM_PeriodElapsedCallback
/tmp/ccX7ayIU.s:256 .text.HAL_TIM_PeriodElapsedCallback:0000000000000010 $d
*COM*:0000000000000001 tick
/tmp/ccX7ayIU.s:262 .text.HAL_UART_RxCpltCallback:0000000000000000 $t
/tmp/ccX7ayIU.s:270 .text.HAL_UART_RxCpltCallback:0000000000000000 HAL_UART_RxCpltCallback
/tmp/ccX7ayIU.s:320 .text.HAL_UART_RxCpltCallback:0000000000000024 $d
*COM*:0000000000000090 huart1
/tmp/ccX7ayIU.s:327 .text.__io_putchar:0000000000000000 $t
/tmp/ccX7ayIU.s:335 .text.__io_putchar:0000000000000000 __io_putchar
/tmp/ccX7ayIU.s:374 .text.__io_putchar:000000000000001c $d
/tmp/ccX7ayIU.s:379 .text._write:0000000000000000 $t
/tmp/ccX7ayIU.s:387 .text._write:0000000000000000 _write
/tmp/ccX7ayIU.s:416 .text._write:0000000000000010 $d
/tmp/ccX7ayIU.s:421 .text.display_write:0000000000000000 $t
/tmp/ccX7ayIU.s:429 .text.display_write:0000000000000000 display_write
/tmp/ccX7ayIU.s:459 .text.display_write:0000000000000014 $d
/tmp/ccX7ayIU.s:464 .text.start_transmit:0000000000000000 $t
/tmp/ccX7ayIU.s:472 .text.start_transmit:0000000000000000 start_transmit
/tmp/ccX7ayIU.s:522 .text.start_transmit:0000000000000030 $d
*COM*:0000000000000014 hdac1
*COM*:000000000000004c htim8
/tmp/ccX7ayIU.s:530 .text.stop_transmit:0000000000000000 $t
/tmp/ccX7ayIU.s:538 .text.stop_transmit:0000000000000000 stop_transmit
/tmp/ccX7ayIU.s:581 .text.stop_transmit:0000000000000024 $d
/tmp/ccX7ayIU.s:588 .text.start_receive:0000000000000000 $t
/tmp/ccX7ayIU.s:596 .text.start_receive:0000000000000000 start_receive
/tmp/ccX7ayIU.s:654 .text.start_receive:0000000000000038 $d
*COM*:000000000000006c hadc1
*COM*:000000000000004c htim6
/tmp/ccX7ayIU.s:664 .text.stop_receive:0000000000000000 $t
/tmp/ccX7ayIU.s:672 .text.stop_receive:0000000000000000 stop_receive
/tmp/ccX7ayIU.s:723 .text.stop_receive:000000000000002c $d
/tmp/ccX7ayIU.s:731 .text.set_gain:0000000000000000 $t
/tmp/ccX7ayIU.s:739 .text.set_gain:0000000000000000 set_gain
/tmp/ccX7ayIU.s:762 .text.set_gain:0000000000000016 $d
/tmp/ccX7ayIU.s:881 .text.set_gain:0000000000000088 $d
*COM*:000000000000003c hopamp1
ARM GAS /tmp/ccX7ayIU.s page 67
/tmp/ccX7ayIU.s:887 .text.SystemClock_Config:0000000000000000 $t
/tmp/ccX7ayIU.s:895 .text.SystemClock_Config:0000000000000000 SystemClock_Config
/tmp/ccX7ayIU.s:1055 .text.startup.main:0000000000000000 $t
/tmp/ccX7ayIU.s:1063 .text.startup.main:0000000000000000 main
/tmp/ccX7ayIU.s:1765 .text.startup.main:00000000000002c8 $d
*COM*:000000000000004c htim7
*COM*:0000000000000028 hcordic
/tmp/ccX7ayIU.s:1785 .text.startup.main:0000000000000304 $t
/tmp/ccX7ayIU.s:2255 .text.startup.main:0000000000000530 $d
/tmp/ccX7ayIU.s:2290 .text.Error_Handler:0000000000000000 $t
/tmp/ccX7ayIU.s:2298 .text.Error_Handler:0000000000000000 Error_Handler
*COM*:0000000000000060 hdma_usart1_tx
*COM*:0000000000000060 hdma_dac1_ch2
*COM*:0000000000000060 hdma_dac1_ch1
*COM*:0000000000000060 hdma_adc1
/tmp/ccX7ayIU.s:767 .text.set_gain:000000000000001b $d
/tmp/ccX7ayIU.s:767 .text.set_gain:000000000000001c $t
UNDEFINED SYMBOLS
lf_buffer_toggle
HAL_GPIO_TogglePin
tx_dac_buffer_toggle
half_tx_dac_buffer_empty
enqueue_cmd
HAL_UART_Receive_IT
uart_rx_buf
HAL_UART_Transmit
HAL_UART_Transmit_DMA
HAL_TIM_Base_Start
HAL_DAC_Start
HAL_DAC_Start_DMA
transmit
tx_dac_buffer
HAL_TIM_Base_Stop
HAL_DAC_Stop
HAL_DAC_Stop_DMA
HAL_ADC_Start_DMA
receive
adc_buffer
lf_buffer
HAL_ADC_Stop_DMA
HAL_OPAMP_Stop
HAL_OPAMP_Start
gain
memset
HAL_PWREx_ControlVoltageScaling
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
HAL_RCCEx_PeriphCLKConfig
display_init
state_set_default
interface_set_default
display_update_mode
display_update_state
HAL_Init
HAL_GPIO_WritePin
HAL_GPIO_Init
ARM GAS /tmp/ccX7ayIU.s page 68
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
HAL_DAC_Init
HAL_DAC_ConfigChannel
HAL_ADC_Init
HAL_ADCEx_MultiModeConfigChannel
HAL_ADC_ConfigChannel
HAL_TIM_Base_Init
HAL_TIMEx_MasterConfigSynchronization
HAL_CORDIC_Init
HAL_CORDIC_Configure
HAL_UART_Init
state_changed
HAL_UARTEx_SetTxFifoThreshold
HAL_UARTEx_SetRxFifoThreshold
HAL_UARTEx_DisableFifoMode
HAL_TIM_ConfigClockSource
HAL_OPAMP_Init
st2_filter_init
audio_filter_init
HAL_TIM_Base_Start_IT
rx_mixer
am_demodulator
arm_fir_q31
tx_mixer
am_modulator
rx_measure_signal
dequeue_cmd
ssb_modulator
dc_modulator
dc_demodulator
ssb_demodulator
nco1_increment
modulation
prefilter_lf_buffer
if_I
if_Q
audio_filter_struct
tx_adc_buffer_ready
rx_cmd_rb_in_idx
rx_cmd_rb_out_idx
uart_tx_buf_in_idx
uart_tx_buf
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