ARM GAS  /tmp/cc1m4PcV.s 			page 1


   1              		.cpu cortex-m4
   2              		.eabi_attribute 27, 1
   3              		.eabi_attribute 28, 1
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 1
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"system_stm32g4xx.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.section	.text.SystemInit,"ax",%progbits
  18              		.align	1
  19              		.global	SystemInit
  20              		.syntax unified
  21              		.thumb
  22              		.thumb_func
  23              		.fpu fpv4-sp-d16
  25              	SystemInit:
  26              	.LFB132:
  27              		.file 1 "Core/Src/system_stm32g4xx.c"
   1:Core/Src/system_stm32g4xx.c **** /**
   2:Core/Src/system_stm32g4xx.c ****   ******************************************************************************
   3:Core/Src/system_stm32g4xx.c ****   * @file    system_stm32g4xx.c
   4:Core/Src/system_stm32g4xx.c ****   * @author  MCD Application Team
   5:Core/Src/system_stm32g4xx.c ****   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
   6:Core/Src/system_stm32g4xx.c ****   *
   7:Core/Src/system_stm32g4xx.c ****   *   This file provides two functions and one global variable to be called from
   8:Core/Src/system_stm32g4xx.c ****   *   user application:
   9:Core/Src/system_stm32g4xx.c ****   *      - SystemInit(): This function is called at startup just after reset and
  10:Core/Src/system_stm32g4xx.c ****   *                      before branch to main program. This call is made inside
  11:Core/Src/system_stm32g4xx.c ****   *                      the "startup_stm32g4xx.s" file.
  12:Core/Src/system_stm32g4xx.c ****   *
  13:Core/Src/system_stm32g4xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14:Core/Src/system_stm32g4xx.c ****   *                                  by the user application to setup the SysTick
  15:Core/Src/system_stm32g4xx.c ****   *                                  timer or configure other parameters.
  16:Core/Src/system_stm32g4xx.c ****   *
  17:Core/Src/system_stm32g4xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Core/Src/system_stm32g4xx.c ****   *                                 be called whenever the core clock is changed
  19:Core/Src/system_stm32g4xx.c ****   *                                 during program execution.
  20:Core/Src/system_stm32g4xx.c ****   *
  21:Core/Src/system_stm32g4xx.c ****   *   After each device reset the HSI (16 MHz) is used as system clock source.
  22:Core/Src/system_stm32g4xx.c ****   *   Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
  23:Core/Src/system_stm32g4xx.c ****   *   configure the system clock before to branch to main program.
  24:Core/Src/system_stm32g4xx.c ****   *
  25:Core/Src/system_stm32g4xx.c ****   *   This file configures the system clock as follows:
  26:Core/Src/system_stm32g4xx.c ****   *=============================================================================
  27:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  28:Core/Src/system_stm32g4xx.c ****   *        System Clock source                    | HSI
  29:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  30:Core/Src/system_stm32g4xx.c ****   *        SYSCLK(Hz)                             | 16000000
  31:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
ARM GAS  /tmp/cc1m4PcV.s 			page 2


  32:Core/Src/system_stm32g4xx.c ****   *        HCLK(Hz)                               | 16000000
  33:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  34:Core/Src/system_stm32g4xx.c ****   *        AHB Prescaler                          | 1
  35:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  36:Core/Src/system_stm32g4xx.c ****   *        APB1 Prescaler                         | 1
  37:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  38:Core/Src/system_stm32g4xx.c ****   *        APB2 Prescaler                         | 1
  39:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  40:Core/Src/system_stm32g4xx.c ****   *        PLL_M                                  | 1
  41:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  42:Core/Src/system_stm32g4xx.c ****   *        PLL_N                                  | 16
  43:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  44:Core/Src/system_stm32g4xx.c ****   *        PLL_P                                  | 7
  45:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  46:Core/Src/system_stm32g4xx.c ****   *        PLL_Q                                  | 2
  47:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  48:Core/Src/system_stm32g4xx.c ****   *        PLL_R                                  | 2
  49:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  50:Core/Src/system_stm32g4xx.c ****   *        Require 48MHz for RNG                  | Disabled
  51:Core/Src/system_stm32g4xx.c ****   *-----------------------------------------------------------------------------
  52:Core/Src/system_stm32g4xx.c ****   *=============================================================================
  53:Core/Src/system_stm32g4xx.c ****   ******************************************************************************
  54:Core/Src/system_stm32g4xx.c ****   * @attention
  55:Core/Src/system_stm32g4xx.c ****   *
  56:Core/Src/system_stm32g4xx.c ****   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
  57:Core/Src/system_stm32g4xx.c ****   * All rights reserved.</center></h2>
  58:Core/Src/system_stm32g4xx.c ****   *
  59:Core/Src/system_stm32g4xx.c ****   * This software component is licensed by ST under BSD 3-Clause license,
  60:Core/Src/system_stm32g4xx.c ****   * the "License"; You may not use this file except in compliance with the
  61:Core/Src/system_stm32g4xx.c ****   * License. You may obtain a copy of the License at:
  62:Core/Src/system_stm32g4xx.c ****   *                        opensource.org/licenses/BSD-3-Clause
  63:Core/Src/system_stm32g4xx.c ****   *
  64:Core/Src/system_stm32g4xx.c ****   ******************************************************************************
  65:Core/Src/system_stm32g4xx.c ****   */
  66:Core/Src/system_stm32g4xx.c **** 
  67:Core/Src/system_stm32g4xx.c **** /** @addtogroup CMSIS
  68:Core/Src/system_stm32g4xx.c ****   * @{
  69:Core/Src/system_stm32g4xx.c ****   */
  70:Core/Src/system_stm32g4xx.c **** 
  71:Core/Src/system_stm32g4xx.c **** /** @addtogroup stm32g4xx_system
  72:Core/Src/system_stm32g4xx.c ****   * @{
  73:Core/Src/system_stm32g4xx.c ****   */
  74:Core/Src/system_stm32g4xx.c **** 
  75:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Includes
  76:Core/Src/system_stm32g4xx.c ****   * @{
  77:Core/Src/system_stm32g4xx.c ****   */
  78:Core/Src/system_stm32g4xx.c **** 
  79:Core/Src/system_stm32g4xx.c **** #include "stm32g4xx.h"
  80:Core/Src/system_stm32g4xx.c **** 
  81:Core/Src/system_stm32g4xx.c **** #if !defined  (HSE_VALUE)
  82:Core/Src/system_stm32g4xx.c ****   #define HSE_VALUE     24000000U /*!< Value of the External oscillator in Hz */
  83:Core/Src/system_stm32g4xx.c **** #endif /* HSE_VALUE */
  84:Core/Src/system_stm32g4xx.c **** 
  85:Core/Src/system_stm32g4xx.c **** #if !defined  (HSI_VALUE)
  86:Core/Src/system_stm32g4xx.c ****   #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
  87:Core/Src/system_stm32g4xx.c **** #endif /* HSI_VALUE */
  88:Core/Src/system_stm32g4xx.c **** 
ARM GAS  /tmp/cc1m4PcV.s 			page 3


  89:Core/Src/system_stm32g4xx.c **** /**
  90:Core/Src/system_stm32g4xx.c ****   * @}
  91:Core/Src/system_stm32g4xx.c ****   */
  92:Core/Src/system_stm32g4xx.c **** 
  93:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_TypesDefinitions
  94:Core/Src/system_stm32g4xx.c ****   * @{
  95:Core/Src/system_stm32g4xx.c ****   */
  96:Core/Src/system_stm32g4xx.c **** 
  97:Core/Src/system_stm32g4xx.c **** /**
  98:Core/Src/system_stm32g4xx.c ****   * @}
  99:Core/Src/system_stm32g4xx.c ****   */
 100:Core/Src/system_stm32g4xx.c **** 
 101:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Defines
 102:Core/Src/system_stm32g4xx.c ****   * @{
 103:Core/Src/system_stm32g4xx.c ****   */
 104:Core/Src/system_stm32g4xx.c **** 
 105:Core/Src/system_stm32g4xx.c **** /************************* Miscellaneous Configuration ************************/
 106:Core/Src/system_stm32g4xx.c **** /* Note: Following vector table addresses must be defined in line with linker
 107:Core/Src/system_stm32g4xx.c ****          configuration. */
 108:Core/Src/system_stm32g4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
 109:Core/Src/system_stm32g4xx.c ****      anywhere in Flash or Sram, else the vector table is kept at the automatic
 110:Core/Src/system_stm32g4xx.c ****      remap of boot address selected */
 111:Core/Src/system_stm32g4xx.c **** /* #define USER_VECT_TAB_ADDRESS */
 112:Core/Src/system_stm32g4xx.c **** 
 113:Core/Src/system_stm32g4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 114:Core/Src/system_stm32g4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
 115:Core/Src/system_stm32g4xx.c ****      in Sram else user remap will be done in Flash. */
 116:Core/Src/system_stm32g4xx.c **** /* #define VECT_TAB_SRAM */
 117:Core/Src/system_stm32g4xx.c **** #if defined(VECT_TAB_SRAM)
 118:Core/Src/system_stm32g4xx.c **** #define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
 119:Core/Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
 120:Core/Src/system_stm32g4xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 121:Core/Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
 122:Core/Src/system_stm32g4xx.c **** #else
 123:Core/Src/system_stm32g4xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
 124:Core/Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
 125:Core/Src/system_stm32g4xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 126:Core/Src/system_stm32g4xx.c ****                                                      This value must be a multiple of 0x200. */
 127:Core/Src/system_stm32g4xx.c **** #endif /* VECT_TAB_SRAM */
 128:Core/Src/system_stm32g4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 129:Core/Src/system_stm32g4xx.c **** /******************************************************************************/
 130:Core/Src/system_stm32g4xx.c **** /**
 131:Core/Src/system_stm32g4xx.c ****   * @}
 132:Core/Src/system_stm32g4xx.c ****   */
 133:Core/Src/system_stm32g4xx.c **** 
 134:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Macros
 135:Core/Src/system_stm32g4xx.c ****   * @{
 136:Core/Src/system_stm32g4xx.c ****   */
 137:Core/Src/system_stm32g4xx.c **** 
 138:Core/Src/system_stm32g4xx.c **** /**
 139:Core/Src/system_stm32g4xx.c ****   * @}
 140:Core/Src/system_stm32g4xx.c ****   */
 141:Core/Src/system_stm32g4xx.c **** 
 142:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Variables
 143:Core/Src/system_stm32g4xx.c ****   * @{
 144:Core/Src/system_stm32g4xx.c ****   */
 145:Core/Src/system_stm32g4xx.c ****   /* The SystemCoreClock variable is updated in three ways:
ARM GAS  /tmp/cc1m4PcV.s 			page 4


 146:Core/Src/system_stm32g4xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 147:Core/Src/system_stm32g4xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 148:Core/Src/system_stm32g4xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 149:Core/Src/system_stm32g4xx.c ****          Note: If you use this function to configure the system clock; then there
 150:Core/Src/system_stm32g4xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
 151:Core/Src/system_stm32g4xx.c ****                variable is updated automatically.
 152:Core/Src/system_stm32g4xx.c ****   */
 153:Core/Src/system_stm32g4xx.c ****   uint32_t SystemCoreClock = HSI_VALUE;
 154:Core/Src/system_stm32g4xx.c **** 
 155:Core/Src/system_stm32g4xx.c ****   const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U
 156:Core/Src/system_stm32g4xx.c ****   const uint8_t APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
 157:Core/Src/system_stm32g4xx.c **** 
 158:Core/Src/system_stm32g4xx.c **** /**
 159:Core/Src/system_stm32g4xx.c ****   * @}
 160:Core/Src/system_stm32g4xx.c ****   */
 161:Core/Src/system_stm32g4xx.c **** 
 162:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
 163:Core/Src/system_stm32g4xx.c ****   * @{
 164:Core/Src/system_stm32g4xx.c ****   */
 165:Core/Src/system_stm32g4xx.c **** 
 166:Core/Src/system_stm32g4xx.c **** /**
 167:Core/Src/system_stm32g4xx.c ****   * @}
 168:Core/Src/system_stm32g4xx.c ****   */
 169:Core/Src/system_stm32g4xx.c **** 
 170:Core/Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Functions
 171:Core/Src/system_stm32g4xx.c ****   * @{
 172:Core/Src/system_stm32g4xx.c ****   */
 173:Core/Src/system_stm32g4xx.c **** 
 174:Core/Src/system_stm32g4xx.c **** /**
 175:Core/Src/system_stm32g4xx.c ****   * @brief  Setup the microcontroller system.
 176:Core/Src/system_stm32g4xx.c ****   * @param  None
 177:Core/Src/system_stm32g4xx.c ****   * @retval None
 178:Core/Src/system_stm32g4xx.c ****   */
 179:Core/Src/system_stm32g4xx.c **** 
 180:Core/Src/system_stm32g4xx.c **** void SystemInit(void)
 181:Core/Src/system_stm32g4xx.c **** {
  28              		.loc 1 181 0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		@ link register save eliminated.
 182:Core/Src/system_stm32g4xx.c ****   /* FPU settings ------------------------------------------------------------*/
 183:Core/Src/system_stm32g4xx.c ****   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 184:Core/Src/system_stm32g4xx.c ****     SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
  33              		.loc 1 184 0
  34 0000 034A     		ldr	r2, .L2
  35 0002 D2F88830 		ldr	r3, [r2, #136]
  36 0006 43F47003 		orr	r3, r3, #15728640
  37 000a C2F88830 		str	r3, [r2, #136]
 185:Core/Src/system_stm32g4xx.c ****   #endif
 186:Core/Src/system_stm32g4xx.c **** 
 187:Core/Src/system_stm32g4xx.c ****   /* Configure the Vector Table location add offset address ------------------*/
 188:Core/Src/system_stm32g4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 189:Core/Src/system_stm32g4xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 
 190:Core/Src/system_stm32g4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 191:Core/Src/system_stm32g4xx.c **** }
  38              		.loc 1 191 0
ARM GAS  /tmp/cc1m4PcV.s 			page 5


  39 000e 7047     		bx	lr
  40              	.L3:
  41              		.align	2
  42              	.L2:
  43 0010 00ED00E0 		.word	-536810240
  44              		.cfi_endproc
  45              	.LFE132:
  47              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  48              		.align	1
  49              		.global	SystemCoreClockUpdate
  50              		.syntax unified
  51              		.thumb
  52              		.thumb_func
  53              		.fpu fpv4-sp-d16
  55              	SystemCoreClockUpdate:
  56              	.LFB133:
 192:Core/Src/system_stm32g4xx.c **** 
 193:Core/Src/system_stm32g4xx.c **** /**
 194:Core/Src/system_stm32g4xx.c ****   * @brief  Update SystemCoreClock variable according to Clock Register Values.
 195:Core/Src/system_stm32g4xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 196:Core/Src/system_stm32g4xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 197:Core/Src/system_stm32g4xx.c ****   *         other parameters.
 198:Core/Src/system_stm32g4xx.c ****   *
 199:Core/Src/system_stm32g4xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 200:Core/Src/system_stm32g4xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 201:Core/Src/system_stm32g4xx.c ****   *         based on this variable will be incorrect.
 202:Core/Src/system_stm32g4xx.c ****   *
 203:Core/Src/system_stm32g4xx.c ****   * @note   - The system frequency computed by this function is not the real
 204:Core/Src/system_stm32g4xx.c ****   *           frequency in the chip. It is calculated based on the predefined
 205:Core/Src/system_stm32g4xx.c ****   *           constant and the selected clock source:
 206:Core/Src/system_stm32g4xx.c ****   *
 207:Core/Src/system_stm32g4xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
 208:Core/Src/system_stm32g4xx.c ****   *
 209:Core/Src/system_stm32g4xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
 210:Core/Src/system_stm32g4xx.c ****   *
 211:Core/Src/system_stm32g4xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
 212:Core/Src/system_stm32g4xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 213:Core/Src/system_stm32g4xx.c ****   *
 214:Core/Src/system_stm32g4xx.c ****   *         (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
 215:Core/Src/system_stm32g4xx.c ****   *              16 MHz) but the real value may vary depending on the variations
 216:Core/Src/system_stm32g4xx.c ****   *              in voltage and temperature.
 217:Core/Src/system_stm32g4xx.c ****   *
 218:Core/Src/system_stm32g4xx.c ****   *         (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
 219:Core/Src/system_stm32g4xx.c ****   *              24 MHz), user has to ensure that HSE_VALUE is same as the real
 220:Core/Src/system_stm32g4xx.c ****   *              frequency of the crystal used. Otherwise, this function may
 221:Core/Src/system_stm32g4xx.c ****   *              have wrong result.
 222:Core/Src/system_stm32g4xx.c ****   *
 223:Core/Src/system_stm32g4xx.c ****   *         - The result of this function could be not correct when using fractional
 224:Core/Src/system_stm32g4xx.c ****   *           value for HSE crystal.
 225:Core/Src/system_stm32g4xx.c ****   *
 226:Core/Src/system_stm32g4xx.c ****   * @param  None
 227:Core/Src/system_stm32g4xx.c ****   * @retval None
 228:Core/Src/system_stm32g4xx.c ****   */
 229:Core/Src/system_stm32g4xx.c **** void SystemCoreClockUpdate(void)
 230:Core/Src/system_stm32g4xx.c **** {
  57              		.loc 1 230 0
  58              		.cfi_startproc
ARM GAS  /tmp/cc1m4PcV.s 			page 6


  59              		@ args = 0, pretend = 0, frame = 0
  60              		@ frame_needed = 0, uses_anonymous_args = 0
  61              		@ link register save eliminated.
 231:Core/Src/system_stm32g4xx.c ****   uint32_t tmp, pllvco, pllr, pllsource, pllm;
 232:Core/Src/system_stm32g4xx.c **** 
 233:Core/Src/system_stm32g4xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 234:Core/Src/system_stm32g4xx.c ****   switch (RCC->CFGR & RCC_CFGR_SWS)
  62              		.loc 1 234 0
  63 0000 1E4B     		ldr	r3, .L13
  64 0002 9B68     		ldr	r3, [r3, #8]
  65 0004 03F00C03 		and	r3, r3, #12
  66 0008 082B     		cmp	r3, #8
  67 000a 12D0     		beq	.L6
  68 000c 0C2B     		cmp	r3, #12
  69 000e 14D0     		beq	.L7
  70 0010 042B     		cmp	r3, #4
  71 0012 0AD0     		beq	.L11
  72              	.L5:
 235:Core/Src/system_stm32g4xx.c ****   {
 236:Core/Src/system_stm32g4xx.c ****     case 0x04:  /* HSI used as system clock source */
 237:Core/Src/system_stm32g4xx.c ****       SystemCoreClock = HSI_VALUE;
 238:Core/Src/system_stm32g4xx.c ****       break;
 239:Core/Src/system_stm32g4xx.c **** 
 240:Core/Src/system_stm32g4xx.c ****     case 0x08:  /* HSE used as system clock source */
 241:Core/Src/system_stm32g4xx.c ****       SystemCoreClock = HSE_VALUE;
 242:Core/Src/system_stm32g4xx.c ****       break;
 243:Core/Src/system_stm32g4xx.c **** 
 244:Core/Src/system_stm32g4xx.c ****     case 0x0C:  /* PLL used as system clock  source */
 245:Core/Src/system_stm32g4xx.c ****       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
 246:Core/Src/system_stm32g4xx.c ****          SYSCLK = PLL_VCO / PLLR
 247:Core/Src/system_stm32g4xx.c ****          */
 248:Core/Src/system_stm32g4xx.c ****       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
 249:Core/Src/system_stm32g4xx.c ****       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
 250:Core/Src/system_stm32g4xx.c ****       if (pllsource == 0x02UL) /* HSI used as PLL clock source */
 251:Core/Src/system_stm32g4xx.c ****       {
 252:Core/Src/system_stm32g4xx.c ****         pllvco = (HSI_VALUE / pllm);
 253:Core/Src/system_stm32g4xx.c ****       }
 254:Core/Src/system_stm32g4xx.c ****       else                   /* HSE used as PLL clock source */
 255:Core/Src/system_stm32g4xx.c ****       {
 256:Core/Src/system_stm32g4xx.c ****         pllvco = (HSE_VALUE / pllm);
 257:Core/Src/system_stm32g4xx.c ****       }
 258:Core/Src/system_stm32g4xx.c ****       pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
 259:Core/Src/system_stm32g4xx.c ****       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
 260:Core/Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
 261:Core/Src/system_stm32g4xx.c ****       break;
 262:Core/Src/system_stm32g4xx.c **** 
 263:Core/Src/system_stm32g4xx.c ****     default:
 264:Core/Src/system_stm32g4xx.c ****       break;
 265:Core/Src/system_stm32g4xx.c ****   }
 266:Core/Src/system_stm32g4xx.c ****   /* Compute HCLK clock frequency --------------------------------------------*/
 267:Core/Src/system_stm32g4xx.c ****   /* Get HCLK prescaler */
 268:Core/Src/system_stm32g4xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  73              		.loc 1 268 0
  74 0014 194B     		ldr	r3, .L13
  75 0016 9B68     		ldr	r3, [r3, #8]
  76 0018 C3F30313 		ubfx	r3, r3, #4, #4
  77 001c 184A     		ldr	r2, .L13+4
ARM GAS  /tmp/cc1m4PcV.s 			page 7


  78 001e D15C     		ldrb	r1, [r2, r3]	@ zero_extendqisi2
  79              	.LVL0:
 269:Core/Src/system_stm32g4xx.c ****   /* HCLK clock frequency */
 270:Core/Src/system_stm32g4xx.c ****   SystemCoreClock >>= tmp;
  80              		.loc 1 270 0
  81 0020 184A     		ldr	r2, .L13+8
  82 0022 1368     		ldr	r3, [r2]
  83 0024 CB40     		lsrs	r3, r3, r1
  84 0026 1360     		str	r3, [r2]
 271:Core/Src/system_stm32g4xx.c **** }
  85              		.loc 1 271 0
  86 0028 7047     		bx	lr
  87              	.LVL1:
  88              	.L11:
 237:Core/Src/system_stm32g4xx.c ****       break;
  89              		.loc 1 237 0
  90 002a 164B     		ldr	r3, .L13+8
  91 002c 164A     		ldr	r2, .L13+12
  92 002e 1A60     		str	r2, [r3]
 238:Core/Src/system_stm32g4xx.c **** 
  93              		.loc 1 238 0
  94 0030 F0E7     		b	.L5
  95              	.L6:
 241:Core/Src/system_stm32g4xx.c ****       break;
  96              		.loc 1 241 0
  97 0032 144B     		ldr	r3, .L13+8
  98 0034 154A     		ldr	r2, .L13+16
  99 0036 1A60     		str	r2, [r3]
 242:Core/Src/system_stm32g4xx.c **** 
 100              		.loc 1 242 0
 101 0038 ECE7     		b	.L5
 102              	.L7:
 248:Core/Src/system_stm32g4xx.c ****       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
 103              		.loc 1 248 0
 104 003a 104B     		ldr	r3, .L13
 105 003c DA68     		ldr	r2, [r3, #12]
 106 003e 02F00302 		and	r2, r2, #3
 107              	.LVL2:
 249:Core/Src/system_stm32g4xx.c ****       if (pllsource == 0x02UL) /* HSI used as PLL clock source */
 108              		.loc 1 249 0
 109 0042 DB68     		ldr	r3, [r3, #12]
 110 0044 C3F30313 		ubfx	r3, r3, #4, #4
 111 0048 0133     		adds	r3, r3, #1
 112              	.LVL3:
 250:Core/Src/system_stm32g4xx.c ****       {
 113              		.loc 1 250 0
 114 004a 022A     		cmp	r2, #2
 115 004c 12D0     		beq	.L12
 256:Core/Src/system_stm32g4xx.c ****       }
 116              		.loc 1 256 0
 117 004e 0F4A     		ldr	r2, .L13+16
 118              	.LVL4:
 119 0050 B2FBF3F3 		udiv	r3, r2, r3
 120              	.LVL5:
 121              	.L10:
 258:Core/Src/system_stm32g4xx.c ****       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
 122              		.loc 1 258 0
ARM GAS  /tmp/cc1m4PcV.s 			page 8


 123 0054 0949     		ldr	r1, .L13
 124 0056 CA68     		ldr	r2, [r1, #12]
 125 0058 C2F30622 		ubfx	r2, r2, #8, #7
 126 005c 03FB02F3 		mul	r3, r3, r2
 127              	.LVL6:
 259:Core/Src/system_stm32g4xx.c ****       SystemCoreClock = pllvco/pllr;
 128              		.loc 1 259 0
 129 0060 CA68     		ldr	r2, [r1, #12]
 130 0062 C2F34162 		ubfx	r2, r2, #25, #2
 131 0066 0132     		adds	r2, r2, #1
 132 0068 5200     		lsls	r2, r2, #1
 133              	.LVL7:
 260:Core/Src/system_stm32g4xx.c ****       break;
 134              		.loc 1 260 0
 135 006a B3FBF2F3 		udiv	r3, r3, r2
 136              	.LVL8:
 137 006e 054A     		ldr	r2, .L13+8
 138              	.LVL9:
 139 0070 1360     		str	r3, [r2]
 261:Core/Src/system_stm32g4xx.c **** 
 140              		.loc 1 261 0
 141 0072 CFE7     		b	.L5
 142              	.LVL10:
 143              	.L12:
 252:Core/Src/system_stm32g4xx.c ****       }
 144              		.loc 1 252 0
 145 0074 044A     		ldr	r2, .L13+12
 146              	.LVL11:
 147 0076 B2FBF3F3 		udiv	r3, r2, r3
 148              	.LVL12:
 149 007a EBE7     		b	.L10
 150              	.L14:
 151              		.align	2
 152              	.L13:
 153 007c 00100240 		.word	1073876992
 154 0080 00000000 		.word	.LANCHOR1
 155 0084 00000000 		.word	.LANCHOR0
 156 0088 0024F400 		.word	16000000
 157 008c 00366E01 		.word	24000000
 158              		.cfi_endproc
 159              	.LFE133:
 161              		.global	APBPrescTable
 162              		.global	AHBPrescTable
 163              		.global	SystemCoreClock
 164              		.section	.data.SystemCoreClock,"aw",%progbits
 165              		.align	2
 166              		.set	.LANCHOR0,. + 0
 169              	SystemCoreClock:
 170 0000 0024F400 		.word	16000000
 171              		.section	.rodata.AHBPrescTable,"a",%progbits
 172              		.align	2
 173              		.set	.LANCHOR1,. + 0
 176              	AHBPrescTable:
 177 0000 00       		.byte	0
 178 0001 00       		.byte	0
 179 0002 00       		.byte	0
 180 0003 00       		.byte	0
ARM GAS  /tmp/cc1m4PcV.s 			page 9


 181 0004 00       		.byte	0
 182 0005 00       		.byte	0
 183 0006 00       		.byte	0
 184 0007 00       		.byte	0
 185 0008 01       		.byte	1
 186 0009 02       		.byte	2
 187 000a 03       		.byte	3
 188 000b 04       		.byte	4
 189 000c 06       		.byte	6
 190 000d 07       		.byte	7
 191 000e 08       		.byte	8
 192 000f 09       		.byte	9
 193              		.section	.rodata.APBPrescTable,"a",%progbits
 194              		.align	2
 197              	APBPrescTable:
 198 0000 00       		.byte	0
 199 0001 00       		.byte	0
 200 0002 00       		.byte	0
 201 0003 00       		.byte	0
 202 0004 01       		.byte	1
 203 0005 02       		.byte	2
 204 0006 03       		.byte	3
 205 0007 04       		.byte	4
 206              		.text
 207              	.Letext0:
 208              		.file 2 "/usr/include/newlib/machine/_default_types.h"
 209              		.file 3 "/usr/include/newlib/sys/_stdint.h"
 210              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
 211              		.file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
 212              		.file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
 213              		.file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
 214              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
 215              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
 216              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
ARM GAS  /tmp/cc1m4PcV.s 			page 10


DEFINED SYMBOLS
                            *ABS*:0000000000000000 system_stm32g4xx.c
     /tmp/cc1m4PcV.s:18     .text.SystemInit:0000000000000000 $t
     /tmp/cc1m4PcV.s:25     .text.SystemInit:0000000000000000 SystemInit
     /tmp/cc1m4PcV.s:43     .text.SystemInit:0000000000000010 $d
     /tmp/cc1m4PcV.s:48     .text.SystemCoreClockUpdate:0000000000000000 $t
     /tmp/cc1m4PcV.s:55     .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
     /tmp/cc1m4PcV.s:153    .text.SystemCoreClockUpdate:000000000000007c $d
     /tmp/cc1m4PcV.s:197    .rodata.APBPrescTable:0000000000000000 APBPrescTable
     /tmp/cc1m4PcV.s:176    .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
     /tmp/cc1m4PcV.s:169    .data.SystemCoreClock:0000000000000000 SystemCoreClock
     /tmp/cc1m4PcV.s:165    .data.SystemCoreClock:0000000000000000 $d
     /tmp/cc1m4PcV.s:172    .rodata.AHBPrescTable:0000000000000000 $d
     /tmp/cc1m4PcV.s:194    .rodata.APBPrescTable:0000000000000000 $d

NO UNDEFINED SYMBOLS
