ARM GAS  /tmp/ccrhJjjK.s 			page 1


   1              		.cpu cortex-m4
   2              		.eabi_attribute 27, 1
   3              		.eabi_attribute 28, 1
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 1
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"main.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.section	.text.MX_GPIO_Init,"ax",%progbits
  18              		.align	1
  19              		.syntax unified
  20              		.thumb
  21              		.thumb_func
  22              		.fpu fpv4-sp-d16
  24              	MX_GPIO_Init:
  25              	.LFB148:
  26              		.file 1 "Core/Src/main.c"
   1:Core/Src/main.c **** /* USER CODE BEGIN Header */
   2:Core/Src/main.c **** /**
   3:Core/Src/main.c ****   ******************************************************************************
   4:Core/Src/main.c ****   * @file           : main.c
   5:Core/Src/main.c ****   * @brief          : Main program body
   6:Core/Src/main.c ****   ******************************************************************************
   7:Core/Src/main.c ****   * @attention
   8:Core/Src/main.c ****   *
   9:Core/Src/main.c ****   * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
  10:Core/Src/main.c ****   * All rights reserved.</center></h2>
  11:Core/Src/main.c ****   *
  12:Core/Src/main.c ****   * This software component is licensed by ST under BSD 3-Clause license,
  13:Core/Src/main.c ****   * the "License"; You may not use this file except in compliance with the
  14:Core/Src/main.c ****   * License. You may obtain a copy of the License at:
  15:Core/Src/main.c ****   *                        opensource.org/licenses/BSD-3-Clause
  16:Core/Src/main.c ****   *
  17:Core/Src/main.c ****   ******************************************************************************
  18:Core/Src/main.c ****   */
  19:Core/Src/main.c **** /* USER CODE END Header */
  20:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
  21:Core/Src/main.c **** #include "main.h"
  22:Core/Src/main.c **** 
  23:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
  24:Core/Src/main.c **** /* USER CODE BEGIN Includes */
  25:Core/Src/main.c **** #include "palmipede.h"
  26:Core/Src/main.c **** 
  27:Core/Src/main.c **** /* USER CODE END Includes */
  28:Core/Src/main.c **** 
  29:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
  30:Core/Src/main.c **** /* USER CODE BEGIN PTD */
  31:Core/Src/main.c **** 
  32:Core/Src/main.c **** /* USER CODE END PTD */
ARM GAS  /tmp/ccrhJjjK.s 			page 2


  33:Core/Src/main.c **** 
  34:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
  35:Core/Src/main.c **** /* USER CODE BEGIN PD */
  36:Core/Src/main.c **** /* USER CODE END PD */
  37:Core/Src/main.c **** 
  38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
  39:Core/Src/main.c **** /* USER CODE BEGIN PM */
  40:Core/Src/main.c **** 
  41:Core/Src/main.c **** /* USER CODE END PM */
  42:Core/Src/main.c **** 
  43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
  44:Core/Src/main.c **** UART_HandleTypeDef hlpuart1;
  45:Core/Src/main.c **** UART_HandleTypeDef huart1;
  46:Core/Src/main.c **** UART_HandleTypeDef huart2;
  47:Core/Src/main.c **** DMA_HandleTypeDef hdma_usart1_tx;
  48:Core/Src/main.c **** DMA_HandleTypeDef hdma_usart2_tx;
  49:Core/Src/main.c **** 
  50:Core/Src/main.c **** TIM_HandleTypeDef htim7;
  51:Core/Src/main.c **** 
  52:Core/Src/main.c **** /* USER CODE BEGIN PV */
  53:Core/Src/main.c **** volatile uint8_t tick;
  54:Core/Src/main.c **** 
  55:Core/Src/main.c **** /* USER CODE END PV */
  56:Core/Src/main.c **** 
  57:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
  58:Core/Src/main.c **** void SystemClock_Config(void);
  59:Core/Src/main.c **** static void MX_GPIO_Init(void);
  60:Core/Src/main.c **** static void MX_DMA_Init(void);
  61:Core/Src/main.c **** static void MX_USART1_UART_Init(void);
  62:Core/Src/main.c **** static void MX_USART2_UART_Init(void);
  63:Core/Src/main.c **** static void MX_TIM7_Init(void);
  64:Core/Src/main.c **** static void MX_LPUART1_UART_Init(void);
  65:Core/Src/main.c **** /* USER CODE BEGIN PFP */
  66:Core/Src/main.c **** 
  67:Core/Src/main.c **** /* USER CODE END PFP */
  68:Core/Src/main.c **** 
  69:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
  70:Core/Src/main.c **** /* USER CODE BEGIN 0 */
  71:Core/Src/main.c **** // uart
  72:Core/Src/main.c **** 
  73:Core/Src/main.c **** void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){
  74:Core/Src/main.c ****         if (huart == &huart1){
  75:Core/Src/main.c ****                 enqueue_cmd(uart1_rx_buf[0]);
  76:Core/Src/main.c ****                 HAL_UART_Receive_IT(&huart1, uart1_rx_buf, 1);
  77:Core/Src/main.c ****         }
  78:Core/Src/main.c **** 
  79:Core/Src/main.c ****         if (huart == &huart2){
  80:Core/Src/main.c ****                 enqueue_cmd(uart2_rx_buf[0]);
  81:Core/Src/main.c ****                 HAL_UART_Receive_IT(&huart2, uart2_rx_buf, 1);
  82:Core/Src/main.c ****         }
  83:Core/Src/main.c **** 
  84:Core/Src/main.c ****         if (huart == &hlpuart1){
  85:Core/Src/main.c ****                 enqueue_nmea(uart3_rx_buf[0]);
  86:Core/Src/main.c ****                 HAL_UART_Receive_IT(&hlpuart1, uart3_rx_buf, 1);
  87:Core/Src/main.c ****         }
  88:Core/Src/main.c **** 
  89:Core/Src/main.c **** }
ARM GAS  /tmp/ccrhJjjK.s 			page 3


  90:Core/Src/main.c **** 
  91:Core/Src/main.c **** int _write(int file,char *ptr, int len){
  92:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart1, ptr, len);
  93:Core/Src/main.c ****         return len;
  94:Core/Src/main.c **** }
  95:Core/Src/main.c **** 
  96:Core/Src/main.c **** int display_write(char *ptr, int len){
  97:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart1, ptr, len);
  98:Core/Src/main.c ****         return len;
  99:Core/Src/main.c **** }
 100:Core/Src/main.c **** 
 101:Core/Src/main.c **** void display_write2(char *ptr){
 102:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart1, ptr, strlen(ptr));
 103:Core/Src/main.c **** }
 104:Core/Src/main.c **** 
 105:Core/Src/main.c **** void radio_write(char *ptr){
 106:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart2, ptr, strlen(ptr));
 107:Core/Src/main.c **** }
 108:Core/Src/main.c **** 
 109:Core/Src/main.c **** void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim){
 110:Core/Src/main.c ****     if (htim->Instance == TIM7){
 111:Core/Src/main.c ****                 tick = 1;
 112:Core/Src/main.c ****     }
 113:Core/Src/main.c **** }
 114:Core/Src/main.c **** 
 115:Core/Src/main.c **** /* USER CODE END 0 */
 116:Core/Src/main.c **** 
 117:Core/Src/main.c **** /**
 118:Core/Src/main.c ****   * @brief  The application entry point.
 119:Core/Src/main.c ****   * @retval int
 120:Core/Src/main.c ****   */
 121:Core/Src/main.c **** int main(void)
 122:Core/Src/main.c **** {
 123:Core/Src/main.c ****   /* USER CODE BEGIN 1 */
 124:Core/Src/main.c **** 
 125:Core/Src/main.c ****   /* USER CODE END 1 */
 126:Core/Src/main.c **** 
 127:Core/Src/main.c ****   /* MCU Configuration--------------------------------------------------------*/
 128:Core/Src/main.c **** 
 129:Core/Src/main.c ****   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
 130:Core/Src/main.c ****   HAL_Init();
 131:Core/Src/main.c **** 
 132:Core/Src/main.c ****   /* USER CODE BEGIN Init */
 133:Core/Src/main.c **** 
 134:Core/Src/main.c ****   /* USER CODE END Init */
 135:Core/Src/main.c **** 
 136:Core/Src/main.c ****   /* Configure the system clock */
 137:Core/Src/main.c ****   SystemClock_Config();
 138:Core/Src/main.c **** 
 139:Core/Src/main.c ****   /* USER CODE BEGIN SysInit */
 140:Core/Src/main.c **** 
 141:Core/Src/main.c ****   /* USER CODE END SysInit */
 142:Core/Src/main.c **** 
 143:Core/Src/main.c ****   /* Initialize all configured peripherals */
 144:Core/Src/main.c ****   MX_GPIO_Init();
 145:Core/Src/main.c ****   MX_DMA_Init();
 146:Core/Src/main.c ****   MX_USART1_UART_Init();
ARM GAS  /tmp/ccrhJjjK.s 			page 4


 147:Core/Src/main.c ****   MX_USART2_UART_Init();
 148:Core/Src/main.c ****   MX_TIM7_Init();
 149:Core/Src/main.c ****   MX_LPUART1_UART_Init();
 150:Core/Src/main.c ****   /* USER CODE BEGIN 2 */
 151:Core/Src/main.c ****   HAL_TIM_Base_Start_IT(&htim7);
 152:Core/Src/main.c ****   HAL_UART_Receive_IT(&huart1, uart1_rx_buf, 1);
 153:Core/Src/main.c ****   HAL_UART_Receive_IT(&huart2, uart2_rx_buf, 1);
 154:Core/Src/main.c ****   HAL_UART_Receive_IT(&hlpuart1, uart3_rx_buf, 1);
 155:Core/Src/main.c ****   /* USER CODE END 2 */
 156:Core/Src/main.c **** 
 157:Core/Src/main.c ****   /* Infinite loop */
 158:Core/Src/main.c ****   /* USER CODE BEGIN WHILE */
 159:Core/Src/main.c ****   HAL_Delay(100);
 160:Core/Src/main.c ****   display_write2("start:");
 161:Core/Src/main.c **** //  display_write2("\x1B[200,100q");
 162:Core/Src/main.c ****   while (1)
 163:Core/Src/main.c ****   {
 164:Core/Src/main.c **** //	HAL_Delay(1000);
 165:Core/Src/main.c ****         while(rx_cmd_rb_in_idx != rx_cmd_rb_out_idx) dequeue_cmd();
 166:Core/Src/main.c ****         if(tick){
 167:Core/Src/main.c **** 		HAL_GPIO_TogglePin(LD2_GPIO_Port, LD2_Pin); //Toggle LED
 168:Core/Src/main.c **** //		display_write("a", 1);
 169:Core/Src/main.c **** //		radio_write("AT+DMOCONNECT \r\n");
 170:Core/Src/main.c **** //		radio_write("1234567890");
 171:Core/Src/main.c **** //		HAL_UART_Transmit_DMA(&huart2, "AT+DMOCONNECT\r\n", 15);
 172:Core/Src/main.c **** //		HAL_UART_Transmit_DMA(&huart2, "AT+DMOSETVOLUME=8\r\n",19);
 173:Core/Src/main.c **** //		radio_write("AT+DMOSETVOLUME=8\r\n");
 174:Core/Src/main.c **** //		HAL_Delay(200);
 175:Core/Src/main.c **** //		HAL_UART_Transmit_DMA(&huart2, "AT+DMOSETGROUP=1,433.5750,433.5750,0000,1,0000\r\n", 48);
 176:Core/Src/main.c **** 		radio_write("AT+DMOSETGROUP=1,433.5750,433.5750,0000,1,0000\r\n");
 177:Core/Src/main.c **** //		radio_write("AT+DMOSETGROUP=0,446.8250,446.8250,0000,0,0000\r\n");
 178:Core/Src/main.c **** //		HAL_UART_Transmit_DMA(&huart1, "a", 1);
 179:Core/Src/main.c ****                 tick = 0;
 180:Core/Src/main.c ****          }
 181:Core/Src/main.c **** 
 182:Core/Src/main.c ****     /* USER CODE END WHILE */
 183:Core/Src/main.c **** 
 184:Core/Src/main.c ****     /* USER CODE BEGIN 3 */
 185:Core/Src/main.c ****   }
 186:Core/Src/main.c ****   /* USER CODE END 3 */
 187:Core/Src/main.c **** }
 188:Core/Src/main.c **** 
 189:Core/Src/main.c **** /**
 190:Core/Src/main.c ****   * @brief System Clock Configuration
 191:Core/Src/main.c ****   * @retval None
 192:Core/Src/main.c ****   */
 193:Core/Src/main.c **** void SystemClock_Config(void)
 194:Core/Src/main.c **** {
 195:Core/Src/main.c ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 196:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 197:Core/Src/main.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 198:Core/Src/main.c **** 
 199:Core/Src/main.c ****   /** Configure the main internal regulator output voltage
 200:Core/Src/main.c ****   */
 201:Core/Src/main.c ****   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 202:Core/Src/main.c ****   /** Initializes the RCC Oscillators according to the specified parameters
 203:Core/Src/main.c ****   * in the RCC_OscInitTypeDef structure.
ARM GAS  /tmp/ccrhJjjK.s 			page 5


 204:Core/Src/main.c ****   */
 205:Core/Src/main.c ****   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
 206:Core/Src/main.c ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 207:Core/Src/main.c ****   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 208:Core/Src/main.c ****   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 209:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 210:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 211:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
 212:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLN = 28;
 213:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 214:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 215:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 216:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 217:Core/Src/main.c ****   {
 218:Core/Src/main.c ****     Error_Handler();
 219:Core/Src/main.c ****   }
 220:Core/Src/main.c ****   /** Initializes the CPU, AHB and APB buses clocks
 221:Core/Src/main.c ****   */
 222:Core/Src/main.c ****   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 223:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 224:Core/Src/main.c ****   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 225:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 226:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 227:Core/Src/main.c ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 228:Core/Src/main.c **** 
 229:Core/Src/main.c ****   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 230:Core/Src/main.c ****   {
 231:Core/Src/main.c ****     Error_Handler();
 232:Core/Src/main.c ****   }
 233:Core/Src/main.c ****   /** Initializes the peripherals clocks
 234:Core/Src/main.c ****   */
 235:Core/Src/main.c ****   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2
 236:Core/Src/main.c ****                               |RCC_PERIPHCLK_LPUART1;
 237:Core/Src/main.c ****   PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
 238:Core/Src/main.c ****   PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
 239:Core/Src/main.c ****   PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
 240:Core/Src/main.c ****   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 241:Core/Src/main.c ****   {
 242:Core/Src/main.c ****     Error_Handler();
 243:Core/Src/main.c ****   }
 244:Core/Src/main.c **** }
 245:Core/Src/main.c **** 
 246:Core/Src/main.c **** /**
 247:Core/Src/main.c ****   * @brief LPUART1 Initialization Function
 248:Core/Src/main.c ****   * @param None
 249:Core/Src/main.c ****   * @retval None
 250:Core/Src/main.c ****   */
 251:Core/Src/main.c **** static void MX_LPUART1_UART_Init(void)
 252:Core/Src/main.c **** {
 253:Core/Src/main.c **** 
 254:Core/Src/main.c ****   /* USER CODE BEGIN LPUART1_Init 0 */
 255:Core/Src/main.c **** 
 256:Core/Src/main.c ****   /* USER CODE END LPUART1_Init 0 */
 257:Core/Src/main.c **** 
 258:Core/Src/main.c ****   /* USER CODE BEGIN LPUART1_Init 1 */
 259:Core/Src/main.c **** 
 260:Core/Src/main.c ****   /* USER CODE END LPUART1_Init 1 */
ARM GAS  /tmp/ccrhJjjK.s 			page 6


 261:Core/Src/main.c ****   hlpuart1.Instance = LPUART1;
 262:Core/Src/main.c ****   hlpuart1.Init.BaudRate = 9600;
 263:Core/Src/main.c ****   hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
 264:Core/Src/main.c ****   hlpuart1.Init.StopBits = UART_STOPBITS_1;
 265:Core/Src/main.c ****   hlpuart1.Init.Parity = UART_PARITY_NONE;
 266:Core/Src/main.c ****   hlpuart1.Init.Mode = UART_MODE_TX_RX;
 267:Core/Src/main.c ****   hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 268:Core/Src/main.c ****   hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 269:Core/Src/main.c ****   hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV8;
 270:Core/Src/main.c ****   hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 271:Core/Src/main.c ****   if (HAL_UART_Init(&hlpuart1) != HAL_OK)
 272:Core/Src/main.c ****   {
 273:Core/Src/main.c ****     Error_Handler();
 274:Core/Src/main.c ****   }
 275:Core/Src/main.c ****   if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 276:Core/Src/main.c ****   {
 277:Core/Src/main.c ****     Error_Handler();
 278:Core/Src/main.c ****   }
 279:Core/Src/main.c ****   if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 280:Core/Src/main.c ****   {
 281:Core/Src/main.c ****     Error_Handler();
 282:Core/Src/main.c ****   }
 283:Core/Src/main.c ****   if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
 284:Core/Src/main.c ****   {
 285:Core/Src/main.c ****     Error_Handler();
 286:Core/Src/main.c ****   }
 287:Core/Src/main.c ****   /* USER CODE BEGIN LPUART1_Init 2 */
 288:Core/Src/main.c **** 
 289:Core/Src/main.c ****   /* USER CODE END LPUART1_Init 2 */
 290:Core/Src/main.c **** 
 291:Core/Src/main.c **** }
 292:Core/Src/main.c **** 
 293:Core/Src/main.c **** /**
 294:Core/Src/main.c ****   * @brief USART1 Initialization Function
 295:Core/Src/main.c ****   * @param None
 296:Core/Src/main.c ****   * @retval None
 297:Core/Src/main.c ****   */
 298:Core/Src/main.c **** static void MX_USART1_UART_Init(void)
 299:Core/Src/main.c **** {
 300:Core/Src/main.c **** 
 301:Core/Src/main.c ****   /* USER CODE BEGIN USART1_Init 0 */
 302:Core/Src/main.c **** 
 303:Core/Src/main.c ****   /* USER CODE END USART1_Init 0 */
 304:Core/Src/main.c **** 
 305:Core/Src/main.c ****   /* USER CODE BEGIN USART1_Init 1 */
 306:Core/Src/main.c **** 
 307:Core/Src/main.c ****   /* USER CODE END USART1_Init 1 */
 308:Core/Src/main.c ****   huart1.Instance = USART1;
 309:Core/Src/main.c ****   huart1.Init.BaudRate = 115200;
 310:Core/Src/main.c ****   huart1.Init.WordLength = UART_WORDLENGTH_8B;
 311:Core/Src/main.c ****   huart1.Init.StopBits = UART_STOPBITS_1;
 312:Core/Src/main.c ****   huart1.Init.Parity = UART_PARITY_NONE;
 313:Core/Src/main.c ****   huart1.Init.Mode = UART_MODE_TX_RX;
 314:Core/Src/main.c ****   huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 315:Core/Src/main.c ****   huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 316:Core/Src/main.c ****   huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 317:Core/Src/main.c ****   huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
ARM GAS  /tmp/ccrhJjjK.s 			page 7


 318:Core/Src/main.c ****   huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 319:Core/Src/main.c ****   if (HAL_UART_Init(&huart1) != HAL_OK)
 320:Core/Src/main.c ****   {
 321:Core/Src/main.c ****     Error_Handler();
 322:Core/Src/main.c ****   }
 323:Core/Src/main.c ****   if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 324:Core/Src/main.c ****   {
 325:Core/Src/main.c ****     Error_Handler();
 326:Core/Src/main.c ****   }
 327:Core/Src/main.c ****   if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 328:Core/Src/main.c ****   {
 329:Core/Src/main.c ****     Error_Handler();
 330:Core/Src/main.c ****   }
 331:Core/Src/main.c ****   if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
 332:Core/Src/main.c ****   {
 333:Core/Src/main.c ****     Error_Handler();
 334:Core/Src/main.c ****   }
 335:Core/Src/main.c ****   /* USER CODE BEGIN USART1_Init 2 */
 336:Core/Src/main.c **** 
 337:Core/Src/main.c ****   /* USER CODE END USART1_Init 2 */
 338:Core/Src/main.c **** 
 339:Core/Src/main.c **** }
 340:Core/Src/main.c **** 
 341:Core/Src/main.c **** /**
 342:Core/Src/main.c ****   * @brief USART2 Initialization Function
 343:Core/Src/main.c ****   * @param None
 344:Core/Src/main.c ****   * @retval None
 345:Core/Src/main.c ****   */
 346:Core/Src/main.c **** static void MX_USART2_UART_Init(void)
 347:Core/Src/main.c **** {
 348:Core/Src/main.c **** 
 349:Core/Src/main.c ****   /* USER CODE BEGIN USART2_Init 0 */
 350:Core/Src/main.c **** 
 351:Core/Src/main.c ****   /* USER CODE END USART2_Init 0 */
 352:Core/Src/main.c **** 
 353:Core/Src/main.c ****   /* USER CODE BEGIN USART2_Init 1 */
 354:Core/Src/main.c **** 
 355:Core/Src/main.c ****   /* USER CODE END USART2_Init 1 */
 356:Core/Src/main.c ****   huart2.Instance = USART2;
 357:Core/Src/main.c ****   huart2.Init.BaudRate = 9600;
 358:Core/Src/main.c ****   huart2.Init.WordLength = UART_WORDLENGTH_8B;
 359:Core/Src/main.c ****   huart2.Init.StopBits = UART_STOPBITS_1;
 360:Core/Src/main.c ****   huart2.Init.Parity = UART_PARITY_NONE;
 361:Core/Src/main.c ****   huart2.Init.Mode = UART_MODE_TX_RX;
 362:Core/Src/main.c ****   huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 363:Core/Src/main.c ****   huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 364:Core/Src/main.c ****   huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 365:Core/Src/main.c ****   huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 366:Core/Src/main.c ****   huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 367:Core/Src/main.c ****   if (HAL_UART_Init(&huart2) != HAL_OK)
 368:Core/Src/main.c ****   {
 369:Core/Src/main.c ****     Error_Handler();
 370:Core/Src/main.c ****   }
 371:Core/Src/main.c ****   if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
 372:Core/Src/main.c ****   {
 373:Core/Src/main.c ****     Error_Handler();
 374:Core/Src/main.c ****   }
ARM GAS  /tmp/ccrhJjjK.s 			page 8


 375:Core/Src/main.c ****   if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
 376:Core/Src/main.c ****   {
 377:Core/Src/main.c ****     Error_Handler();
 378:Core/Src/main.c ****   }
 379:Core/Src/main.c ****   if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
 380:Core/Src/main.c ****   {
 381:Core/Src/main.c ****     Error_Handler();
 382:Core/Src/main.c ****   }
 383:Core/Src/main.c ****   /* USER CODE BEGIN USART2_Init 2 */
 384:Core/Src/main.c **** 
 385:Core/Src/main.c ****   /* USER CODE END USART2_Init 2 */
 386:Core/Src/main.c **** 
 387:Core/Src/main.c **** }
 388:Core/Src/main.c **** 
 389:Core/Src/main.c **** /**
 390:Core/Src/main.c ****   * @brief TIM7 Initialization Function
 391:Core/Src/main.c ****   * @param None
 392:Core/Src/main.c ****   * @retval None
 393:Core/Src/main.c ****   */
 394:Core/Src/main.c **** static void MX_TIM7_Init(void)
 395:Core/Src/main.c **** {
 396:Core/Src/main.c **** 
 397:Core/Src/main.c ****   /* USER CODE BEGIN TIM7_Init 0 */
 398:Core/Src/main.c **** 
 399:Core/Src/main.c ****   /* USER CODE END TIM7_Init 0 */
 400:Core/Src/main.c **** 
 401:Core/Src/main.c ****   TIM_MasterConfigTypeDef sMasterConfig = {0};
 402:Core/Src/main.c **** 
 403:Core/Src/main.c ****   /* USER CODE BEGIN TIM7_Init 1 */
 404:Core/Src/main.c **** 
 405:Core/Src/main.c ****   /* USER CODE END TIM7_Init 1 */
 406:Core/Src/main.c ****   htim7.Instance = TIM7;
 407:Core/Src/main.c ****   htim7.Init.Prescaler = 16799;
 408:Core/Src/main.c ****   htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
 409:Core/Src/main.c ****   htim7.Init.Period = 9999;
 410:Core/Src/main.c ****   htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 411:Core/Src/main.c ****   if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
 412:Core/Src/main.c ****   {
 413:Core/Src/main.c ****     Error_Handler();
 414:Core/Src/main.c ****   }
 415:Core/Src/main.c ****   sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 416:Core/Src/main.c ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 417:Core/Src/main.c ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
 418:Core/Src/main.c ****   {
 419:Core/Src/main.c ****     Error_Handler();
 420:Core/Src/main.c ****   }
 421:Core/Src/main.c ****   /* USER CODE BEGIN TIM7_Init 2 */
 422:Core/Src/main.c **** 
 423:Core/Src/main.c ****   /* USER CODE END TIM7_Init 2 */
 424:Core/Src/main.c **** 
 425:Core/Src/main.c **** }
 426:Core/Src/main.c **** 
 427:Core/Src/main.c **** /**
 428:Core/Src/main.c ****   * Enable DMA controller clock
 429:Core/Src/main.c ****   */
 430:Core/Src/main.c **** static void MX_DMA_Init(void)
 431:Core/Src/main.c **** {
ARM GAS  /tmp/ccrhJjjK.s 			page 9


 432:Core/Src/main.c **** 
 433:Core/Src/main.c ****   /* DMA controller clock enable */
 434:Core/Src/main.c ****   __HAL_RCC_DMAMUX1_CLK_ENABLE();
 435:Core/Src/main.c ****   __HAL_RCC_DMA1_CLK_ENABLE();
 436:Core/Src/main.c **** 
 437:Core/Src/main.c ****   /* DMA interrupt init */
 438:Core/Src/main.c ****   /* DMA1_Channel1_IRQn interrupt configuration */
 439:Core/Src/main.c ****   HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 440:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 441:Core/Src/main.c ****   /* DMA1_Channel5_IRQn interrupt configuration */
 442:Core/Src/main.c ****   HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
 443:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 444:Core/Src/main.c **** 
 445:Core/Src/main.c **** }
 446:Core/Src/main.c **** 
 447:Core/Src/main.c **** /**
 448:Core/Src/main.c ****   * @brief GPIO Initialization Function
 449:Core/Src/main.c ****   * @param None
 450:Core/Src/main.c ****   * @retval None
 451:Core/Src/main.c ****   */
 452:Core/Src/main.c **** static void MX_GPIO_Init(void)
 453:Core/Src/main.c **** {
  27              		.loc 1 453 0
  28              		.cfi_startproc
  29              		@ args = 0, pretend = 0, frame = 32
  30              		@ frame_needed = 0, uses_anonymous_args = 0
  31 0000 30B5     		push	{r4, r5, lr}
  32              	.LCFI0:
  33              		.cfi_def_cfa_offset 12
  34              		.cfi_offset 4, -12
  35              		.cfi_offset 5, -8
  36              		.cfi_offset 14, -4
  37 0002 89B0     		sub	sp, sp, #36
  38              	.LCFI1:
  39              		.cfi_def_cfa_offset 48
 454:Core/Src/main.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
  40              		.loc 1 454 0
  41 0004 0024     		movs	r4, #0
  42 0006 0394     		str	r4, [sp, #12]
  43 0008 0494     		str	r4, [sp, #16]
  44 000a 0594     		str	r4, [sp, #20]
  45 000c 0694     		str	r4, [sp, #24]
  46 000e 0794     		str	r4, [sp, #28]
  47              	.LBB4:
 455:Core/Src/main.c **** 
 456:Core/Src/main.c ****   /* GPIO Ports Clock Enable */
 457:Core/Src/main.c ****   __HAL_RCC_GPIOF_CLK_ENABLE();
  48              		.loc 1 457 0
  49 0010 174B     		ldr	r3, .L3
  50 0012 DA6C     		ldr	r2, [r3, #76]
  51 0014 42F02002 		orr	r2, r2, #32
  52 0018 DA64     		str	r2, [r3, #76]
  53 001a DA6C     		ldr	r2, [r3, #76]
  54 001c 02F02002 		and	r2, r2, #32
  55 0020 0092     		str	r2, [sp]
  56 0022 009A     		ldr	r2, [sp]
  57              	.LBE4:
ARM GAS  /tmp/ccrhJjjK.s 			page 10


  58              	.LBB5:
 458:Core/Src/main.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
  59              		.loc 1 458 0
  60 0024 DA6C     		ldr	r2, [r3, #76]
  61 0026 42F00102 		orr	r2, r2, #1
  62 002a DA64     		str	r2, [r3, #76]
  63 002c DA6C     		ldr	r2, [r3, #76]
  64 002e 02F00102 		and	r2, r2, #1
  65 0032 0192     		str	r2, [sp, #4]
  66 0034 019A     		ldr	r2, [sp, #4]
  67              	.LBE5:
  68              	.LBB6:
 459:Core/Src/main.c ****   __HAL_RCC_GPIOB_CLK_ENABLE();
  69              		.loc 1 459 0
  70 0036 DA6C     		ldr	r2, [r3, #76]
  71 0038 42F00202 		orr	r2, r2, #2
  72 003c DA64     		str	r2, [r3, #76]
  73 003e DB6C     		ldr	r3, [r3, #76]
  74 0040 03F00203 		and	r3, r3, #2
  75 0044 0293     		str	r3, [sp, #8]
  76 0046 029B     		ldr	r3, [sp, #8]
  77              	.LBE6:
 460:Core/Src/main.c **** 
 461:Core/Src/main.c ****   /*Configure GPIO pin Output Level */
 462:Core/Src/main.c ****   HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
  78              		.loc 1 462 0
  79 0048 0A4D     		ldr	r5, .L3+4
  80 004a 2246     		mov	r2, r4
  81 004c 4FF48071 		mov	r1, #256
  82 0050 2846     		mov	r0, r5
  83 0052 FFF7FEFF 		bl	HAL_GPIO_WritePin
  84              	.LVL0:
 463:Core/Src/main.c **** 
 464:Core/Src/main.c ****   /*Configure GPIO pin : LD2_Pin */
 465:Core/Src/main.c ****   GPIO_InitStruct.Pin = LD2_Pin;
  85              		.loc 1 465 0
  86 0056 4FF48073 		mov	r3, #256
  87 005a 0393     		str	r3, [sp, #12]
 466:Core/Src/main.c ****   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  88              		.loc 1 466 0
  89 005c 0123     		movs	r3, #1
  90 005e 0493     		str	r3, [sp, #16]
 467:Core/Src/main.c ****   GPIO_InitStruct.Pull = GPIO_NOPULL;
  91              		.loc 1 467 0
  92 0060 0594     		str	r4, [sp, #20]
 468:Core/Src/main.c ****   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  93              		.loc 1 468 0
  94 0062 0694     		str	r4, [sp, #24]
 469:Core/Src/main.c ****   HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
  95              		.loc 1 469 0
  96 0064 03A9     		add	r1, sp, #12
  97 0066 2846     		mov	r0, r5
  98 0068 FFF7FEFF 		bl	HAL_GPIO_Init
  99              	.LVL1:
 470:Core/Src/main.c **** 
 471:Core/Src/main.c **** }
 100              		.loc 1 471 0
ARM GAS  /tmp/ccrhJjjK.s 			page 11


 101 006c 09B0     		add	sp, sp, #36
 102              	.LCFI2:
 103              		.cfi_def_cfa_offset 12
 104              		@ sp needed
 105 006e 30BD     		pop	{r4, r5, pc}
 106              	.L4:
 107              		.align	2
 108              	.L3:
 109 0070 00100240 		.word	1073876992
 110 0074 00040048 		.word	1207960576
 111              		.cfi_endproc
 112              	.LFE148:
 114              		.section	.text.MX_DMA_Init,"ax",%progbits
 115              		.align	1
 116              		.syntax unified
 117              		.thumb
 118              		.thumb_func
 119              		.fpu fpv4-sp-d16
 121              	MX_DMA_Init:
 122              	.LFB147:
 431:Core/Src/main.c **** 
 123              		.loc 1 431 0
 124              		.cfi_startproc
 125              		@ args = 0, pretend = 0, frame = 8
 126              		@ frame_needed = 0, uses_anonymous_args = 0
 127 0000 00B5     		push	{lr}
 128              	.LCFI3:
 129              		.cfi_def_cfa_offset 4
 130              		.cfi_offset 14, -4
 131 0002 83B0     		sub	sp, sp, #12
 132              	.LCFI4:
 133              		.cfi_def_cfa_offset 16
 134              	.LBB7:
 434:Core/Src/main.c ****   __HAL_RCC_DMA1_CLK_ENABLE();
 135              		.loc 1 434 0
 136 0004 124B     		ldr	r3, .L7
 137 0006 9A6C     		ldr	r2, [r3, #72]
 138 0008 42F00402 		orr	r2, r2, #4
 139 000c 9A64     		str	r2, [r3, #72]
 140 000e 9A6C     		ldr	r2, [r3, #72]
 141 0010 02F00402 		and	r2, r2, #4
 142 0014 0092     		str	r2, [sp]
 143 0016 009A     		ldr	r2, [sp]
 144              	.LBE7:
 145              	.LBB8:
 435:Core/Src/main.c **** 
 146              		.loc 1 435 0
 147 0018 9A6C     		ldr	r2, [r3, #72]
 148 001a 42F00102 		orr	r2, r2, #1
 149 001e 9A64     		str	r2, [r3, #72]
 150 0020 9B6C     		ldr	r3, [r3, #72]
 151 0022 03F00103 		and	r3, r3, #1
 152 0026 0193     		str	r3, [sp, #4]
 153 0028 019B     		ldr	r3, [sp, #4]
 154              	.LBE8:
 439:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 155              		.loc 1 439 0
ARM GAS  /tmp/ccrhJjjK.s 			page 12


 156 002a 0022     		movs	r2, #0
 157 002c 1146     		mov	r1, r2
 158 002e 0B20     		movs	r0, #11
 159 0030 FFF7FEFF 		bl	HAL_NVIC_SetPriority
 160              	.LVL2:
 440:Core/Src/main.c ****   /* DMA1_Channel5_IRQn interrupt configuration */
 161              		.loc 1 440 0
 162 0034 0B20     		movs	r0, #11
 163 0036 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
 164              	.LVL3:
 442:Core/Src/main.c ****   HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 165              		.loc 1 442 0
 166 003a 0022     		movs	r2, #0
 167 003c 1146     		mov	r1, r2
 168 003e 0F20     		movs	r0, #15
 169 0040 FFF7FEFF 		bl	HAL_NVIC_SetPriority
 170              	.LVL4:
 443:Core/Src/main.c **** 
 171              		.loc 1 443 0
 172 0044 0F20     		movs	r0, #15
 173 0046 FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
 174              	.LVL5:
 445:Core/Src/main.c **** 
 175              		.loc 1 445 0
 176 004a 03B0     		add	sp, sp, #12
 177              	.LCFI5:
 178              		.cfi_def_cfa_offset 4
 179              		@ sp needed
 180 004c 5DF804FB 		ldr	pc, [sp], #4
 181              	.L8:
 182              		.align	2
 183              	.L7:
 184 0050 00100240 		.word	1073876992
 185              		.cfi_endproc
 186              	.LFE147:
 188              		.section	.text.HAL_UART_RxCpltCallback,"ax",%progbits
 189              		.align	1
 190              		.global	HAL_UART_RxCpltCallback
 191              		.syntax unified
 192              		.thumb
 193              		.thumb_func
 194              		.fpu fpv4-sp-d16
 196              	HAL_UART_RxCpltCallback:
 197              	.LFB135:
  73:Core/Src/main.c ****         if (huart == &huart1){
 198              		.loc 1 73 0
 199              		.cfi_startproc
 200              		@ args = 0, pretend = 0, frame = 0
 201              		@ frame_needed = 0, uses_anonymous_args = 0
 202              	.LVL6:
 203 0000 38B5     		push	{r3, r4, r5, lr}
 204              	.LCFI6:
 205              		.cfi_def_cfa_offset 16
 206              		.cfi_offset 3, -16
 207              		.cfi_offset 4, -12
 208              		.cfi_offset 5, -8
 209              		.cfi_offset 14, -4
ARM GAS  /tmp/ccrhJjjK.s 			page 13


 210 0002 0446     		mov	r4, r0
  74:Core/Src/main.c ****                 enqueue_cmd(uart1_rx_buf[0]);
 211              		.loc 1 74 0
 212 0004 134B     		ldr	r3, .L17
 213 0006 9842     		cmp	r0, r3
 214 0008 06D0     		beq	.L14
 215              	.LVL7:
 216              	.L10:
  79:Core/Src/main.c ****                 enqueue_cmd(uart2_rx_buf[0]);
 217              		.loc 1 79 0
 218 000a 134B     		ldr	r3, .L17+4
 219 000c 9C42     		cmp	r4, r3
 220 000e 0DD0     		beq	.L15
 221              	.L11:
  84:Core/Src/main.c ****                 enqueue_nmea(uart3_rx_buf[0]);
 222              		.loc 1 84 0
 223 0010 124B     		ldr	r3, .L17+8
 224 0012 9C42     		cmp	r4, r3
 225 0014 14D0     		beq	.L16
 226              	.LVL8:
 227              	.L9:
  89:Core/Src/main.c **** 
 228              		.loc 1 89 0
 229 0016 38BD     		pop	{r3, r4, r5, pc}
 230              	.LVL9:
 231              	.L14:
  75:Core/Src/main.c ****                 HAL_UART_Receive_IT(&huart1, uart1_rx_buf, 1);
 232              		.loc 1 75 0
 233 0018 114D     		ldr	r5, .L17+12
 234 001a 2878     		ldrb	r0, [r5]	@ zero_extendqisi2
 235              	.LVL10:
 236 001c FFF7FEFF 		bl	enqueue_cmd
 237              	.LVL11:
  76:Core/Src/main.c ****         }
 238              		.loc 1 76 0
 239 0020 0122     		movs	r2, #1
 240 0022 2946     		mov	r1, r5
 241 0024 0B48     		ldr	r0, .L17
 242 0026 FFF7FEFF 		bl	HAL_UART_Receive_IT
 243              	.LVL12:
 244 002a EEE7     		b	.L10
 245              	.L15:
  80:Core/Src/main.c ****                 HAL_UART_Receive_IT(&huart2, uart2_rx_buf, 1);
 246              		.loc 1 80 0
 247 002c 0D4D     		ldr	r5, .L17+16
 248 002e 2878     		ldrb	r0, [r5]	@ zero_extendqisi2
 249 0030 FFF7FEFF 		bl	enqueue_cmd
 250              	.LVL13:
  81:Core/Src/main.c ****         }
 251              		.loc 1 81 0
 252 0034 0122     		movs	r2, #1
 253 0036 2946     		mov	r1, r5
 254 0038 0748     		ldr	r0, .L17+4
 255 003a FFF7FEFF 		bl	HAL_UART_Receive_IT
 256              	.LVL14:
 257 003e E7E7     		b	.L11
 258              	.L16:
ARM GAS  /tmp/ccrhJjjK.s 			page 14


  85:Core/Src/main.c ****                 HAL_UART_Receive_IT(&hlpuart1, uart3_rx_buf, 1);
 259              		.loc 1 85 0
 260 0040 094C     		ldr	r4, .L17+20
 261              	.LVL15:
 262 0042 2078     		ldrb	r0, [r4]	@ zero_extendqisi2
 263 0044 FFF7FEFF 		bl	enqueue_nmea
 264              	.LVL16:
  86:Core/Src/main.c ****         }
 265              		.loc 1 86 0
 266 0048 0122     		movs	r2, #1
 267 004a 2146     		mov	r1, r4
 268 004c 0348     		ldr	r0, .L17+8
 269 004e FFF7FEFF 		bl	HAL_UART_Receive_IT
 270              	.LVL17:
  89:Core/Src/main.c **** 
 271              		.loc 1 89 0
 272 0052 E0E7     		b	.L9
 273              	.L18:
 274              		.align	2
 275              	.L17:
 276 0054 00000000 		.word	huart1
 277 0058 00000000 		.word	huart2
 278 005c 00000000 		.word	hlpuart1
 279 0060 00000000 		.word	uart1_rx_buf
 280 0064 00000000 		.word	uart2_rx_buf
 281 0068 00000000 		.word	uart3_rx_buf
 282              		.cfi_endproc
 283              	.LFE135:
 285              		.section	.text._write,"ax",%progbits
 286              		.align	1
 287              		.global	_write
 288              		.syntax unified
 289              		.thumb
 290              		.thumb_func
 291              		.fpu fpv4-sp-d16
 293              	_write:
 294              	.LFB136:
  91:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart1, ptr, len);
 295              		.loc 1 91 0
 296              		.cfi_startproc
 297              		@ args = 0, pretend = 0, frame = 0
 298              		@ frame_needed = 0, uses_anonymous_args = 0
 299              	.LVL18:
 300 0000 10B5     		push	{r4, lr}
 301              	.LCFI7:
 302              		.cfi_def_cfa_offset 8
 303              		.cfi_offset 4, -8
 304              		.cfi_offset 14, -4
 305 0002 1446     		mov	r4, r2
  92:Core/Src/main.c ****         return len;
 306              		.loc 1 92 0
 307 0004 92B2     		uxth	r2, r2
 308              	.LVL19:
 309 0006 0248     		ldr	r0, .L21
 310              	.LVL20:
 311 0008 FFF7FEFF 		bl	HAL_UART_Transmit_DMA
 312              	.LVL21:
ARM GAS  /tmp/ccrhJjjK.s 			page 15


  94:Core/Src/main.c **** 
 313              		.loc 1 94 0
 314 000c 2046     		mov	r0, r4
 315 000e 10BD     		pop	{r4, pc}
 316              	.LVL22:
 317              	.L22:
 318              		.align	2
 319              	.L21:
 320 0010 00000000 		.word	huart1
 321              		.cfi_endproc
 322              	.LFE136:
 324              		.section	.text.display_write,"ax",%progbits
 325              		.align	1
 326              		.global	display_write
 327              		.syntax unified
 328              		.thumb
 329              		.thumb_func
 330              		.fpu fpv4-sp-d16
 332              	display_write:
 333              	.LFB137:
  96:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart1, ptr, len);
 334              		.loc 1 96 0
 335              		.cfi_startproc
 336              		@ args = 0, pretend = 0, frame = 0
 337              		@ frame_needed = 0, uses_anonymous_args = 0
 338              	.LVL23:
 339 0000 10B5     		push	{r4, lr}
 340              	.LCFI8:
 341              		.cfi_def_cfa_offset 8
 342              		.cfi_offset 4, -8
 343              		.cfi_offset 14, -4
 344 0002 0C46     		mov	r4, r1
  97:Core/Src/main.c ****         return len;
 345              		.loc 1 97 0
 346 0004 8AB2     		uxth	r2, r1
 347 0006 0146     		mov	r1, r0
 348              	.LVL24:
 349 0008 0248     		ldr	r0, .L25
 350              	.LVL25:
 351 000a FFF7FEFF 		bl	HAL_UART_Transmit_DMA
 352              	.LVL26:
  99:Core/Src/main.c **** 
 353              		.loc 1 99 0
 354 000e 2046     		mov	r0, r4
 355 0010 10BD     		pop	{r4, pc}
 356              	.LVL27:
 357              	.L26:
 358 0012 00BF     		.align	2
 359              	.L25:
 360 0014 00000000 		.word	huart1
 361              		.cfi_endproc
 362              	.LFE137:
 364              		.section	.text.display_write2,"ax",%progbits
 365              		.align	1
 366              		.global	display_write2
 367              		.syntax unified
 368              		.thumb
ARM GAS  /tmp/ccrhJjjK.s 			page 16


 369              		.thumb_func
 370              		.fpu fpv4-sp-d16
 372              	display_write2:
 373              	.LFB138:
 101:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart1, ptr, strlen(ptr));
 374              		.loc 1 101 0
 375              		.cfi_startproc
 376              		@ args = 0, pretend = 0, frame = 0
 377              		@ frame_needed = 0, uses_anonymous_args = 0
 378              	.LVL28:
 379 0000 10B5     		push	{r4, lr}
 380              	.LCFI9:
 381              		.cfi_def_cfa_offset 8
 382              		.cfi_offset 4, -8
 383              		.cfi_offset 14, -4
 384 0002 0446     		mov	r4, r0
 102:Core/Src/main.c **** }
 385              		.loc 1 102 0
 386 0004 FFF7FEFF 		bl	strlen
 387              	.LVL29:
 388 0008 82B2     		uxth	r2, r0
 389 000a 2146     		mov	r1, r4
 390 000c 0148     		ldr	r0, .L29
 391 000e FFF7FEFF 		bl	HAL_UART_Transmit_DMA
 392              	.LVL30:
 103:Core/Src/main.c **** 
 393              		.loc 1 103 0
 394 0012 10BD     		pop	{r4, pc}
 395              	.LVL31:
 396              	.L30:
 397              		.align	2
 398              	.L29:
 399 0014 00000000 		.word	huart1
 400              		.cfi_endproc
 401              	.LFE138:
 403              		.section	.text.radio_write,"ax",%progbits
 404              		.align	1
 405              		.global	radio_write
 406              		.syntax unified
 407              		.thumb
 408              		.thumb_func
 409              		.fpu fpv4-sp-d16
 411              	radio_write:
 412              	.LFB139:
 105:Core/Src/main.c ****         HAL_UART_Transmit_DMA(&huart2, ptr, strlen(ptr));
 413              		.loc 1 105 0
 414              		.cfi_startproc
 415              		@ args = 0, pretend = 0, frame = 0
 416              		@ frame_needed = 0, uses_anonymous_args = 0
 417              	.LVL32:
 418 0000 10B5     		push	{r4, lr}
 419              	.LCFI10:
 420              		.cfi_def_cfa_offset 8
 421              		.cfi_offset 4, -8
 422              		.cfi_offset 14, -4
 423 0002 0446     		mov	r4, r0
 106:Core/Src/main.c **** }
ARM GAS  /tmp/ccrhJjjK.s 			page 17


 424              		.loc 1 106 0
 425 0004 FFF7FEFF 		bl	strlen
 426              	.LVL33:
 427 0008 82B2     		uxth	r2, r0
 428 000a 2146     		mov	r1, r4
 429 000c 0148     		ldr	r0, .L33
 430 000e FFF7FEFF 		bl	HAL_UART_Transmit_DMA
 431              	.LVL34:
 107:Core/Src/main.c **** 
 432              		.loc 1 107 0
 433 0012 10BD     		pop	{r4, pc}
 434              	.LVL35:
 435              	.L34:
 436              		.align	2
 437              	.L33:
 438 0014 00000000 		.word	huart2
 439              		.cfi_endproc
 440              	.LFE139:
 442              		.section	.text.HAL_TIM_PeriodElapsedCallback,"ax",%progbits
 443              		.align	1
 444              		.global	HAL_TIM_PeriodElapsedCallback
 445              		.syntax unified
 446              		.thumb
 447              		.thumb_func
 448              		.fpu fpv4-sp-d16
 450              	HAL_TIM_PeriodElapsedCallback:
 451              	.LFB140:
 109:Core/Src/main.c ****     if (htim->Instance == TIM7){
 452              		.loc 1 109 0
 453              		.cfi_startproc
 454              		@ args = 0, pretend = 0, frame = 0
 455              		@ frame_needed = 0, uses_anonymous_args = 0
 456              		@ link register save eliminated.
 457              	.LVL36:
 110:Core/Src/main.c ****                 tick = 1;
 458              		.loc 1 110 0
 459 0000 0268     		ldr	r2, [r0]
 460 0002 044B     		ldr	r3, .L38
 461 0004 9A42     		cmp	r2, r3
 462 0006 00D0     		beq	.L37
 463              	.L35:
 113:Core/Src/main.c **** 
 464              		.loc 1 113 0
 465 0008 7047     		bx	lr
 466              	.L37:
 111:Core/Src/main.c ****     }
 467              		.loc 1 111 0
 468 000a 034B     		ldr	r3, .L38+4
 469 000c 0122     		movs	r2, #1
 470 000e 1A70     		strb	r2, [r3]
 113:Core/Src/main.c **** 
 471              		.loc 1 113 0
 472 0010 FAE7     		b	.L35
 473              	.L39:
 474 0012 00BF     		.align	2
 475              	.L38:
 476 0014 00140040 		.word	1073746944
ARM GAS  /tmp/ccrhJjjK.s 			page 18


 477 0018 00000000 		.word	tick
 478              		.cfi_endproc
 479              	.LFE140:
 481              		.section	.text.Error_Handler,"ax",%progbits
 482              		.align	1
 483              		.global	Error_Handler
 484              		.syntax unified
 485              		.thumb
 486              		.thumb_func
 487              		.fpu fpv4-sp-d16
 489              	Error_Handler:
 490              	.LFB149:
 472:Core/Src/main.c **** 
 473:Core/Src/main.c **** /* USER CODE BEGIN 4 */
 474:Core/Src/main.c **** 
 475:Core/Src/main.c **** /* USER CODE END 4 */
 476:Core/Src/main.c **** 
 477:Core/Src/main.c **** /**
 478:Core/Src/main.c ****   * @brief  This function is executed in case of error occurrence.
 479:Core/Src/main.c ****   * @retval None
 480:Core/Src/main.c ****   */
 481:Core/Src/main.c **** void Error_Handler(void)
 482:Core/Src/main.c **** {
 491              		.loc 1 482 0
 492              		.cfi_startproc
 493              		@ Volatile: function does not return.
 494              		@ args = 0, pretend = 0, frame = 0
 495              		@ frame_needed = 0, uses_anonymous_args = 0
 496              		@ link register save eliminated.
 497              	.LBB9:
 498              	.LBB10:
 499              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
ARM GAS  /tmp/ccrhJjjK.s 			page 19


  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
ARM GAS  /tmp/ccrhJjjK.s 			page 20


  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
ARM GAS  /tmp/ccrhJjjK.s 			page 21


 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
ARM GAS  /tmp/ccrhJjjK.s 			page 22


 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 500              		.loc 2 209 0
 501              		.syntax unified
 502              	@ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 503 0000 72B6     		cpsid i
 504              	@ 0 "" 2
 505              		.thumb
 506              		.syntax unified
 507              	.L41:
 508 0002 FEE7     		b	.L41
 509              	.LBE10:
 510              	.LBE9:
 511              		.cfi_endproc
 512              	.LFE149:
 514              		.section	.text.MX_USART1_UART_Init,"ax",%progbits
 515              		.align	1
 516              		.syntax unified
 517              		.thumb
 518              		.thumb_func
 519              		.fpu fpv4-sp-d16
 521              	MX_USART1_UART_Init:
 522              	.LFB144:
 299:Core/Src/main.c **** 
 523              		.loc 1 299 0
 524              		.cfi_startproc
 525              		@ args = 0, pretend = 0, frame = 0
 526              		@ frame_needed = 0, uses_anonymous_args = 0
 527 0000 08B5     		push	{r3, lr}
 528              	.LCFI11:
 529              		.cfi_def_cfa_offset 8
 530              		.cfi_offset 3, -8
 531              		.cfi_offset 14, -4
 308:Core/Src/main.c ****   huart1.Init.BaudRate = 115200;
 532              		.loc 1 308 0
 533 0002 1548     		ldr	r0, .L52
 534 0004 154B     		ldr	r3, .L52+4
 535 0006 0360     		str	r3, [r0]
 309:Core/Src/main.c ****   huart1.Init.WordLength = UART_WORDLENGTH_8B;
 536              		.loc 1 309 0
 537 0008 4FF4E133 		mov	r3, #115200
 538 000c 4360     		str	r3, [r0, #4]
 310:Core/Src/main.c ****   huart1.Init.StopBits = UART_STOPBITS_1;
 539              		.loc 1 310 0
 540 000e 0023     		movs	r3, #0
 541 0010 8360     		str	r3, [r0, #8]
ARM GAS  /tmp/ccrhJjjK.s 			page 23


 311:Core/Src/main.c ****   huart1.Init.Parity = UART_PARITY_NONE;
 542              		.loc 1 311 0
 543 0012 C360     		str	r3, [r0, #12]
 312:Core/Src/main.c ****   huart1.Init.Mode = UART_MODE_TX_RX;
 544              		.loc 1 312 0
 545 0014 0361     		str	r3, [r0, #16]
 313:Core/Src/main.c ****   huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 546              		.loc 1 313 0
 547 0016 0C22     		movs	r2, #12
 548 0018 4261     		str	r2, [r0, #20]
 314:Core/Src/main.c ****   huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 549              		.loc 1 314 0
 550 001a 8361     		str	r3, [r0, #24]
 315:Core/Src/main.c ****   huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 551              		.loc 1 315 0
 552 001c C361     		str	r3, [r0, #28]
 316:Core/Src/main.c ****   huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 553              		.loc 1 316 0
 554 001e 0362     		str	r3, [r0, #32]
 317:Core/Src/main.c ****   huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 555              		.loc 1 317 0
 556 0020 4362     		str	r3, [r0, #36]
 318:Core/Src/main.c ****   if (HAL_UART_Init(&huart1) != HAL_OK)
 557              		.loc 1 318 0
 558 0022 8362     		str	r3, [r0, #40]
 319:Core/Src/main.c ****   {
 559              		.loc 1 319 0
 560 0024 FFF7FEFF 		bl	HAL_UART_Init
 561              	.LVL37:
 562 0028 70B9     		cbnz	r0, .L48
 323:Core/Src/main.c ****   {
 563              		.loc 1 323 0
 564 002a 0021     		movs	r1, #0
 565 002c 0A48     		ldr	r0, .L52
 566 002e FFF7FEFF 		bl	HAL_UARTEx_SetTxFifoThreshold
 567              	.LVL38:
 568 0032 58B9     		cbnz	r0, .L49
 327:Core/Src/main.c ****   {
 569              		.loc 1 327 0
 570 0034 0021     		movs	r1, #0
 571 0036 0848     		ldr	r0, .L52
 572 0038 FFF7FEFF 		bl	HAL_UARTEx_SetRxFifoThreshold
 573              	.LVL39:
 574 003c 40B9     		cbnz	r0, .L50
 331:Core/Src/main.c ****   {
 575              		.loc 1 331 0
 576 003e 0648     		ldr	r0, .L52
 577 0040 FFF7FEFF 		bl	HAL_UARTEx_DisableFifoMode
 578              	.LVL40:
 579 0044 30B9     		cbnz	r0, .L51
 339:Core/Src/main.c **** 
 580              		.loc 1 339 0
 581 0046 08BD     		pop	{r3, pc}
 582              	.L48:
 321:Core/Src/main.c ****   }
 583              		.loc 1 321 0
 584 0048 FFF7FEFF 		bl	Error_Handler
ARM GAS  /tmp/ccrhJjjK.s 			page 24


 585              	.LVL41:
 586              	.L49:
 325:Core/Src/main.c ****   }
 587              		.loc 1 325 0
 588 004c FFF7FEFF 		bl	Error_Handler
 589              	.LVL42:
 590              	.L50:
 329:Core/Src/main.c ****   }
 591              		.loc 1 329 0
 592 0050 FFF7FEFF 		bl	Error_Handler
 593              	.LVL43:
 594              	.L51:
 333:Core/Src/main.c ****   }
 595              		.loc 1 333 0
 596 0054 FFF7FEFF 		bl	Error_Handler
 597              	.LVL44:
 598              	.L53:
 599              		.align	2
 600              	.L52:
 601 0058 00000000 		.word	huart1
 602 005c 00380140 		.word	1073821696
 603              		.cfi_endproc
 604              	.LFE144:
 606              		.section	.text.MX_USART2_UART_Init,"ax",%progbits
 607              		.align	1
 608              		.syntax unified
 609              		.thumb
 610              		.thumb_func
 611              		.fpu fpv4-sp-d16
 613              	MX_USART2_UART_Init:
 614              	.LFB145:
 347:Core/Src/main.c **** 
 615              		.loc 1 347 0
 616              		.cfi_startproc
 617              		@ args = 0, pretend = 0, frame = 0
 618              		@ frame_needed = 0, uses_anonymous_args = 0
 619 0000 08B5     		push	{r3, lr}
 620              	.LCFI12:
 621              		.cfi_def_cfa_offset 8
 622              		.cfi_offset 3, -8
 623              		.cfi_offset 14, -4
 356:Core/Src/main.c ****   huart2.Init.BaudRate = 9600;
 624              		.loc 1 356 0
 625 0002 1548     		ldr	r0, .L64
 626 0004 154B     		ldr	r3, .L64+4
 627 0006 0360     		str	r3, [r0]
 357:Core/Src/main.c ****   huart2.Init.WordLength = UART_WORDLENGTH_8B;
 628              		.loc 1 357 0
 629 0008 4FF41653 		mov	r3, #9600
 630 000c 4360     		str	r3, [r0, #4]
 358:Core/Src/main.c ****   huart2.Init.StopBits = UART_STOPBITS_1;
 631              		.loc 1 358 0
 632 000e 0023     		movs	r3, #0
 633 0010 8360     		str	r3, [r0, #8]
 359:Core/Src/main.c ****   huart2.Init.Parity = UART_PARITY_NONE;
 634              		.loc 1 359 0
 635 0012 C360     		str	r3, [r0, #12]
ARM GAS  /tmp/ccrhJjjK.s 			page 25


 360:Core/Src/main.c ****   huart2.Init.Mode = UART_MODE_TX_RX;
 636              		.loc 1 360 0
 637 0014 0361     		str	r3, [r0, #16]
 361:Core/Src/main.c ****   huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 638              		.loc 1 361 0
 639 0016 0C22     		movs	r2, #12
 640 0018 4261     		str	r2, [r0, #20]
 362:Core/Src/main.c ****   huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 641              		.loc 1 362 0
 642 001a 8361     		str	r3, [r0, #24]
 363:Core/Src/main.c ****   huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 643              		.loc 1 363 0
 644 001c C361     		str	r3, [r0, #28]
 364:Core/Src/main.c ****   huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
 645              		.loc 1 364 0
 646 001e 0362     		str	r3, [r0, #32]
 365:Core/Src/main.c ****   huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 647              		.loc 1 365 0
 648 0020 4362     		str	r3, [r0, #36]
 366:Core/Src/main.c ****   if (HAL_UART_Init(&huart2) != HAL_OK)
 649              		.loc 1 366 0
 650 0022 8362     		str	r3, [r0, #40]
 367:Core/Src/main.c ****   {
 651              		.loc 1 367 0
 652 0024 FFF7FEFF 		bl	HAL_UART_Init
 653              	.LVL45:
 654 0028 70B9     		cbnz	r0, .L60
 371:Core/Src/main.c ****   {
 655              		.loc 1 371 0
 656 002a 0021     		movs	r1, #0
 657 002c 0A48     		ldr	r0, .L64
 658 002e FFF7FEFF 		bl	HAL_UARTEx_SetTxFifoThreshold
 659              	.LVL46:
 660 0032 58B9     		cbnz	r0, .L61
 375:Core/Src/main.c ****   {
 661              		.loc 1 375 0
 662 0034 0021     		movs	r1, #0
 663 0036 0848     		ldr	r0, .L64
 664 0038 FFF7FEFF 		bl	HAL_UARTEx_SetRxFifoThreshold
 665              	.LVL47:
 666 003c 40B9     		cbnz	r0, .L62
 379:Core/Src/main.c ****   {
 667              		.loc 1 379 0
 668 003e 0648     		ldr	r0, .L64
 669 0040 FFF7FEFF 		bl	HAL_UARTEx_DisableFifoMode
 670              	.LVL48:
 671 0044 30B9     		cbnz	r0, .L63
 387:Core/Src/main.c **** 
 672              		.loc 1 387 0
 673 0046 08BD     		pop	{r3, pc}
 674              	.L60:
 369:Core/Src/main.c ****   }
 675              		.loc 1 369 0
 676 0048 FFF7FEFF 		bl	Error_Handler
 677              	.LVL49:
 678              	.L61:
 373:Core/Src/main.c ****   }
ARM GAS  /tmp/ccrhJjjK.s 			page 26


 679              		.loc 1 373 0
 680 004c FFF7FEFF 		bl	Error_Handler
 681              	.LVL50:
 682              	.L62:
 377:Core/Src/main.c ****   }
 683              		.loc 1 377 0
 684 0050 FFF7FEFF 		bl	Error_Handler
 685              	.LVL51:
 686              	.L63:
 381:Core/Src/main.c ****   }
 687              		.loc 1 381 0
 688 0054 FFF7FEFF 		bl	Error_Handler
 689              	.LVL52:
 690              	.L65:
 691              		.align	2
 692              	.L64:
 693 0058 00000000 		.word	huart2
 694 005c 00440040 		.word	1073759232
 695              		.cfi_endproc
 696              	.LFE145:
 698              		.section	.text.MX_TIM7_Init,"ax",%progbits
 699              		.align	1
 700              		.syntax unified
 701              		.thumb
 702              		.thumb_func
 703              		.fpu fpv4-sp-d16
 705              	MX_TIM7_Init:
 706              	.LFB146:
 395:Core/Src/main.c **** 
 707              		.loc 1 395 0
 708              		.cfi_startproc
 709              		@ args = 0, pretend = 0, frame = 16
 710              		@ frame_needed = 0, uses_anonymous_args = 0
 711 0000 00B5     		push	{lr}
 712              	.LCFI13:
 713              		.cfi_def_cfa_offset 4
 714              		.cfi_offset 14, -4
 715 0002 85B0     		sub	sp, sp, #20
 716              	.LCFI14:
 717              		.cfi_def_cfa_offset 24
 401:Core/Src/main.c **** 
 718              		.loc 1 401 0
 719 0004 0023     		movs	r3, #0
 720 0006 0193     		str	r3, [sp, #4]
 721 0008 0293     		str	r3, [sp, #8]
 722 000a 0393     		str	r3, [sp, #12]
 406:Core/Src/main.c ****   htim7.Init.Prescaler = 16799;
 723              		.loc 1 406 0
 724 000c 0E48     		ldr	r0, .L72
 725 000e 0F4A     		ldr	r2, .L72+4
 726 0010 0260     		str	r2, [r0]
 407:Core/Src/main.c ****   htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
 727              		.loc 1 407 0
 728 0012 44F29F12 		movw	r2, #16799
 729 0016 4260     		str	r2, [r0, #4]
 408:Core/Src/main.c ****   htim7.Init.Period = 9999;
 730              		.loc 1 408 0
ARM GAS  /tmp/ccrhJjjK.s 			page 27


 731 0018 8360     		str	r3, [r0, #8]
 409:Core/Src/main.c ****   htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 732              		.loc 1 409 0
 733 001a 42F20F72 		movw	r2, #9999
 734 001e C260     		str	r2, [r0, #12]
 410:Core/Src/main.c ****   if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
 735              		.loc 1 410 0
 736 0020 8361     		str	r3, [r0, #24]
 411:Core/Src/main.c ****   {
 737              		.loc 1 411 0
 738 0022 FFF7FEFF 		bl	HAL_TIM_Base_Init
 739              	.LVL53:
 740 0026 50B9     		cbnz	r0, .L70
 415:Core/Src/main.c ****   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 741              		.loc 1 415 0
 742 0028 0023     		movs	r3, #0
 743 002a 0193     		str	r3, [sp, #4]
 416:Core/Src/main.c ****   if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
 744              		.loc 1 416 0
 745 002c 0393     		str	r3, [sp, #12]
 417:Core/Src/main.c ****   {
 746              		.loc 1 417 0
 747 002e 01A9     		add	r1, sp, #4
 748 0030 0548     		ldr	r0, .L72
 749 0032 FFF7FEFF 		bl	HAL_TIMEx_MasterConfigSynchronization
 750              	.LVL54:
 751 0036 20B9     		cbnz	r0, .L71
 425:Core/Src/main.c **** 
 752              		.loc 1 425 0
 753 0038 05B0     		add	sp, sp, #20
 754              	.LCFI15:
 755              		.cfi_remember_state
 756              		.cfi_def_cfa_offset 4
 757              		@ sp needed
 758 003a 5DF804FB 		ldr	pc, [sp], #4
 759              	.L70:
 760              	.LCFI16:
 761              		.cfi_restore_state
 413:Core/Src/main.c ****   }
 762              		.loc 1 413 0
 763 003e FFF7FEFF 		bl	Error_Handler
 764              	.LVL55:
 765              	.L71:
 419:Core/Src/main.c ****   }
 766              		.loc 1 419 0
 767 0042 FFF7FEFF 		bl	Error_Handler
 768              	.LVL56:
 769              	.L73:
 770 0046 00BF     		.align	2
 771              	.L72:
 772 0048 00000000 		.word	htim7
 773 004c 00140040 		.word	1073746944
 774              		.cfi_endproc
 775              	.LFE146:
 777              		.section	.text.MX_LPUART1_UART_Init,"ax",%progbits
 778              		.align	1
 779              		.syntax unified
ARM GAS  /tmp/ccrhJjjK.s 			page 28


 780              		.thumb
 781              		.thumb_func
 782              		.fpu fpv4-sp-d16
 784              	MX_LPUART1_UART_Init:
 785              	.LFB143:
 252:Core/Src/main.c **** 
 786              		.loc 1 252 0
 787              		.cfi_startproc
 788              		@ args = 0, pretend = 0, frame = 0
 789              		@ frame_needed = 0, uses_anonymous_args = 0
 790 0000 08B5     		push	{r3, lr}
 791              	.LCFI17:
 792              		.cfi_def_cfa_offset 8
 793              		.cfi_offset 3, -8
 794              		.cfi_offset 14, -4
 261:Core/Src/main.c ****   hlpuart1.Init.BaudRate = 9600;
 795              		.loc 1 261 0
 796 0002 1548     		ldr	r0, .L84
 797 0004 154B     		ldr	r3, .L84+4
 798 0006 0360     		str	r3, [r0]
 262:Core/Src/main.c ****   hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
 799              		.loc 1 262 0
 800 0008 4FF41653 		mov	r3, #9600
 801 000c 4360     		str	r3, [r0, #4]
 263:Core/Src/main.c ****   hlpuart1.Init.StopBits = UART_STOPBITS_1;
 802              		.loc 1 263 0
 803 000e 0023     		movs	r3, #0
 804 0010 8360     		str	r3, [r0, #8]
 264:Core/Src/main.c ****   hlpuart1.Init.Parity = UART_PARITY_NONE;
 805              		.loc 1 264 0
 806 0012 C360     		str	r3, [r0, #12]
 265:Core/Src/main.c ****   hlpuart1.Init.Mode = UART_MODE_TX_RX;
 807              		.loc 1 265 0
 808 0014 0361     		str	r3, [r0, #16]
 266:Core/Src/main.c ****   hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 809              		.loc 1 266 0
 810 0016 0C22     		movs	r2, #12
 811 0018 4261     		str	r2, [r0, #20]
 267:Core/Src/main.c ****   hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 812              		.loc 1 267 0
 813 001a 8361     		str	r3, [r0, #24]
 268:Core/Src/main.c ****   hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV8;
 814              		.loc 1 268 0
 815 001c 0362     		str	r3, [r0, #32]
 269:Core/Src/main.c ****   hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 816              		.loc 1 269 0
 817 001e 0422     		movs	r2, #4
 818 0020 4262     		str	r2, [r0, #36]
 270:Core/Src/main.c ****   if (HAL_UART_Init(&hlpuart1) != HAL_OK)
 819              		.loc 1 270 0
 820 0022 8362     		str	r3, [r0, #40]
 271:Core/Src/main.c ****   {
 821              		.loc 1 271 0
 822 0024 FFF7FEFF 		bl	HAL_UART_Init
 823              	.LVL57:
 824 0028 70B9     		cbnz	r0, .L80
 275:Core/Src/main.c ****   {
ARM GAS  /tmp/ccrhJjjK.s 			page 29


 825              		.loc 1 275 0
 826 002a 0021     		movs	r1, #0
 827 002c 0A48     		ldr	r0, .L84
 828 002e FFF7FEFF 		bl	HAL_UARTEx_SetTxFifoThreshold
 829              	.LVL58:
 830 0032 58B9     		cbnz	r0, .L81
 279:Core/Src/main.c ****   {
 831              		.loc 1 279 0
 832 0034 0021     		movs	r1, #0
 833 0036 0848     		ldr	r0, .L84
 834 0038 FFF7FEFF 		bl	HAL_UARTEx_SetRxFifoThreshold
 835              	.LVL59:
 836 003c 40B9     		cbnz	r0, .L82
 283:Core/Src/main.c ****   {
 837              		.loc 1 283 0
 838 003e 0648     		ldr	r0, .L84
 839 0040 FFF7FEFF 		bl	HAL_UARTEx_DisableFifoMode
 840              	.LVL60:
 841 0044 30B9     		cbnz	r0, .L83
 291:Core/Src/main.c **** 
 842              		.loc 1 291 0
 843 0046 08BD     		pop	{r3, pc}
 844              	.L80:
 273:Core/Src/main.c ****   }
 845              		.loc 1 273 0
 846 0048 FFF7FEFF 		bl	Error_Handler
 847              	.LVL61:
 848              	.L81:
 277:Core/Src/main.c ****   }
 849              		.loc 1 277 0
 850 004c FFF7FEFF 		bl	Error_Handler
 851              	.LVL62:
 852              	.L82:
 281:Core/Src/main.c ****   }
 853              		.loc 1 281 0
 854 0050 FFF7FEFF 		bl	Error_Handler
 855              	.LVL63:
 856              	.L83:
 285:Core/Src/main.c ****   }
 857              		.loc 1 285 0
 858 0054 FFF7FEFF 		bl	Error_Handler
 859              	.LVL64:
 860              	.L85:
 861              		.align	2
 862              	.L84:
 863 0058 00000000 		.word	hlpuart1
 864 005c 00800040 		.word	1073774592
 865              		.cfi_endproc
 866              	.LFE143:
 868              		.section	.text.SystemClock_Config,"ax",%progbits
 869              		.align	1
 870              		.global	SystemClock_Config
 871              		.syntax unified
 872              		.thumb
 873              		.thumb_func
 874              		.fpu fpv4-sp-d16
 876              	SystemClock_Config:
ARM GAS  /tmp/ccrhJjjK.s 			page 30


 877              	.LFB142:
 194:Core/Src/main.c ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 878              		.loc 1 194 0
 879              		.cfi_startproc
 880              		@ args = 0, pretend = 0, frame = 144
 881              		@ frame_needed = 0, uses_anonymous_args = 0
 882 0000 10B5     		push	{r4, lr}
 883              	.LCFI18:
 884              		.cfi_def_cfa_offset 8
 885              		.cfi_offset 4, -8
 886              		.cfi_offset 14, -4
 887 0002 A4B0     		sub	sp, sp, #144
 888              	.LCFI19:
 889              		.cfi_def_cfa_offset 152
 195:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 890              		.loc 1 195 0
 891 0004 3822     		movs	r2, #56
 892 0006 0021     		movs	r1, #0
 893 0008 16A8     		add	r0, sp, #88
 894 000a FFF7FEFF 		bl	memset
 895              	.LVL65:
 196:Core/Src/main.c ****   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 896              		.loc 1 196 0
 897 000e 0024     		movs	r4, #0
 898 0010 1194     		str	r4, [sp, #68]
 899 0012 1294     		str	r4, [sp, #72]
 900 0014 1394     		str	r4, [sp, #76]
 901 0016 1494     		str	r4, [sp, #80]
 902 0018 1594     		str	r4, [sp, #84]
 197:Core/Src/main.c **** 
 903              		.loc 1 197 0
 904 001a 4422     		movs	r2, #68
 905 001c 2146     		mov	r1, r4
 906 001e 6846     		mov	r0, sp
 907 0020 FFF7FEFF 		bl	memset
 908              	.LVL66:
 201:Core/Src/main.c ****   /** Initializes the RCC Oscillators according to the specified parameters
 909              		.loc 1 201 0
 910 0024 2046     		mov	r0, r4
 911 0026 FFF7FEFF 		bl	HAL_PWREx_ControlVoltageScaling
 912              	.LVL67:
 205:Core/Src/main.c ****   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 913              		.loc 1 205 0
 914 002a 0322     		movs	r2, #3
 915 002c 1692     		str	r2, [sp, #88]
 206:Core/Src/main.c ****   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 916              		.loc 1 206 0
 917 002e 4FF48033 		mov	r3, #65536
 918 0032 1793     		str	r3, [sp, #92]
 207:Core/Src/main.c ****   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 919              		.loc 1 207 0
 920 0034 4FF48073 		mov	r3, #256
 921 0038 1993     		str	r3, [sp, #100]
 208:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 922              		.loc 1 208 0
 923 003a 4023     		movs	r3, #64
 924 003c 1A93     		str	r3, [sp, #104]
ARM GAS  /tmp/ccrhJjjK.s 			page 31


 209:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 925              		.loc 1 209 0
 926 003e 0223     		movs	r3, #2
 927 0040 1D93     		str	r3, [sp, #116]
 210:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
 928              		.loc 1 210 0
 929 0042 1E92     		str	r2, [sp, #120]
 211:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLN = 28;
 930              		.loc 1 211 0
 931 0044 1F93     		str	r3, [sp, #124]
 212:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 932              		.loc 1 212 0
 933 0046 1C22     		movs	r2, #28
 934 0048 2092     		str	r2, [sp, #128]
 213:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 935              		.loc 1 213 0
 936 004a 2193     		str	r3, [sp, #132]
 214:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 937              		.loc 1 214 0
 938 004c 2293     		str	r3, [sp, #136]
 215:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 939              		.loc 1 215 0
 940 004e 2393     		str	r3, [sp, #140]
 216:Core/Src/main.c ****   {
 941              		.loc 1 216 0
 942 0050 16A8     		add	r0, sp, #88
 943 0052 FFF7FEFF 		bl	HAL_RCC_OscConfig
 944              	.LVL68:
 945 0056 D0B9     		cbnz	r0, .L91
 222:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 946              		.loc 1 222 0
 947 0058 0F23     		movs	r3, #15
 948 005a 1193     		str	r3, [sp, #68]
 224:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 949              		.loc 1 224 0
 950 005c 0323     		movs	r3, #3
 951 005e 1293     		str	r3, [sp, #72]
 225:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 952              		.loc 1 225 0
 953 0060 0023     		movs	r3, #0
 954 0062 1393     		str	r3, [sp, #76]
 226:Core/Src/main.c ****   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 955              		.loc 1 226 0
 956 0064 1493     		str	r3, [sp, #80]
 227:Core/Src/main.c **** 
 957              		.loc 1 227 0
 958 0066 1593     		str	r3, [sp, #84]
 229:Core/Src/main.c ****   {
 959              		.loc 1 229 0
 960 0068 0421     		movs	r1, #4
 961 006a 11A8     		add	r0, sp, #68
 962 006c FFF7FEFF 		bl	HAL_RCC_ClockConfig
 963              	.LVL69:
 964 0070 78B9     		cbnz	r0, .L92
 235:Core/Src/main.c ****                               |RCC_PERIPHCLK_LPUART1;
 965              		.loc 1 235 0
 966 0072 2323     		movs	r3, #35
ARM GAS  /tmp/ccrhJjjK.s 			page 32


 967 0074 0093     		str	r3, [sp]
 237:Core/Src/main.c ****   PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
 968              		.loc 1 237 0
 969 0076 0023     		movs	r3, #0
 970 0078 0193     		str	r3, [sp, #4]
 238:Core/Src/main.c ****   PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
 971              		.loc 1 238 0
 972 007a 0293     		str	r3, [sp, #8]
 239:Core/Src/main.c ****   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 973              		.loc 1 239 0
 974 007c 4FF40063 		mov	r3, #2048
 975 0080 0593     		str	r3, [sp, #20]
 240:Core/Src/main.c ****   {
 976              		.loc 1 240 0
 977 0082 6846     		mov	r0, sp
 978 0084 FFF7FEFF 		bl	HAL_RCCEx_PeriphCLKConfig
 979              	.LVL70:
 980 0088 28B9     		cbnz	r0, .L93
 244:Core/Src/main.c **** 
 981              		.loc 1 244 0
 982 008a 24B0     		add	sp, sp, #144
 983              	.LCFI20:
 984              		.cfi_remember_state
 985              		.cfi_def_cfa_offset 8
 986              		@ sp needed
 987 008c 10BD     		pop	{r4, pc}
 988              	.L91:
 989              	.LCFI21:
 990              		.cfi_restore_state
 218:Core/Src/main.c ****   }
 991              		.loc 1 218 0
 992 008e FFF7FEFF 		bl	Error_Handler
 993              	.LVL71:
 994              	.L92:
 231:Core/Src/main.c ****   }
 995              		.loc 1 231 0
 996 0092 FFF7FEFF 		bl	Error_Handler
 997              	.LVL72:
 998              	.L93:
 242:Core/Src/main.c ****   }
 999              		.loc 1 242 0
 1000 0096 FFF7FEFF 		bl	Error_Handler
 1001              	.LVL73:
 1002              		.cfi_endproc
 1003              	.LFE142:
 1005              		.section	.text.main,"ax",%progbits
 1006              		.align	1
 1007              		.global	main
 1008              		.syntax unified
 1009              		.thumb
 1010              		.thumb_func
 1011              		.fpu fpv4-sp-d16
 1013              	main:
 1014              	.LFB141:
 122:Core/Src/main.c ****   /* USER CODE BEGIN 1 */
 1015              		.loc 1 122 0
 1016              		.cfi_startproc
ARM GAS  /tmp/ccrhJjjK.s 			page 33


 1017              		@ Volatile: function does not return.
 1018              		@ args = 0, pretend = 0, frame = 0
 1019              		@ frame_needed = 0, uses_anonymous_args = 0
 1020 0000 08B5     		push	{r3, lr}
 1021              	.LCFI22:
 1022              		.cfi_def_cfa_offset 8
 1023              		.cfi_offset 3, -8
 1024              		.cfi_offset 14, -4
 130:Core/Src/main.c **** 
 1025              		.loc 1 130 0
 1026 0002 FFF7FEFF 		bl	HAL_Init
 1027              	.LVL74:
 137:Core/Src/main.c **** 
 1028              		.loc 1 137 0
 1029 0006 FFF7FEFF 		bl	SystemClock_Config
 1030              	.LVL75:
 144:Core/Src/main.c ****   MX_DMA_Init();
 1031              		.loc 1 144 0
 1032 000a FFF7FEFF 		bl	MX_GPIO_Init
 1033              	.LVL76:
 145:Core/Src/main.c ****   MX_USART1_UART_Init();
 1034              		.loc 1 145 0
 1035 000e FFF7FEFF 		bl	MX_DMA_Init
 1036              	.LVL77:
 146:Core/Src/main.c ****   MX_USART2_UART_Init();
 1037              		.loc 1 146 0
 1038 0012 FFF7FEFF 		bl	MX_USART1_UART_Init
 1039              	.LVL78:
 147:Core/Src/main.c ****   MX_TIM7_Init();
 1040              		.loc 1 147 0
 1041 0016 FFF7FEFF 		bl	MX_USART2_UART_Init
 1042              	.LVL79:
 148:Core/Src/main.c ****   MX_LPUART1_UART_Init();
 1043              		.loc 1 148 0
 1044 001a FFF7FEFF 		bl	MX_TIM7_Init
 1045              	.LVL80:
 149:Core/Src/main.c ****   /* USER CODE BEGIN 2 */
 1046              		.loc 1 149 0
 1047 001e FFF7FEFF 		bl	MX_LPUART1_UART_Init
 1048              	.LVL81:
 151:Core/Src/main.c ****   HAL_UART_Receive_IT(&huart1, uart1_rx_buf, 1);
 1049              		.loc 1 151 0
 1050 0022 1848     		ldr	r0, .L99
 1051 0024 FFF7FEFF 		bl	HAL_TIM_Base_Start_IT
 1052              	.LVL82:
 152:Core/Src/main.c ****   HAL_UART_Receive_IT(&huart2, uart2_rx_buf, 1);
 1053              		.loc 1 152 0
 1054 0028 0122     		movs	r2, #1
 1055 002a 1749     		ldr	r1, .L99+4
 1056 002c 1748     		ldr	r0, .L99+8
 1057 002e FFF7FEFF 		bl	HAL_UART_Receive_IT
 1058              	.LVL83:
 153:Core/Src/main.c ****   HAL_UART_Receive_IT(&hlpuart1, uart3_rx_buf, 1);
 1059              		.loc 1 153 0
 1060 0032 0122     		movs	r2, #1
 1061 0034 1649     		ldr	r1, .L99+12
 1062 0036 1748     		ldr	r0, .L99+16
ARM GAS  /tmp/ccrhJjjK.s 			page 34


 1063 0038 FFF7FEFF 		bl	HAL_UART_Receive_IT
 1064              	.LVL84:
 154:Core/Src/main.c ****   /* USER CODE END 2 */
 1065              		.loc 1 154 0
 1066 003c 0122     		movs	r2, #1
 1067 003e 1649     		ldr	r1, .L99+20
 1068 0040 1648     		ldr	r0, .L99+24
 1069 0042 FFF7FEFF 		bl	HAL_UART_Receive_IT
 1070              	.LVL85:
 159:Core/Src/main.c ****   display_write2("start:");
 1071              		.loc 1 159 0
 1072 0046 6420     		movs	r0, #100
 1073 0048 FFF7FEFF 		bl	HAL_Delay
 1074              	.LVL86:
 160:Core/Src/main.c **** //  display_write2("\x1B[200,100q");
 1075              		.loc 1 160 0
 1076 004c 1448     		ldr	r0, .L99+28
 1077 004e FFF7FEFF 		bl	display_write2
 1078              	.LVL87:
 1079 0052 01E0     		b	.L95
 1080              	.L96:
 1081              	.LBB11:
 165:Core/Src/main.c ****         if(tick){
 1082              		.loc 1 165 0 discriminator 2
 1083 0054 FFF7FEFF 		bl	dequeue_cmd
 1084              	.LVL88:
 1085              	.L95:
 1086              	.LBE11:
 165:Core/Src/main.c ****         if(tick){
 1087              		.loc 1 165 0 is_stmt 0 discriminator 1
 1088 0058 124B     		ldr	r3, .L99+32
 1089 005a 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
 1090 005c 124B     		ldr	r3, .L99+36
 1091 005e 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 1092 0060 9A42     		cmp	r2, r3
 1093 0062 F7D1     		bne	.L96
 166:Core/Src/main.c **** 		HAL_GPIO_TogglePin(LD2_GPIO_Port, LD2_Pin); //Toggle LED
 1094              		.loc 1 166 0 is_stmt 1
 1095 0064 114B     		ldr	r3, .L99+40
 1096 0066 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 1097 0068 002B     		cmp	r3, #0
 1098 006a F5D0     		beq	.L95
 167:Core/Src/main.c **** //		display_write("a", 1);
 1099              		.loc 1 167 0
 1100 006c 4FF48071 		mov	r1, #256
 1101 0070 0F48     		ldr	r0, .L99+44
 1102 0072 FFF7FEFF 		bl	HAL_GPIO_TogglePin
 1103              	.LVL89:
 176:Core/Src/main.c **** //		radio_write("AT+DMOSETGROUP=0,446.8250,446.8250,0000,0,0000\r\n");
 1104              		.loc 1 176 0
 1105 0076 0F48     		ldr	r0, .L99+48
 1106 0078 FFF7FEFF 		bl	radio_write
 1107              	.LVL90:
 179:Core/Src/main.c ****          }
 1108              		.loc 1 179 0
 1109 007c 0B4B     		ldr	r3, .L99+40
 1110 007e 0022     		movs	r2, #0
ARM GAS  /tmp/ccrhJjjK.s 			page 35


 1111 0080 1A70     		strb	r2, [r3]
 1112 0082 E9E7     		b	.L95
 1113              	.L100:
 1114              		.align	2
 1115              	.L99:
 1116 0084 00000000 		.word	htim7
 1117 0088 00000000 		.word	uart1_rx_buf
 1118 008c 00000000 		.word	huart1
 1119 0090 00000000 		.word	uart2_rx_buf
 1120 0094 00000000 		.word	huart2
 1121 0098 00000000 		.word	uart3_rx_buf
 1122 009c 00000000 		.word	hlpuart1
 1123 00a0 00000000 		.word	.LC0
 1124 00a4 00000000 		.word	rx_cmd_rb_in_idx
 1125 00a8 00000000 		.word	rx_cmd_rb_out_idx
 1126 00ac 00000000 		.word	tick
 1127 00b0 00040048 		.word	1207960576
 1128 00b4 08000000 		.word	.LC1
 1129              		.cfi_endproc
 1130              	.LFE141:
 1132              		.comm	tick,1,1
 1133              		.comm	htim7,76,4
 1134              		.comm	hdma_usart2_tx,96,4
 1135              		.comm	hdma_usart1_tx,96,4
 1136              		.comm	huart2,144,4
 1137              		.comm	huart1,144,4
 1138              		.comm	hlpuart1,144,4
 1139              		.section	.rodata.main.str1.4,"aMS",%progbits,1
 1140              		.align	2
 1141              	.LC0:
 1142 0000 73746172 		.ascii	"start:\000"
 1142      743A00
 1143 0007 00       		.space	1
 1144              	.LC1:
 1145 0008 41542B44 		.ascii	"AT+DMOSETGROUP=1,433.5750,433.5750,0000,1,0000\015\012"
 1145      4D4F5345 
 1145      5447524F 
 1145      55503D31 
 1145      2C343333 
 1146 0038 00       		.ascii	"\000"
 1147              		.text
 1148              	.Letext0:
 1149              		.file 3 "/usr/include/newlib/machine/_default_types.h"
 1150              		.file 4 "/usr/include/newlib/sys/_stdint.h"
 1151              		.file 5 "Drivers/CMSIS/Include/core_cm4.h"
 1152              		.file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
 1153              		.file 7 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
 1154              		.file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
 1155              		.file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
 1156              		.file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"
 1157              		.file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
 1158              		.file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
 1159              		.file 13 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
 1160              		.file 14 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
 1161              		.file 15 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
 1162              		.file 16 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
 1163              		.file 17 "/usr/include/newlib/sys/lock.h"
ARM GAS  /tmp/ccrhJjjK.s 			page 36


 1164              		.file 18 "/usr/include/newlib/sys/_types.h"
 1165              		.file 19 "/usr/lib/gcc/arm-none-eabi/7.3.1/include/stddef.h"
 1166              		.file 20 "/usr/include/newlib/sys/reent.h"
 1167              		.file 21 "Core/Inc/palmipede.h"
 1168              		.file 22 "<built-in>"
 1169              		.file 23 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
 1170              		.file 24 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
 1171              		.file 25 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h"
 1172              		.file 26 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
ARM GAS  /tmp/ccrhJjjK.s 			page 37


DEFINED SYMBOLS
                            *ABS*:0000000000000000 main.c
     /tmp/ccrhJjjK.s:18     .text.MX_GPIO_Init:0000000000000000 $t
     /tmp/ccrhJjjK.s:24     .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init
     /tmp/ccrhJjjK.s:109    .text.MX_GPIO_Init:0000000000000070 $d
     /tmp/ccrhJjjK.s:115    .text.MX_DMA_Init:0000000000000000 $t
     /tmp/ccrhJjjK.s:121    .text.MX_DMA_Init:0000000000000000 MX_DMA_Init
     /tmp/ccrhJjjK.s:184    .text.MX_DMA_Init:0000000000000050 $d
     /tmp/ccrhJjjK.s:189    .text.HAL_UART_RxCpltCallback:0000000000000000 $t
     /tmp/ccrhJjjK.s:196    .text.HAL_UART_RxCpltCallback:0000000000000000 HAL_UART_RxCpltCallback
     /tmp/ccrhJjjK.s:276    .text.HAL_UART_RxCpltCallback:0000000000000054 $d
                            *COM*:0000000000000090 huart1
                            *COM*:0000000000000090 huart2
                            *COM*:0000000000000090 hlpuart1
     /tmp/ccrhJjjK.s:286    .text._write:0000000000000000 $t
     /tmp/ccrhJjjK.s:293    .text._write:0000000000000000 _write
     /tmp/ccrhJjjK.s:320    .text._write:0000000000000010 $d
     /tmp/ccrhJjjK.s:325    .text.display_write:0000000000000000 $t
     /tmp/ccrhJjjK.s:332    .text.display_write:0000000000000000 display_write
     /tmp/ccrhJjjK.s:360    .text.display_write:0000000000000014 $d
     /tmp/ccrhJjjK.s:365    .text.display_write2:0000000000000000 $t
     /tmp/ccrhJjjK.s:372    .text.display_write2:0000000000000000 display_write2
     /tmp/ccrhJjjK.s:399    .text.display_write2:0000000000000014 $d
     /tmp/ccrhJjjK.s:404    .text.radio_write:0000000000000000 $t
     /tmp/ccrhJjjK.s:411    .text.radio_write:0000000000000000 radio_write
     /tmp/ccrhJjjK.s:438    .text.radio_write:0000000000000014 $d
     /tmp/ccrhJjjK.s:443    .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 $t
     /tmp/ccrhJjjK.s:450    .text.HAL_TIM_PeriodElapsedCallback:0000000000000000 HAL_TIM_PeriodElapsedCallback
     /tmp/ccrhJjjK.s:476    .text.HAL_TIM_PeriodElapsedCallback:0000000000000014 $d
                            *COM*:0000000000000001 tick
     /tmp/ccrhJjjK.s:482    .text.Error_Handler:0000000000000000 $t
     /tmp/ccrhJjjK.s:489    .text.Error_Handler:0000000000000000 Error_Handler
     /tmp/ccrhJjjK.s:515    .text.MX_USART1_UART_Init:0000000000000000 $t
     /tmp/ccrhJjjK.s:521    .text.MX_USART1_UART_Init:0000000000000000 MX_USART1_UART_Init
     /tmp/ccrhJjjK.s:601    .text.MX_USART1_UART_Init:0000000000000058 $d
     /tmp/ccrhJjjK.s:607    .text.MX_USART2_UART_Init:0000000000000000 $t
     /tmp/ccrhJjjK.s:613    .text.MX_USART2_UART_Init:0000000000000000 MX_USART2_UART_Init
     /tmp/ccrhJjjK.s:693    .text.MX_USART2_UART_Init:0000000000000058 $d
     /tmp/ccrhJjjK.s:699    .text.MX_TIM7_Init:0000000000000000 $t
     /tmp/ccrhJjjK.s:705    .text.MX_TIM7_Init:0000000000000000 MX_TIM7_Init
     /tmp/ccrhJjjK.s:772    .text.MX_TIM7_Init:0000000000000048 $d
                            *COM*:000000000000004c htim7
     /tmp/ccrhJjjK.s:778    .text.MX_LPUART1_UART_Init:0000000000000000 $t
     /tmp/ccrhJjjK.s:784    .text.MX_LPUART1_UART_Init:0000000000000000 MX_LPUART1_UART_Init
     /tmp/ccrhJjjK.s:863    .text.MX_LPUART1_UART_Init:0000000000000058 $d
     /tmp/ccrhJjjK.s:869    .text.SystemClock_Config:0000000000000000 $t
     /tmp/ccrhJjjK.s:876    .text.SystemClock_Config:0000000000000000 SystemClock_Config
     /tmp/ccrhJjjK.s:1006   .text.main:0000000000000000 $t
     /tmp/ccrhJjjK.s:1013   .text.main:0000000000000000 main
     /tmp/ccrhJjjK.s:1116   .text.main:0000000000000084 $d
                            *COM*:0000000000000060 hdma_usart2_tx
                            *COM*:0000000000000060 hdma_usart1_tx
     /tmp/ccrhJjjK.s:1140   .rodata.main.str1.4:0000000000000000 $d

UNDEFINED SYMBOLS
HAL_GPIO_WritePin
HAL_GPIO_Init
ARM GAS  /tmp/ccrhJjjK.s 			page 38


HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
enqueue_cmd
HAL_UART_Receive_IT
enqueue_nmea
uart1_rx_buf
uart2_rx_buf
uart3_rx_buf
HAL_UART_Transmit_DMA
strlen
HAL_UART_Init
HAL_UARTEx_SetTxFifoThreshold
HAL_UARTEx_SetRxFifoThreshold
HAL_UARTEx_DisableFifoMode
HAL_TIM_Base_Init
HAL_TIMEx_MasterConfigSynchronization
memset
HAL_PWREx_ControlVoltageScaling
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
HAL_RCCEx_PeriphCLKConfig
HAL_Init
HAL_TIM_Base_Start_IT
HAL_Delay
dequeue_cmd
HAL_GPIO_TogglePin
rx_cmd_rb_in_idx
rx_cmd_rb_out_idx
