cesco/squeow
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Files
28b7af65b6b4b2a27e17d5cd0560fc94bdf146fe
squeow/squeow_sw/build/si5351.lst

1160 lines
47 KiB
Plaintext
Raw Normal View History

UI led
2025-06-28 00:58:29 +02:00
ARM GAS /tmp/cccZCQn9.s page 1
primo commit
2023-07-02 17:09:41 +02:00
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "si5351.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Src/si5351.c"
UI led
2025-06-28 00:58:29 +02:00
20 .section .text.CalcRegisters,"ax",%progbits
primo commit
2023-07-02 17:09:41 +02:00
21 .align 1
UI led
2025-06-28 00:58:29 +02:00
22 .global CalcRegisters
primo commit
2023-07-02 17:09:41 +02:00
23 .syntax unified
24 .thumb
25 .thumb_func
UI led
2025-06-28 00:58:29 +02:00
27 CalcRegisters:
primo commit
2023-07-02 17:09:41 +02:00
28 .LVL0:
29 .LFB329:
1:Src/si5351.c **** #include "main.h"
UI led
2025-06-28 00:58:29 +02:00
2:Src/si5351.c **** #include <math.h>
3:Src/si5351.c **** #include "si5351.h"
4:Src/si5351.c **** #include "si5351_cfg.h"
primo commit
2023-07-02 17:09:41 +02:00
5:Src/si5351.c ****
6:Src/si5351.c **** uint8_t oeb;
7:Src/si5351.c ****
UI led
2025-06-28 00:58:29 +02:00
8:Src/si5351.c **** void CalcRegisters(uint32_t fout, uint8_t *regs){
30 .loc 1 8 49 view -0
primo commit
2023-07-02 17:09:41 +02:00
31 .cfi_startproc
UI led
2025-06-28 00:58:29 +02:00
32 @ args = 0, pretend = 0, frame = 0
primo commit
2023-07-02 17:09:41 +02:00
33 @ frame_needed = 0, uses_anonymous_args = 0
UI led
2025-06-28 00:58:29 +02:00
34 .loc 1 8 49 is_stmt 0 view .LVU1
35 0000 2DE9F84F push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
primo commit
2023-07-02 17:09:41 +02:00
36 .LCFI0:
UI led
2025-06-28 00:58:29 +02:00
37 .cfi_def_cfa_offset 40
38 .cfi_offset 3, -40
39 .cfi_offset 4, -36
40 .cfi_offset 5, -32
41 .cfi_offset 6, -28
42 .cfi_offset 7, -24
43 .cfi_offset 8, -20
44 .cfi_offset 9, -16
45 .cfi_offset 10, -12
46 .cfi_offset 11, -8
47 .cfi_offset 14, -4
48 0004 8046 mov r8, r0
49 0006 0C46 mov r4, r1
9:Src/si5351.c **** // uint32_t fref = SI5351_CRYSTAL_FREQ; // The reference frequency
ARM GAS /tmp/cccZCQn9.s page 2
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
10:Src/si5351.c ****
11:Src/si5351.c **** // Calc Output Multisynth Divider and R with e = 0 and f = 1 => msx_p2 = 0 and msx_p3 = 1
12:Src/si5351.c **** uint32_t d = 4;
50 .loc 1 12 5 is_stmt 1 view .LVU2
51 .LVL1:
13:Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY
52 .loc 1 13 5 view .LVU3
14:Src/si5351.c **** int msx_divby4 = 0;
53 .loc 1 14 5 view .LVU4
15:Src/si5351.c **** int rx_div = 0;
54 .loc 1 15 5 view .LVU5
16:Src/si5351.c **** int r = 1;
55 .loc 1 16 5 view .LVU6
17:Src/si5351.c ****
18:Src/si5351.c **** if (fout > 150e6)
56 .loc 1 18 5 view .LVU7
57 .loc 1 18 8 is_stmt 0 view .LVU8
58 0008 674B ldr r3, .L19+24
59 000a 9842 cmp r0, r3
60 000c 49D8 bhi .L10
19:Src/si5351.c **** msx_divby4 = 0x0C; // MSx_DIVBY4[1:0] = 0b11, see datasheet 4.1.3
20:Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas
61 .loc 1 20 10 is_stmt 1 view .LVU9
62 .loc 1 20 13 is_stmt 0 view .LVU10
63 000e 674B ldr r3, .L19+28
64 0010 9842 cmp r0, r3
65 0012 38D9 bls .L11
21:Src/si5351.c **** {
22:Src/si5351.c **** int rd = 0;
23:Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL))
24:Src/si5351.c **** {
25:Src/si5351.c **** r <<= 1;
26:Src/si5351.c **** rd++;
27:Src/si5351.c **** }
28:Src/si5351.c **** rx_div = rd << 4;
29:Src/si5351.c ****
30:Src/si5351.c **** d = 600e6 / (r * fout); // Use lowest VCO frequency but handle d minimum
31:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
32:Src/si5351.c **** d++;
33:Src/si5351.c ****
34:Src/si5351.c **** if (d * r * fout < 600e6) // VCO frequency to low check and maintain an even
35:Src/si5351.c **** d += 2;
36:Src/si5351.c **** }
37:Src/si5351.c **** else // 292968 Hz <= fout <= 150 MHz
38:Src/si5351.c **** {
39:Src/si5351.c **** d = 600e6 / fout; // Use lowest VCO frequency but handle d minimum
66 .loc 1 39 9 is_stmt 1 view .LVU11
67 .loc 1 39 19 is_stmt 0 view .LVU12
68 0014 FFF7FEFF bl __aeabi_ui2d
69 .LVL2:
70 .loc 1 39 19 view .LVU13
71 0018 0246 mov r2, r0
72 001a 0B46 mov r3, r1
73 001c 5CA1 adr r1, .L19
74 001e D1E90001 ldrd r0, [r1]
75 0022 FFF7FEFF bl __aeabi_ddiv
76 .LVL3:
ARM GAS /tmp/cccZCQn9.s page 3
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
77 .loc 1 39 11 view .LVU14
78 0026 FFF7FEFF bl __aeabi_d2uiz
79 .LVL4:
40:Src/si5351.c **** if (d < 6)
80 .loc 1 40 9 is_stmt 1 view .LVU15
81 .loc 1 40 12 is_stmt 0 view .LVU16
82 002a 0528 cmp r0, #5
83 002c 2ED9 bls .L13
41:Src/si5351.c **** d = 6;
42:Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d
84 .loc 1 42 14 is_stmt 1 view .LVU17
85 .loc 1 42 17 is_stmt 0 view .LVU18
86 002e 10F0010F tst r0, #1
87 0032 2CD0 beq .L8
43:Src/si5351.c **** d++;
88 .loc 1 43 12 is_stmt 1 view .LVU19
89 .loc 1 43 13 is_stmt 0 view .LVU20
90 0034 0130 adds r0, r0, #1
91 .LVL5:
92 .loc 1 43 13 view .LVU21
93 0036 2AE0 b .L8
94 .LVL6:
95 .L6:
96 .LBB2:
25:Src/si5351.c **** rd++;
97 .loc 1 25 13 is_stmt 1 view .LVU22
25:Src/si5351.c **** rd++;
98 .loc 1 25 15 is_stmt 0 view .LVU23
99 0038 7600 lsls r6, r6, #1
100 .LVL7:
26:Src/si5351.c **** }
101 .loc 1 26 13 is_stmt 1 view .LVU24
26:Src/si5351.c **** }
102 .loc 1 26 15 is_stmt 0 view .LVU25
103 003a 0135 adds r5, r5, #1
104 .LVL8:
105 .L3:
23:Src/si5351.c **** {
106 .loc 1 23 26 is_stmt 1 view .LVU26
107 003c 7F2E cmp r6, #127
108 003e 04DC bgt .L5
23:Src/si5351.c **** {
109 .loc 1 23 32 is_stmt 0 discriminator 1 view .LVU27
110 0040 08FB06F2 mul r2, r8, r6
23:Src/si5351.c **** {
111 .loc 1 23 26 discriminator 1 view .LVU28
112 0044 594B ldr r3, .L19+28
113 0046 9A42 cmp r2, r3
114 0048 F6D9 bls .L6
115 .L5:
28:Src/si5351.c ****
116 .loc 1 28 9 is_stmt 1 view .LVU29
28:Src/si5351.c ****
117 .loc 1 28 16 is_stmt 0 view .LVU30
118 004a 2D01 lsls r5, r5, #4
119 .LVL9:
30:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
ARM GAS /tmp/cccZCQn9.s page 4
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
120 .loc 1 30 9 is_stmt 1 view .LVU31
30:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
121 .loc 1 30 24 is_stmt 0 view .LVU32
122 004c 3746 mov r7, r6
30:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
123 .loc 1 30 19 view .LVU33
124 004e 08FB06F0 mul r0, r8, r6
125 .LVL10:
30:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
126 .loc 1 30 19 view .LVU34
127 0052 FFF7FEFF bl __aeabi_ui2d
128 .LVL11:
30:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
129 .loc 1 30 19 view .LVU35
130 0056 0246 mov r2, r0
131 0058 0B46 mov r3, r1
132 005a 4DA1 adr r1, .L19
133 005c D1E90001 ldrd r0, [r1]
134 0060 FFF7FEFF bl __aeabi_ddiv
135 .LVL12:
30:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
136 .loc 1 30 11 view .LVU36
137 0064 FFF7FEFF bl __aeabi_d2uiz
138 .LVL13:
31:Src/si5351.c **** d++;
139 .loc 1 31 9 is_stmt 1 view .LVU37
31:Src/si5351.c **** d++;
140 .loc 1 31 12 is_stmt 0 view .LVU38
141 0068 10F0010F tst r0, #1
142 006c 00D0 beq .L7
32:Src/si5351.c ****
143 .loc 1 32 13 is_stmt 1 view .LVU39
32:Src/si5351.c ****
144 .loc 1 32 14 is_stmt 0 view .LVU40
145 006e 0130 adds r0, r0, #1
146 .LVL14:
147 .L7:
34:Src/si5351.c **** d += 2;
148 .loc 1 34 9 is_stmt 1 view .LVU41
34:Src/si5351.c **** d += 2;
149 .loc 1 34 15 is_stmt 0 view .LVU42
150 0070 00FB07F7 mul r7, r0, r7
34:Src/si5351.c **** d += 2;
151 .loc 1 34 19 view .LVU43
152 0074 08FB07F7 mul r7, r8, r7
34:Src/si5351.c **** d += 2;
153 .loc 1 34 12 view .LVU44
154 0078 4D4B ldr r3, .L19+32
155 007a 9F42 cmp r7, r3
156 007c 4ED8 bhi .L12
35:Src/si5351.c **** }
157 .loc 1 35 13 is_stmt 1 view .LVU45
35:Src/si5351.c **** }
158 .loc 1 35 15 is_stmt 0 view .LVU46
159 007e 0230 adds r0, r0, #2
160 .LVL15:
35:Src/si5351.c **** }
ARM GAS /tmp/cccZCQn9.s page 5
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
161 .loc 1 35 15 view .LVU47
162 .LBE2:
14:Src/si5351.c **** int rx_div = 0;
163 .loc 1 14 9 view .LVU48
164 0080 4FF0000A mov r10, #0
165 0084 12E0 b .L2
166 .LVL16:
167 .L11:
168 .LBB3:
22:Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL))
169 .loc 1 22 13 view .LVU49
170 0086 0025 movs r5, #0
171 .LBE3:
16:Src/si5351.c ****
172 .loc 1 16 9 view .LVU50
173 0088 0126 movs r6, #1
174 008a D7E7 b .L3
175 .LVL17:
176 .L13:
41:Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d
177 .loc 1 41 15 view .LVU51
178 008c 0620 movs r0, #6
179 .LVL18:
180 .L8:
44:Src/si5351.c ****
45:Src/si5351.c **** if (d * fout < 600e6) // VCO frequency to low check and maintain an even
181 .loc 1 45 9 is_stmt 1 view .LVU52
182 .loc 1 45 15 is_stmt 0 view .LVU53
183 008e 08FB00F2 mul r2, r8, r0
184 .loc 1 45 12 view .LVU54
185 0092 474B ldr r3, .L19+32
186 0094 9A42 cmp r2, r3
187 0096 44D8 bhi .L14
46:Src/si5351.c **** d += 2;
188 .loc 1 46 13 is_stmt 1 view .LVU55
189 .loc 1 46 15 is_stmt 0 view .LVU56
190 0098 0230 adds r0, r0, #2
191 .LVL19:
16:Src/si5351.c ****
192 .loc 1 16 9 view .LVU57
193 009a 0126 movs r6, #1
15:Src/si5351.c **** int r = 1;
194 .loc 1 15 9 view .LVU58
195 009c 0025 movs r5, #0
14:Src/si5351.c **** int rx_div = 0;
196 .loc 1 14 9 view .LVU59
197 009e AA46 mov r10, r5
198 00a0 04E0 b .L2
199 .LVL20:
200 .L10:
16:Src/si5351.c ****
201 .loc 1 16 9 view .LVU60
202 00a2 0126 movs r6, #1
15:Src/si5351.c **** int r = 1;
203 .loc 1 15 9 view .LVU61
204 00a4 0025 movs r5, #0
19:Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas
ARM GAS /tmp/cccZCQn9.s page 6
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
205 .loc 1 19 20 view .LVU62
206 00a6 4FF00C0A mov r10, #12
12:Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY
207 .loc 1 12 14 view .LVU63
208 00aa 0420 movs r0, #4
209 .LVL21:
210 .L2:
47:Src/si5351.c **** }
48:Src/si5351.c **** msx_p1 = 128 * d - 512;
211 .loc 1 48 5 is_stmt 1 view .LVU64
212 .loc 1 48 22 is_stmt 0 view .LVU65
213 00ac 00F10077 add r7, r0, #33554432
214 00b0 043F subs r7, r7, #4
215 .loc 1 48 12 view .LVU66
216 00b2 FF01 lsls r7, r7, #7
217 .LVL22:
49:Src/si5351.c ****
50:Src/si5351.c **** uint32_t fvco = (uint32_t) d * r * fout;
218 .loc 1 50 5 is_stmt 1 view .LVU67
219 .loc 1 50 34 is_stmt 0 view .LVU68
220 00b4 06FB00F0 mul r0, r6, r0
221 .LVL23:
51:Src/si5351.c ****
52:Src/si5351.c **** // Calc Feedback Multisynth Divider
53:Src/si5351.c **** double fmd = (double)fvco / SI5351_CRYSTAL_FREQ; // The FMD value has been found
222 .loc 1 53 5 is_stmt 1 view .LVU69
223 .loc 1 53 18 is_stmt 0 view .LVU70
224 00b8 08FB00F0 mul r0, r8, r0
225 .LVL24:
226 .loc 1 53 18 view .LVU71
227 00bc FFF7FEFF bl __aeabi_ui2d
228 .LVL25:
229 .loc 1 53 12 view .LVU72
230 00c0 35A3 adr r3, .L19+8
231 00c2 D3E90023 ldrd r2, [r3]
232 00c6 FFF7FEFF bl __aeabi_ddiv
233 .LVL26:
234 00ca 8046 mov r8, r0
235 .LVL27:
236 .loc 1 53 12 view .LVU73
237 00cc 8946 mov r9, r1
238 .LVL28:
54:Src/si5351.c **** int a = fmd; // a is the integer part of the FMD value
239 .loc 1 54 5 is_stmt 1 view .LVU74
240 .loc 1 54 9 is_stmt 0 view .LVU75
241 00ce FFF7FEFF bl __aeabi_d2iz
242 .LVL29:
243 00d2 0646 mov r6, r0
244 .LVL30:
55:Src/si5351.c ****
56:Src/si5351.c **** double b_c = (double)fmd - a; // Get b/c
245 .loc 1 56 5 is_stmt 1 view .LVU76
246 .loc 1 56 30 is_stmt 0 view .LVU77
247 00d4 FFF7FEFF bl __aeabi_i2d
248 .LVL31:
249 .loc 1 56 30 view .LVU78
250 00d8 0246 mov r2, r0
ARM GAS /tmp/cccZCQn9.s page 7
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
251 00da 0B46 mov r3, r1
252 .loc 1 56 12 view .LVU79
253 00dc 4046 mov r0, r8
254 00de 4946 mov r1, r9
255 00e0 FFF7FEFF bl __aeabi_dsub
256 .LVL32:
257 00e4 8046 mov r8, r0
258 .LVL33:
259 .loc 1 56 12 view .LVU80
260 00e6 8946 mov r9, r1
261 .LVL34:
57:Src/si5351.c **** uint32_t c = 1048575UL;
262 .loc 1 57 5 is_stmt 1 view .LVU81
58:Src/si5351.c **** uint32_t b = (double)b_c * c;
263 .loc 1 58 5 view .LVU82
264 .loc 1 58 30 is_stmt 0 view .LVU83
265 00e8 2DA3 adr r3, .L19+16
266 00ea D3E90023 ldrd r2, [r3]
267 00ee FFF7FEFF bl __aeabi_dmul
268 .LVL35:
269 .loc 1 58 14 view .LVU84
270 00f2 FFF7FEFF bl __aeabi_d2uiz
271 .LVL36:
59:Src/si5351.c **** if (b > 0)
272 .loc 1 59 5 is_stmt 1 view .LVU85
273 .loc 1 59 8 is_stmt 0 view .LVU86
274 00f6 8346 mov fp, r0
275 00f8 B8B1 cbz r0, .L15
60:Src/si5351.c **** {
61:Src/si5351.c **** c = (double)b / b_c + 0.5; // Improves frequency precision in some cases
276 .loc 1 61 9 is_stmt 1 view .LVU87
277 .loc 1 61 13 is_stmt 0 view .LVU88
278 00fa FFF7FEFF bl __aeabi_ui2d
279 .LVL37:
280 .loc 1 61 23 view .LVU89
281 00fe 4246 mov r2, r8
282 0100 4B46 mov r3, r9
283 0102 FFF7FEFF bl __aeabi_ddiv
284 .LVL38:
285 .loc 1 61 29 view .LVU90
286 0106 0022 movs r2, #0
287 0108 2A4B ldr r3, .L19+36
288 010a FFF7FEFF bl __aeabi_dadd
289 .LVL39:
290 .loc 1 61 11 view .LVU91
291 010e FFF7FEFF bl __aeabi_d2uiz
292 .LVL40:
62:Src/si5351.c **** if (c > 1048575UL)
293 .loc 1 62 9 is_stmt 1 view .LVU92
294 .loc 1 62 12 is_stmt 0 view .LVU93
295 0112 B0F5801F cmp r0, #1048576
296 0116 09D3 bcc .L9
63:Src/si5351.c **** c = 1048575UL;
297 .loc 1 63 15 view .LVU94
298 0118 2748 ldr r0, .L19+40
299 .LVL41:
300 .loc 1 63 15 view .LVU95
ARM GAS /tmp/cccZCQn9.s page 8
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
301 011a 07E0 b .L9
302 .LVL42:
303 .L12:
14:Src/si5351.c **** int rx_div = 0;
304 .loc 1 14 9 view .LVU96
305 011c 4FF0000A mov r10, #0
306 0120 C4E7 b .L2
307 .LVL43:
308 .L14:
16:Src/si5351.c ****
309 .loc 1 16 9 view .LVU97
310 0122 0126 movs r6, #1
15:Src/si5351.c **** int r = 1;
311 .loc 1 15 9 view .LVU98
312 0124 0025 movs r5, #0
14:Src/si5351.c **** int rx_div = 0;
313 .loc 1 14 9 view .LVU99
314 0126 AA46 mov r10, r5
315 0128 C0E7 b .L2
316 .LVL44:
317 .L15:
57:Src/si5351.c **** uint32_t b = (double)b_c * c;
318 .loc 1 57 14 view .LVU100
319 012a 2348 ldr r0, .L19+40
320 .LVL45:
321 .L9:
64:Src/si5351.c **** }
65:Src/si5351.c ****
66:Src/si5351.c **** uint32_t msnx_p1 = 128 * a + 128 * b / c - 512; // See datasheet 3.2
322 .loc 1 66 5 is_stmt 1 view .LVU101
323 .loc 1 66 38 is_stmt 0 view .LVU102
324 012c 4FEACB1B lsl fp, fp, #7
325 .LVL46:
326 .loc 1 66 42 view .LVU103
327 0130 BBFBF0F3 udiv r3, fp, r0
328 .loc 1 66 32 view .LVU104
329 0134 03EBC616 add r6, r3, r6, lsl #7
330 .LVL47:
331 .loc 1 66 14 view .LVU105
332 0138 A6F50076 sub r6, r6, #512
333 .LVL48:
67:Src/si5351.c **** uint32_t msnx_p2 = 128 * b - c * (128 * b / c);
334 .loc 1 67 5 is_stmt 1 view .LVU106
335 .loc 1 67 14 is_stmt 0 view .LVU107
336 013c 00FB13BB mls fp, r0, r3, fp
337 .LVL49:
68:Src/si5351.c **** uint32_t msnx_p3 = c;
338 .loc 1 68 5 is_stmt 1 view .LVU108
69:Src/si5351.c ****
70:Src/si5351.c **** // Feedback Multisynth Divider registers
71:Src/si5351.c **** regs[0] = (msnx_p3 >> 8) & 0xFF;
339 .loc 1 71 5 view .LVU109
340 .loc 1 71 24 is_stmt 0 view .LVU110
341 0140 030A lsrs r3, r0, #8
342 .loc 1 71 13 view .LVU111
343 0142 2370 strb r3, [r4]
72:Src/si5351.c **** regs[1] = msnx_p3 & 0xFF;
ARM GAS /tmp/cccZCQn9.s page 9
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
344 .loc 1 72 5 is_stmt 1 view .LVU112
345 .loc 1 72 13 is_stmt 0 view .LVU113
346 0144 6070 strb r0, [r4, #1]
73:Src/si5351.c **** regs[2] = (msnx_p1 >> 16) & 0x03;
347 .loc 1 73 5 is_stmt 1 view .LVU114
348 .loc 1 73 31 is_stmt 0 view .LVU115
349 0146 C6F30143 ubfx r3, r6, #16, #2
350 .loc 1 73 13 view .LVU116
351 014a A370 strb r3, [r4, #2]
74:Src/si5351.c **** regs[3] = (msnx_p1 >> 8) & 0xFF;
352 .loc 1 74 5 is_stmt 1 view .LVU117
353 .loc 1 74 24 is_stmt 0 view .LVU118
354 014c 330A lsrs r3, r6, #8
355 .loc 1 74 13 view .LVU119
356 014e E370 strb r3, [r4, #3]
75:Src/si5351.c **** regs[4] = msnx_p1 & 0xFF;
357 .loc 1 75 5 is_stmt 1 view .LVU120
358 .loc 1 75 13 is_stmt 0 view .LVU121
359 0150 2671 strb r6, [r4, #4]
76:Src/si5351.c **** regs[5] = ((msnx_p3 >> 12) & 0xF0) + ((msnx_p2 >> 16) & 0x0F);
360 .loc 1 76 5 is_stmt 1 view .LVU122
361 .loc 1 76 25 is_stmt 0 view .LVU123
362 0152 000B lsrs r0, r0, #12
363 .LVL50:
364 .loc 1 76 32 view .LVU124
365 0154 00F0F000 and r0, r0, #240
366 .loc 1 76 59 view .LVU125
367 0158 CBF30343 ubfx r3, fp, #16, #4
368 .loc 1 76 40 view .LVU126
369 015c 1843 orrs r0, r0, r3
370 .loc 1 76 13 view .LVU127
371 015e 6071 strb r0, [r4, #5]
77:Src/si5351.c **** regs[6] = (msnx_p2 >> 8) & 0xFF;
372 .loc 1 77 5 is_stmt 1 view .LVU128
373 .loc 1 77 24 is_stmt 0 view .LVU129
374 0160 4FEA1B23 lsr r3, fp, #8
375 .loc 1 77 13 view .LVU130
376 0164 A371 strb r3, [r4, #6]
78:Src/si5351.c **** regs[7] = msnx_p2 & 0xFF;
377 .loc 1 78 5 is_stmt 1 view .LVU131
378 .loc 1 78 13 is_stmt 0 view .LVU132
379 0166 84F807B0 strb fp, [r4, #7]
79:Src/si5351.c ****
80:Src/si5351.c **** // Output Multisynth Divider registers
81:Src/si5351.c **** regs[8] = 0; // (msx_p3 >> 8) & 0xFF
380 .loc 1 81 5 is_stmt 1 view .LVU133
381 .loc 1 81 13 is_stmt 0 view .LVU134
382 016a 0023 movs r3, #0
383 016c 2372 strb r3, [r4, #8]
82:Src/si5351.c **** regs[9] = 1; // msx_p3 & 0xFF
384 .loc 1 82 5 is_stmt 1 view .LVU135
385 .loc 1 82 13 is_stmt 0 view .LVU136
386 016e 0122 movs r2, #1
387 0170 6272 strb r2, [r4, #9]
83:Src/si5351.c **** regs[10] = rx_div + msx_divby4 + ((msx_p1 >> 16) & 0x03);
388 .loc 1 83 5 is_stmt 1 view .LVU137
389 .loc 1 83 23 is_stmt 0 view .LVU138
ARM GAS /tmp/cccZCQn9.s page 10
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
390 0172 5544 add r5, r5, r10
391 .LVL51:
392 .loc 1 83 23 view .LVU139
393 0174 EDB2 uxtb r5, r5
394 .loc 1 83 54 view .LVU140
395 0176 C7F30142 ubfx r2, r7, #16, #2
396 .loc 1 83 36 view .LVU141
397 017a 1544 add r5, r5, r2
398 .loc 1 83 14 view .LVU142
399 017c A572 strb r5, [r4, #10]
84:Src/si5351.c **** regs[11] = (msx_p1 >> 8) & 0xFF;
400 .loc 1 84 5 is_stmt 1 view .LVU143
401 .loc 1 84 24 is_stmt 0 view .LVU144
402 017e 3A0A lsrs r2, r7, #8
403 .loc 1 84 14 view .LVU145
404 0180 E272 strb r2, [r4, #11]
85:Src/si5351.c **** regs[12] = msx_p1 & 0xFF;
405 .loc 1 85 5 is_stmt 1 view .LVU146
406 .loc 1 85 14 is_stmt 0 view .LVU147
407 0182 2773 strb r7, [r4, #12]
86:Src/si5351.c **** regs[13] = 0; // ((msx_p3 >> 12) & 0xF0) + (msx_p2 >> 16) & 0x0
408 .loc 1 86 5 is_stmt 1 view .LVU148
409 .loc 1 86 14 is_stmt 0 view .LVU149
410 0184 6373 strb r3, [r4, #13]
87:Src/si5351.c **** regs[14] = 0; // (msx_p2 >> 8) & 0xFF
411 .loc 1 87 5 is_stmt 1 view .LVU150
412 .loc 1 87 14 is_stmt 0 view .LVU151
413 0186 A373 strb r3, [r4, #14]
88:Src/si5351.c **** regs[15] = 0; // msx_p2 & 0xFF
414 .loc 1 88 5 is_stmt 1 view .LVU152
415 .loc 1 88 14 is_stmt 0 view .LVU153
416 0188 E373 strb r3, [r4, #15]
89:Src/si5351.c ****
90:Src/si5351.c **** // HAL_I2C_Master_Transmit(&hi2c2, Si5351_ConfigStruct->HW_I2C_Address, reg_data, sizeof(reg_data),
91:Src/si5351.c **** return;
417 .loc 1 91 5 is_stmt 1 view .LVU154
92:Src/si5351.c **** }
418 .loc 1 92 1 is_stmt 0 view .LVU155
419 018a BDE8F88F pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
420 .LVL52:
421 .L20:
422 .loc 1 92 1 view .LVU156
423 018e 00BF .align 3
424 .L19:
425 0190 00000000 .word 0
426 0194 A3E1C141 .word 1103225251
427 0198 00000000 .word 0
428 019c 60E37641 .word 1098310496
429 01a0 00000000 .word 0
430 01a4 FEFF2F41 .word 1093664766
431 01a8 80D1F008 .word 150000000
432 01ac 68780400 .word 292968
433 01b0 FF45C323 .word 599999999
434 01b4 0000E03F .word 1071644672
435 01b8 FFFF0F00 .word 1048575
436 .cfi_endproc
437 .LFE329:
ARM GAS /tmp/cccZCQn9.s page 11
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
439 .section .text.si5351_initialize,"ax",%progbits
440 .align 1
441 .global si5351_initialize
442 .syntax unified
443 .thumb
444 .thumb_func
446 si5351_initialize:
447 .LFB330:
93:Src/si5351.c ****
94:Src/si5351.c **** void si5351_initialize(){
448 .loc 1 94 25 is_stmt 1 view -0
449 .cfi_startproc
450 @ args = 0, pretend = 0, frame = 8
451 @ frame_needed = 0, uses_anonymous_args = 0
452 0000 00B5 push {lr}
453 .LCFI1:
454 .cfi_def_cfa_offset 4
455 .cfi_offset 14, -4
456 0002 83B0 sub sp, sp, #12
457 .LCFI2:
458 .cfi_def_cfa_offset 16
459 .L22:
95:Src/si5351.c **** uint8_t dummy;
96:Src/si5351.c **** // Initialize Si5351A
97:Src/si5351.c **** while (si5351_read8(0,&dummy) & 0x80); // Wait for Si5351A to initialize
460 .loc 1 97 9 discriminator 1 view .LVU158
461 0004 0DF10701 add r1, sp, #7
462 0008 0020 movs r0, #0
463 000a FFF7FEFF bl si5351_read8
464 .LVL53:
465 000e 10F0800F tst r0, #128
466 0012 F7D1 bne .L22
98:Src/si5351.c **** oeb = 0xFF;
467 .loc 1 98 2 view .LVU159
468 .loc 1 98 6 is_stmt 0 view .LVU160
469 0014 FF21 movs r1, #255
470 0016 2E4B ldr r3, .L24
471 0018 1970 strb r1, [r3]
99:Src/si5351.c ****
100:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb); // Output Enable Control, disable all
472 .loc 1 100 5 is_stmt 1 view .LVU161
473 001a 0320 movs r0, #3
474 001c FFF7FEFF bl si5351_write8
475 .LVL54:
101:Src/si5351.c ****
102:Src/si5351.c **** si5351_write8(SI5351_INPUT_SOURCE, 0x00); // PLL Input Source, select the XTAL input
476 .loc 1 102 5 view .LVU162
477 0020 0021 movs r1, #0
478 0022 0F20 movs r0, #15
479 0024 FFF7FEFF bl si5351_write8
480 .LVL55:
103:Src/si5351.c **** si5351_write8(SI5351_OUT_DIS_STATE, 0x00); // stato bassa Z giu se disabilitati
481 .loc 1 103 5 view .LVU163
482 0028 0021 movs r1, #0
483 002a 1820 movs r0, #24
484 002c FFF7FEFF bl si5351_write8
485 .LVL56:
ARM GAS /tmp/cccZCQn9.s page 12
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
104:Src/si5351.c ****
105:Src/si5351.c **** // Output MultisynthN, e = 0, f = 1, MS0_P2 and MSO_P3
106:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0, 0x00);
486 .loc 1 106 5 view .LVU164
487 0030 0021 movs r1, #0
488 0032 2A20 movs r0, #42
489 0034 FFF7FEFF bl si5351_write8
490 .LVL57:
107:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+1, 0x01);
491 .loc 1 107 5 view .LVU165
492 0038 0121 movs r1, #1
493 003a 2B20 movs r0, #43
494 003c FFF7FEFF bl si5351_write8
495 .LVL58:
108:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+5, 0x00);
496 .loc 1 108 5 view .LVU166
497 0040 0021 movs r1, #0
498 0042 2F20 movs r0, #47
499 0044 FFF7FEFF bl si5351_write8
500 .LVL59:
109:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+6, 0x00);
501 .loc 1 109 5 view .LVU167
502 0048 0021 movs r1, #0
503 004a 3020 movs r0, #48
504 004c FFF7FEFF bl si5351_write8
505 .LVL60:
110:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+7, 0x00);
506 .loc 1 110 5 view .LVU168
507 0050 0021 movs r1, #0
508 0052 3120 movs r0, #49
509 0054 FFF7FEFF bl si5351_write8
510 .LVL61:
111:Src/si5351.c ****
112:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1, 0x00);
511 .loc 1 112 5 view .LVU169
512 0058 0021 movs r1, #0
513 005a 3220 movs r0, #50
514 005c FFF7FEFF bl si5351_write8
515 .LVL62:
113:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+1, 0x01);
516 .loc 1 113 5 view .LVU170
517 0060 0121 movs r1, #1
518 0062 3320 movs r0, #51
519 0064 FFF7FEFF bl si5351_write8
520 .LVL63:
114:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+5, 0x00);
521 .loc 1 114 5 view .LVU171
522 0068 0021 movs r1, #0
523 006a 3720 movs r0, #55
524 006c FFF7FEFF bl si5351_write8
525 .LVL64:
115:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+6, 0x00);
526 .loc 1 115 5 view .LVU172
527 0070 0021 movs r1, #0
528 0072 3820 movs r0, #56
529 0074 FFF7FEFF bl si5351_write8
530 .LVL65:
ARM GAS /tmp/cccZCQn9.s page 13
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
116:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+7, 0x00);
531 .loc 1 116 5 view .LVU173
532 0078 0021 movs r1, #0
533 007a 3920 movs r0, #57
534 007c FFF7FEFF bl si5351_write8
535 .LVL66:
117:Src/si5351.c ****
118:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2, 0x00);
536 .loc 1 118 5 view .LVU174
537 0080 0021 movs r1, #0
538 0082 3A20 movs r0, #58
539 0084 FFF7FEFF bl si5351_write8
540 .LVL67:
119:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+1, 0x01);
541 .loc 1 119 5 view .LVU175
542 0088 0121 movs r1, #1
543 008a 3B20 movs r0, #59
544 008c FFF7FEFF bl si5351_write8
545 .LVL68:
120:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+5, 0x00);
546 .loc 1 120 5 view .LVU176
547 0090 0021 movs r1, #0
548 0092 3F20 movs r0, #63
549 0094 FFF7FEFF bl si5351_write8
550 .LVL69:
121:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+6, 0x00);
551 .loc 1 121 5 view .LVU177
552 0098 0021 movs r1, #0
553 009a 4020 movs r0, #64
554 009c FFF7FEFF bl si5351_write8
555 .LVL70:
122:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+7, 0x00);
556 .loc 1 122 5 view .LVU178
557 00a0 0021 movs r1, #0
558 00a2 4120 movs r0, #65
559 00a4 FFF7FEFF bl si5351_write8
560 .LVL71:
123:Src/si5351.c ****
124:Src/si5351.c **** si5351_write8(SI5351_CLK0_CONTROL, 0x4F); // Power up CLK0, PLLA, MS0 operates in integer mod
561 .loc 1 124 5 view .LVU179
562 00a8 4F21 movs r1, #79
563 00aa 1020 movs r0, #16
564 00ac FFF7FEFF bl si5351_write8
565 .LVL72:
125:Src/si5351.c **** si5351_write8(SI5351_CLK1_CONTROL, 0x5F); // Power up CLK1, PLLA, MS0 operates in integer mod
566 .loc 1 125 5 view .LVU180
567 00b0 5F21 movs r1, #95
568 00b2 1120 movs r0, #17
569 00b4 FFF7FEFF bl si5351_write8
570 .LVL73:
126:Src/si5351.c **** si5351_write8(SI5351_CLK2_CONTROL, 0x6F); // Power up CLK2, PLLB, int, non inv, multisynth 2,
571 .loc 1 126 5 view .LVU181
572 00b8 6F21 movs r1, #111
573 00ba 1220 movs r0, #18
574 00bc FFF7FEFF bl si5351_write8
575 .LVL74:
127:Src/si5351.c ****
ARM GAS /tmp/cccZCQn9.s page 14
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
128:Src/si5351.c **** // Reference load configuration
129:Src/si5351.c **** si5351_write8(SI5351_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_VALUE); // Set reference load C
576 .loc 1 129 5 view .LVU182
577 00c0 1221 movs r1, #18
578 00c2 B720 movs r0, #183
579 00c4 FFF7FEFF bl si5351_write8
580 .LVL75:
130:Src/si5351.c **** }
581 .loc 1 130 1 is_stmt 0 view .LVU183
582 00c8 03B0 add sp, sp, #12
583 .LCFI3:
584 .cfi_def_cfa_offset 4
585 @ sp needed
586 00ca 5DF804FB ldr pc, [sp], #4
587 .L25:
588 00ce 00BF .align 2
589 .L24:
590 00d0 00000000 .word oeb
591 .cfi_endproc
592 .LFE330:
594 .section .text.si5351_set_frequency,"ax",%progbits
595 .align 1
596 .global si5351_set_frequency
597 .syntax unified
598 .thumb
599 .thumb_func
601 si5351_set_frequency:
602 .LVL76:
603 .LFB331:
primo commit
2023-07-02 17:09:41 +02:00
131:Src/si5351.c ****
UI led
2025-06-28 00:58:29 +02:00
132:Src/si5351.c **** void si5351_set_frequency(uint32_t freq, uint8_t pll){
604 .loc 1 132 54 is_stmt 1 view -0
605 .cfi_startproc
606 @ args = 0, pretend = 0, frame = 16
607 @ frame_needed = 0, uses_anonymous_args = 0
608 .loc 1 132 54 is_stmt 0 view .LVU185
609 0000 10B5 push {r4, lr}
610 .LCFI4:
611 .cfi_def_cfa_offset 8
612 .cfi_offset 4, -8
613 .cfi_offset 14, -4
614 0002 84B0 sub sp, sp, #16
615 .LCFI5:
616 .cfi_def_cfa_offset 24
617 0004 0C46 mov r4, r1
133:Src/si5351.c **** uint8_t regs[16];
618 .loc 1 133 2 is_stmt 1 view .LVU186
134:Src/si5351.c **** CalcRegisters(freq, regs);
619 .loc 1 134 2 view .LVU187
620 0006 6946 mov r1, sp
621 .LVL77:
622 .loc 1 134 2 is_stmt 0 view .LVU188
623 0008 FFF7FEFF bl CalcRegisters
624 .LVL78:
135:Src/si5351.c ****
136:Src/si5351.c **** // Load Output Multisynth0 with d (e and f already set during init. and never changed)
137:Src/si5351.c **** if(pll == 0){
ARM GAS /tmp/cccZCQn9.s page 15
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
625 .loc 1 137 2 is_stmt 1 view .LVU189
626 .loc 1 137 4 is_stmt 0 view .LVU190
627 000c 94B1 cbz r4, .L37
138:Src/si5351.c **** for (int i = 0; i < 8; i++)
139:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]);
140:Src/si5351.c **** for (int i = 10; i < 13; i++)
141:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
142:Src/si5351.c **** } else if(pll == 1){
628 .loc 1 142 9 is_stmt 1 view .LVU191
629 .loc 1 142 11 is_stmt 0 view .LVU192
630 000e 012C cmp r4, #1
631 0010 1FD1 bne .L32
632 .LBB4:
143:Src/si5351.c **** for (int i = 0; i < 8; i++)
633 .loc 1 143 12 view .LVU193
634 0012 0024 movs r4, #0
635 .LVL79:
636 .loc 1 143 12 view .LVU194
637 0014 2EE0 b .L33
638 .LVL80:
639 .L29:
640 .loc 1 143 12 view .LVU195
641 .LBE4:
642 .LBB5:
139:Src/si5351.c **** for (int i = 10; i < 13; i++)
643 .loc 1 139 4 is_stmt 1 view .LVU196
644 0016 04F11003 add r3, r4, #16
645 001a 6B44 add r3, sp, r3
646 001c 04F11A00 add r0, r4, #26
647 0020 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
648 0024 C0B2 uxtb r0, r0
649 0026 FFF7FEFF bl si5351_write8
650 .LVL81:
138:Src/si5351.c **** for (int i = 0; i < 8; i++)
651 .loc 1 138 27 discriminator 3 view .LVU197
652 002a 0134 adds r4, r4, #1
653 .LVL82:
654 .L27:
138:Src/si5351.c **** for (int i = 0; i < 8; i++)
655 .loc 1 138 21 discriminator 1 view .LVU198
656 002c 072C cmp r4, #7
657 002e F2DD ble .L29
658 .LBE5:
659 .LBB6:
140:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
660 .loc 1 140 12 is_stmt 0 view .LVU199
661 0030 0A24 movs r4, #10
662 .LVL83:
140:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
663 .loc 1 140 12 view .LVU200
664 0032 0CE0 b .L30
665 .LVL84:
666 .L37:
140:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
667 .loc 1 140 12 view .LVU201
668 .LBE6:
669 .LBB7:
ARM GAS /tmp/cccZCQn9.s page 16
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
138:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]);
670 .loc 1 138 12 view .LVU202
671 0034 0024 movs r4, #0
672 0036 F9E7 b .L27
673 .LVL85:
674 .L31:
138:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]);
675 .loc 1 138 12 view .LVU203
676 .LBE7:
677 .LBB8:
141:Src/si5351.c **** } else if(pll == 1){
678 .loc 1 141 11 is_stmt 1 view .LVU204
679 0038 04F11003 add r3, r4, #16
680 003c 6B44 add r3, sp, r3
681 003e 04F12200 add r0, r4, #34
682 0042 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
683 0046 C0B2 uxtb r0, r0
684 0048 FFF7FEFF bl si5351_write8
685 .LVL86:
140:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
686 .loc 1 140 29 discriminator 3 view .LVU205
687 004c 0134 adds r4, r4, #1
688 .LVL87:
689 .L30:
140:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
690 .loc 1 140 22 discriminator 1 view .LVU206
691 004e 0C2C cmp r4, #12
692 0050 F2DD ble .L31
693 .LVL88:
694 .L32:
140:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
695 .loc 1 140 22 is_stmt 0 discriminator 1 view .LVU207
696 .LBE8:
144:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
145:Src/si5351.c **** for (int i = 10; i < 13; i++)
146:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
147:Src/si5351.c **** }
148:Src/si5351.c ****
149:Src/si5351.c **** // Reset PLLA - fa un glitch, pero se non lo fai fa overflow
150:Src/si5351.c **** // HAL_Delay(1); // Allow registers to settle before resetting the PLL
151:Src/si5351.c **** si5351_write8(SI5351_RESET, 0x20);
697 .loc 1 151 5 is_stmt 1 view .LVU208
698 0052 2021 movs r1, #32
699 0054 B120 movs r0, #177
700 0056 FFF7FEFF bl si5351_write8
701 .LVL89:
152:Src/si5351.c **** }
702 .loc 1 152 1 is_stmt 0 view .LVU209
703 005a 04B0 add sp, sp, #16
704 .LCFI6:
705 .cfi_remember_state
706 .cfi_def_cfa_offset 8
707 @ sp needed
708 005c 10BD pop {r4, pc}
709 .LVL90:
710 .L34:
711 .LCFI7:
ARM GAS /tmp/cccZCQn9.s page 17
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
712 .cfi_restore_state
713 .LBB9:
144:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
714 .loc 1 144 4 is_stmt 1 view .LVU210
715 005e 04F11003 add r3, r4, #16
716 0062 6B44 add r3, sp, r3
717 0064 04F12200 add r0, r4, #34
718 0068 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
719 006c C0B2 uxtb r0, r0
720 006e FFF7FEFF bl si5351_write8
721 .LVL91:
143:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
722 .loc 1 143 27 discriminator 3 view .LVU211
723 0072 0134 adds r4, r4, #1
724 .LVL92:
725 .L33:
143:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
726 .loc 1 143 21 discriminator 1 view .LVU212
727 0074 072C cmp r4, #7
728 0076 F2DD ble .L34
729 .LBE9:
730 .LBB10:
145:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
731 .loc 1 145 12 is_stmt 0 view .LVU213
732 0078 0A24 movs r4, #10
733 .LVL93:
145:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
734 .loc 1 145 12 view .LVU214
735 007a 0AE0 b .L35
736 .LVL94:
737 .L36:
146:Src/si5351.c **** }
738 .loc 1 146 11 is_stmt 1 view .LVU215
739 007c 04F11003 add r3, r4, #16
740 0080 6B44 add r3, sp, r3
741 0082 04F12A00 add r0, r4, #42
742 0086 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
743 008a C0B2 uxtb r0, r0
744 008c FFF7FEFF bl si5351_write8
745 .LVL95:
145:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
746 .loc 1 145 29 discriminator 3 view .LVU216
747 0090 0134 adds r4, r4, #1
748 .LVL96:
749 .L35:
145:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
750 .loc 1 145 22 discriminator 1 view .LVU217
751 0092 0C2C cmp r4, #12
752 0094 F2DD ble .L36
753 0096 DCE7 b .L32
754 .LBE10:
755 .cfi_endproc
756 .LFE331:
758 .section .text.si5351_off_clk,"ax",%progbits
759 .align 1
760 .global si5351_off_clk
761 .syntax unified
ARM GAS /tmp/cccZCQn9.s page 18
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
762 .thumb
763 .thumb_func
765 si5351_off_clk:
766 .LVL97:
767 .LFB332:
153:Src/si5351.c ****
154:Src/si5351.c **** void si5351_off_clk(uint8_t clk){
768 .loc 1 154 33 view -0
769 .cfi_startproc
770 @ args = 0, pretend = 0, frame = 0
771 @ frame_needed = 0, uses_anonymous_args = 0
772 .loc 1 154 33 is_stmt 0 view .LVU219
773 0000 08B5 push {r3, lr}
774 .LCFI8:
775 .cfi_def_cfa_offset 8
776 .cfi_offset 3, -8
777 .cfi_offset 14, -4
155:Src/si5351.c **** oeb |= 1U << clk;
778 .loc 1 155 2 is_stmt 1 view .LVU220
779 .loc 1 155 12 is_stmt 0 view .LVU221
780 0002 0123 movs r3, #1
781 0004 8340 lsls r3, r3, r0
782 .loc 1 155 6 view .LVU222
783 0006 044A ldr r2, .L43
784 0008 1178 ldrb r1, [r2] @ zero_extendqisi2
785 000a 1943 orrs r1, r1, r3
786 000c C9B2 uxtb r1, r1
787 000e 1170 strb r1, [r2]
156:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb);
788 .loc 1 156 2 is_stmt 1 view .LVU223
789 0010 0320 movs r0, #3
790 .LVL98:
791 .loc 1 156 2 is_stmt 0 view .LVU224
792 0012 FFF7FEFF bl si5351_write8
793 .LVL99:
157:Src/si5351.c **** }
794 .loc 1 157 1 view .LVU225
795 0016 08BD pop {r3, pc}
796 .L44:
797 .align 2
798 .L43:
799 0018 00000000 .word oeb
800 .cfi_endproc
801 .LFE332:
803 .section .text.si5351_on_clk,"ax",%progbits
804 .align 1
805 .global si5351_on_clk
806 .syntax unified
807 .thumb
808 .thumb_func
810 si5351_on_clk:
811 .LVL100:
812 .LFB333:
158:Src/si5351.c ****
159:Src/si5351.c **** void si5351_on_clk(uint8_t clk){
813 .loc 1 159 32 is_stmt 1 view -0
814 .cfi_startproc
ARM GAS /tmp/cccZCQn9.s page 19
primo commit
2023-07-02 17:09:41 +02:00
UI led
2025-06-28 00:58:29 +02:00
815 @ args = 0, pretend = 0, frame = 0
816 @ frame_needed = 0, uses_anonymous_args = 0
817 .loc 1 159 32 is_stmt 0 view .LVU227
818 0000 08B5 push {r3, lr}
819 .LCFI9:
820 .cfi_def_cfa_offset 8
821 .cfi_offset 3, -8
822 .cfi_offset 14, -4
160:Src/si5351.c **** oeb &= ~(1U << clk);
823 .loc 1 160 2 is_stmt 1 view .LVU228
824 .loc 1 160 14 is_stmt 0 view .LVU229
825 0002 0123 movs r3, #1
826 0004 8340 lsls r3, r3, r0
827 .loc 1 160 6 view .LVU230
828 0006 044A ldr r2, .L47
829 0008 1178 ldrb r1, [r2] @ zero_extendqisi2
830 000a 21EA0301 bic r1, r1, r3
831 000e 1170 strb r1, [r2]
161:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb);
832 .loc 1 161 2 is_stmt 1 view .LVU231
833 0010 0320 movs r0, #3
834 .LVL101:
835 .loc 1 161 2 is_stmt 0 view .LVU232
836 0012 FFF7FEFF bl si5351_write8
837 .LVL102:
162:Src/si5351.c **** }
838 .loc 1 162 1 view .LVU233
839 0016 08BD pop {r3, pc}
840 .L48:
841 .align 2
842 .L47:
843 0018 00000000 .word oeb
844 .cfi_endproc
845 .LFE333:
847 .global oeb
848 .section .bss.oeb,"aw",%nobits
851 oeb:
852 0000 00 .space 1
853 .text
854 .Letext0:
855 .file 2 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach
856 .file 3 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/
857 .file 4 "Inc/si5351.h"
ARM GAS /tmp/cccZCQn9.s page 20
primo commit
2023-07-02 17:09:41 +02:00
DEFINED SYMBOLS
*ABS*:00000000 si5351.c
UI led
2025-06-28 00:58:29 +02:00
/tmp/cccZCQn9.s:21 .text.CalcRegisters:00000000 $t
/tmp/cccZCQn9.s:27 .text.CalcRegisters:00000000 CalcRegisters
/tmp/cccZCQn9.s:425 .text.CalcRegisters:00000190 $d
/tmp/cccZCQn9.s:440 .text.si5351_initialize:00000000 $t
/tmp/cccZCQn9.s:446 .text.si5351_initialize:00000000 si5351_initialize
/tmp/cccZCQn9.s:590 .text.si5351_initialize:000000d0 $d
/tmp/cccZCQn9.s:851 .bss.oeb:00000000 oeb
/tmp/cccZCQn9.s:595 .text.si5351_set_frequency:00000000 $t
/tmp/cccZCQn9.s:601 .text.si5351_set_frequency:00000000 si5351_set_frequency
/tmp/cccZCQn9.s:759 .text.si5351_off_clk:00000000 $t
/tmp/cccZCQn9.s:765 .text.si5351_off_clk:00000000 si5351_off_clk
/tmp/cccZCQn9.s:799 .text.si5351_off_clk:00000018 $d
/tmp/cccZCQn9.s:804 .text.si5351_on_clk:00000000 $t
/tmp/cccZCQn9.s:810 .text.si5351_on_clk:00000000 si5351_on_clk
/tmp/cccZCQn9.s:843 .text.si5351_on_clk:00000018 $d
/tmp/cccZCQn9.s:852 .bss.oeb:00000000 $d
primo commit
2023-07-02 17:09:41 +02:00
UNDEFINED SYMBOLS
__aeabi_ui2d
__aeabi_ddiv
__aeabi_d2uiz
__aeabi_d2iz
__aeabi_i2d
__aeabi_dsub
__aeabi_dmul
__aeabi_dadd
UI led
2025-06-28 00:58:29 +02:00
si5351_read8
si5351_write8
Reference in New Issue Copy Permalink