2025-06-28 00:58:29 +02:00
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ARM GAS /tmp/ccvxi4x8.s page 1
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2023-07-02 17:09:41 +02:00
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 1
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "system_stm32g4xx.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Src/system_stm32g4xx.c"
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20 .section .text.SystemInit,"ax",%progbits
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21 .align 1
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22 .global SystemInit
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 SystemInit:
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28 .LFB329:
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1:Src/system_stm32g4xx.c **** /**
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2:Src/system_stm32g4xx.c **** ******************************************************************************
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3:Src/system_stm32g4xx.c **** * @file system_stm32g4xx.c
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4:Src/system_stm32g4xx.c **** * @author MCD Application Team
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5:Src/system_stm32g4xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
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6:Src/system_stm32g4xx.c **** *
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7:Src/system_stm32g4xx.c **** * This file provides two functions and one global variable to be called from
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8:Src/system_stm32g4xx.c **** * user application:
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9:Src/system_stm32g4xx.c **** * - SystemInit(): This function is called at startup just after reset and
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10:Src/system_stm32g4xx.c **** * before branch to main program. This call is made inside
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11:Src/system_stm32g4xx.c **** * the "startup_stm32g4xx.s" file.
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12:Src/system_stm32g4xx.c **** *
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13:Src/system_stm32g4xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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14:Src/system_stm32g4xx.c **** * by the user application to setup the SysTick
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15:Src/system_stm32g4xx.c **** * timer or configure other parameters.
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16:Src/system_stm32g4xx.c **** *
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17:Src/system_stm32g4xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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18:Src/system_stm32g4xx.c **** * be called whenever the core clock is changed
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19:Src/system_stm32g4xx.c **** * during program execution.
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20:Src/system_stm32g4xx.c **** *
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21:Src/system_stm32g4xx.c **** * After each device reset the HSI (16 MHz) is used as system clock source.
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22:Src/system_stm32g4xx.c **** * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
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23:Src/system_stm32g4xx.c **** * configure the system clock before to branch to main program.
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24:Src/system_stm32g4xx.c **** *
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25:Src/system_stm32g4xx.c **** * This file configures the system clock as follows:
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26:Src/system_stm32g4xx.c **** *=============================================================================
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27:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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28:Src/system_stm32g4xx.c **** * System Clock source | HSI
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29:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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30:Src/system_stm32g4xx.c **** * SYSCLK(Hz) | 16000000
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ARM GAS /tmp/ccvxi4x8.s page 2
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2023-07-02 17:09:41 +02:00
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31:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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32:Src/system_stm32g4xx.c **** * HCLK(Hz) | 16000000
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33:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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34:Src/system_stm32g4xx.c **** * AHB Prescaler | 1
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35:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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36:Src/system_stm32g4xx.c **** * APB1 Prescaler | 1
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37:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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38:Src/system_stm32g4xx.c **** * APB2 Prescaler | 1
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39:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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40:Src/system_stm32g4xx.c **** * PLL_M | 1
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41:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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42:Src/system_stm32g4xx.c **** * PLL_N | 16
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43:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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44:Src/system_stm32g4xx.c **** * PLL_P | 7
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45:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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46:Src/system_stm32g4xx.c **** * PLL_Q | 2
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47:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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48:Src/system_stm32g4xx.c **** * PLL_R | 2
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49:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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50:Src/system_stm32g4xx.c **** * Require 48MHz for RNG | Disabled
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51:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
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52:Src/system_stm32g4xx.c **** *=============================================================================
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53:Src/system_stm32g4xx.c **** ******************************************************************************
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54:Src/system_stm32g4xx.c **** * @attention
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55:Src/system_stm32g4xx.c **** *
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56:Src/system_stm32g4xx.c **** * Copyright (c) 2019 STMicroelectronics.
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57:Src/system_stm32g4xx.c **** * All rights reserved.
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58:Src/system_stm32g4xx.c **** *
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59:Src/system_stm32g4xx.c **** * This software is licensed under terms that can be found in the LICENSE file
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60:Src/system_stm32g4xx.c **** * in the root directory of this software component.
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61:Src/system_stm32g4xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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62:Src/system_stm32g4xx.c **** *
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63:Src/system_stm32g4xx.c **** ******************************************************************************
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64:Src/system_stm32g4xx.c **** */
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65:Src/system_stm32g4xx.c ****
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66:Src/system_stm32g4xx.c **** /** @addtogroup CMSIS
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67:Src/system_stm32g4xx.c **** * @{
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68:Src/system_stm32g4xx.c **** */
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69:Src/system_stm32g4xx.c ****
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70:Src/system_stm32g4xx.c **** /** @addtogroup stm32g4xx_system
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71:Src/system_stm32g4xx.c **** * @{
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72:Src/system_stm32g4xx.c **** */
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73:Src/system_stm32g4xx.c ****
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74:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Includes
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75:Src/system_stm32g4xx.c **** * @{
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76:Src/system_stm32g4xx.c **** */
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77:Src/system_stm32g4xx.c ****
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78:Src/system_stm32g4xx.c **** #include "stm32g4xx.h"
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79:Src/system_stm32g4xx.c ****
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80:Src/system_stm32g4xx.c **** #if !defined (HSE_VALUE)
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81:Src/system_stm32g4xx.c **** #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
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82:Src/system_stm32g4xx.c **** #endif /* HSE_VALUE */
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83:Src/system_stm32g4xx.c ****
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84:Src/system_stm32g4xx.c **** #if !defined (HSI_VALUE)
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85:Src/system_stm32g4xx.c **** #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
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86:Src/system_stm32g4xx.c **** #endif /* HSI_VALUE */
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87:Src/system_stm32g4xx.c ****
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ARM GAS /tmp/ccvxi4x8.s page 3
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2023-07-02 17:09:41 +02:00
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88:Src/system_stm32g4xx.c **** /**
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89:Src/system_stm32g4xx.c **** * @}
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90:Src/system_stm32g4xx.c **** */
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91:Src/system_stm32g4xx.c ****
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92:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_TypesDefinitions
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93:Src/system_stm32g4xx.c **** * @{
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94:Src/system_stm32g4xx.c **** */
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95:Src/system_stm32g4xx.c ****
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96:Src/system_stm32g4xx.c **** /**
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97:Src/system_stm32g4xx.c **** * @}
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98:Src/system_stm32g4xx.c **** */
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99:Src/system_stm32g4xx.c ****
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100:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Defines
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101:Src/system_stm32g4xx.c **** * @{
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102:Src/system_stm32g4xx.c **** */
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103:Src/system_stm32g4xx.c ****
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104:Src/system_stm32g4xx.c **** /************************* Miscellaneous Configuration ************************/
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105:Src/system_stm32g4xx.c **** /* Note: Following vector table addresses must be defined in line with linker
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106:Src/system_stm32g4xx.c **** configuration. */
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107:Src/system_stm32g4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
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108:Src/system_stm32g4xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
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109:Src/system_stm32g4xx.c **** remap of boot address selected */
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110:Src/system_stm32g4xx.c **** /* #define USER_VECT_TAB_ADDRESS */
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111:Src/system_stm32g4xx.c ****
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112:Src/system_stm32g4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
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113:Src/system_stm32g4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
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114:Src/system_stm32g4xx.c **** in Sram else user remap will be done in Flash. */
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115:Src/system_stm32g4xx.c **** /* #define VECT_TAB_SRAM */
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116:Src/system_stm32g4xx.c **** #if defined(VECT_TAB_SRAM)
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117:Src/system_stm32g4xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
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118:Src/system_stm32g4xx.c **** This value must be a multiple of 0x200. */
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119:Src/system_stm32g4xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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120:Src/system_stm32g4xx.c **** This value must be a multiple of 0x200. */
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121:Src/system_stm32g4xx.c **** #else
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122:Src/system_stm32g4xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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123:Src/system_stm32g4xx.c **** This value must be a multiple of 0x200. */
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124:Src/system_stm32g4xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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125:Src/system_stm32g4xx.c **** This value must be a multiple of 0x200. */
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126:Src/system_stm32g4xx.c **** #endif /* VECT_TAB_SRAM */
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127:Src/system_stm32g4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
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128:Src/system_stm32g4xx.c **** /******************************************************************************/
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129:Src/system_stm32g4xx.c **** /**
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130:Src/system_stm32g4xx.c **** * @}
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131:Src/system_stm32g4xx.c **** */
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132:Src/system_stm32g4xx.c ****
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133:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Macros
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134:Src/system_stm32g4xx.c **** * @{
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135:Src/system_stm32g4xx.c **** */
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136:Src/system_stm32g4xx.c ****
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137:Src/system_stm32g4xx.c **** /**
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138:Src/system_stm32g4xx.c **** * @}
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139:Src/system_stm32g4xx.c **** */
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140:Src/system_stm32g4xx.c ****
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141:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Variables
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142:Src/system_stm32g4xx.c **** * @{
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143:Src/system_stm32g4xx.c **** */
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144:Src/system_stm32g4xx.c **** /* The SystemCoreClock variable is updated in three ways:
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ARM GAS /tmp/ccvxi4x8.s page 4
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2023-07-02 17:09:41 +02:00
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145:Src/system_stm32g4xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
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146:Src/system_stm32g4xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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147:Src/system_stm32g4xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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148:Src/system_stm32g4xx.c **** Note: If you use this function to configure the system clock; then there
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149:Src/system_stm32g4xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
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150:Src/system_stm32g4xx.c **** variable is updated automatically.
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151:Src/system_stm32g4xx.c **** */
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152:Src/system_stm32g4xx.c **** uint32_t SystemCoreClock = HSI_VALUE;
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153:Src/system_stm32g4xx.c ****
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154:Src/system_stm32g4xx.c **** const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U
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155:Src/system_stm32g4xx.c **** const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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156:Src/system_stm32g4xx.c ****
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157:Src/system_stm32g4xx.c **** /**
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158:Src/system_stm32g4xx.c **** * @}
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159:Src/system_stm32g4xx.c **** */
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160:Src/system_stm32g4xx.c ****
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161:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
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162:Src/system_stm32g4xx.c **** * @{
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163:Src/system_stm32g4xx.c **** */
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164:Src/system_stm32g4xx.c ****
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165:Src/system_stm32g4xx.c **** /**
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166:Src/system_stm32g4xx.c **** * @}
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167:Src/system_stm32g4xx.c **** */
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168:Src/system_stm32g4xx.c ****
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169:Src/system_stm32g4xx.c **** /** @addtogroup STM32G4xx_System_Private_Functions
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170:Src/system_stm32g4xx.c **** * @{
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171:Src/system_stm32g4xx.c **** */
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172:Src/system_stm32g4xx.c ****
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173:Src/system_stm32g4xx.c **** /**
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174:Src/system_stm32g4xx.c **** * @brief Setup the microcontroller system.
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175:Src/system_stm32g4xx.c **** * @param None
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176:Src/system_stm32g4xx.c **** * @retval None
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177:Src/system_stm32g4xx.c **** */
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178:Src/system_stm32g4xx.c ****
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179:Src/system_stm32g4xx.c **** void SystemInit(void)
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180:Src/system_stm32g4xx.c **** {
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29 .loc 1 180 1 view -0
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30 .cfi_startproc
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31 @ args = 0, pretend = 0, frame = 0
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32 @ frame_needed = 0, uses_anonymous_args = 0
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33 @ link register save eliminated.
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181:Src/system_stm32g4xx.c **** /* FPU settings ------------------------------------------------------------*/
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182:Src/system_stm32g4xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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183:Src/system_stm32g4xx.c **** SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
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34 .loc 1 183 5 view .LVU1
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35 .loc 1 183 8 is_stmt 0 view .LVU2
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36 0000 034A ldr r2, .L2
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37 0002 D2F88830 ldr r3, [r2, #136]
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38 .loc 1 183 16 view .LVU3
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39 0006 43F47003 orr r3, r3, #15728640
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40 000a C2F88830 str r3, [r2, #136]
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184:Src/system_stm32g4xx.c **** #endif
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185:Src/system_stm32g4xx.c ****
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186:Src/system_stm32g4xx.c **** /* Configure the Vector Table location add offset address ------------------*/
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187:Src/system_stm32g4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
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188:Src/system_stm32g4xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
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189:Src/system_stm32g4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
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2025-06-28 00:58:29 +02:00
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ARM GAS /tmp/ccvxi4x8.s page 5
|
2023-07-02 17:09:41 +02:00
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190:Src/system_stm32g4xx.c **** }
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41 .loc 1 190 1 view .LVU4
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42 000e 7047 bx lr
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43 .L3:
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44 .align 2
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45 .L2:
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46 0010 00ED00E0 .word -536810240
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47 .cfi_endproc
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48 .LFE329:
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50 .section .text.SystemCoreClockUpdate,"ax",%progbits
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51 .align 1
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52 .global SystemCoreClockUpdate
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53 .syntax unified
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54 .thumb
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55 .thumb_func
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57 SystemCoreClockUpdate:
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58 .LFB330:
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191:Src/system_stm32g4xx.c ****
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192:Src/system_stm32g4xx.c **** /**
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193:Src/system_stm32g4xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
|
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194:Src/system_stm32g4xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
|
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195:Src/system_stm32g4xx.c **** * be used by the user application to setup the SysTick timer or configure
|
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196:Src/system_stm32g4xx.c **** * other parameters.
|
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197:Src/system_stm32g4xx.c **** *
|
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198:Src/system_stm32g4xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
|
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199:Src/system_stm32g4xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
|
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200:Src/system_stm32g4xx.c **** * based on this variable will be incorrect.
|
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201:Src/system_stm32g4xx.c **** *
|
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|
202:Src/system_stm32g4xx.c **** * @note - The system frequency computed by this function is not the real
|
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|
203:Src/system_stm32g4xx.c **** * frequency in the chip. It is calculated based on the predefined
|
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|
204:Src/system_stm32g4xx.c **** * constant and the selected clock source:
|
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|
205:Src/system_stm32g4xx.c **** *
|
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|
206:Src/system_stm32g4xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
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|
207:Src/system_stm32g4xx.c **** *
|
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|
208:Src/system_stm32g4xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
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|
209:Src/system_stm32g4xx.c **** *
|
|
|
|
|
|
210:Src/system_stm32g4xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
|
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|
|
|
211:Src/system_stm32g4xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
|
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|
|
212:Src/system_stm32g4xx.c **** *
|
|
|
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|
|
213:Src/system_stm32g4xx.c **** * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
|
|
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|
|
214:Src/system_stm32g4xx.c **** * 16 MHz) but the real value may vary depending on the variations
|
|
|
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|
|
215:Src/system_stm32g4xx.c **** * in voltage and temperature.
|
|
|
|
|
|
216:Src/system_stm32g4xx.c **** *
|
|
|
|
|
|
217:Src/system_stm32g4xx.c **** * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
|
|
|
|
|
|
218:Src/system_stm32g4xx.c **** * 24 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
|
|
|
|
219:Src/system_stm32g4xx.c **** * frequency of the crystal used. Otherwise, this function may
|
|
|
|
|
|
220:Src/system_stm32g4xx.c **** * have wrong result.
|
|
|
|
|
|
221:Src/system_stm32g4xx.c **** *
|
|
|
|
|
|
222:Src/system_stm32g4xx.c **** * - The result of this function could be not correct when using fractional
|
|
|
|
|
|
223:Src/system_stm32g4xx.c **** * value for HSE crystal.
|
|
|
|
|
|
224:Src/system_stm32g4xx.c **** *
|
|
|
|
|
|
225:Src/system_stm32g4xx.c **** * @param None
|
|
|
|
|
|
226:Src/system_stm32g4xx.c **** * @retval None
|
|
|
|
|
|
227:Src/system_stm32g4xx.c **** */
|
|
|
|
|
|
228:Src/system_stm32g4xx.c **** void SystemCoreClockUpdate(void)
|
|
|
|
|
|
229:Src/system_stm32g4xx.c **** {
|
|
|
|
|
|
59 .loc 1 229 1 is_stmt 1 view -0
|
2025-06-28 00:58:29 +02:00
|
|
|
|
ARM GAS /tmp/ccvxi4x8.s page 6
|
2023-07-02 17:09:41 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
60 .cfi_startproc
|
|
|
|
|
|
61 @ args = 0, pretend = 0, frame = 0
|
|
|
|
|
|
62 @ frame_needed = 0, uses_anonymous_args = 0
|
|
|
|
|
|
63 @ link register save eliminated.
|
|
|
|
|
|
230:Src/system_stm32g4xx.c **** uint32_t tmp, pllvco, pllr, pllsource, pllm;
|
|
|
|
|
|
64 .loc 1 230 3 view .LVU6
|
|
|
|
|
|
231:Src/system_stm32g4xx.c ****
|
|
|
|
|
|
232:Src/system_stm32g4xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
|
|
|
|
|
|
233:Src/system_stm32g4xx.c **** switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
|
|
|
|
65 .loc 1 233 3 view .LVU7
|
|
|
|
|
|
66 .loc 1 233 14 is_stmt 0 view .LVU8
|
2025-01-28 19:01:22 +01:00
|
|
|
|
67 0000 1E4B ldr r3, .L11
|
2023-07-02 17:09:41 +02:00
|
|
|
|
68 0002 9B68 ldr r3, [r3, #8]
|
|
|
|
|
|
69 .loc 1 233 21 view .LVU9
|
|
|
|
|
|
70 0004 03F00C03 and r3, r3, #12
|
|
|
|
|
|
71 .loc 1 233 3 view .LVU10
|
|
|
|
|
|
72 0008 082B cmp r3, #8
|
2025-01-28 19:01:22 +01:00
|
|
|
|
73 000a 11D0 beq .L5
|
2023-07-02 17:09:41 +02:00
|
|
|
|
74 000c 0C2B cmp r3, #12
|
2025-01-28 19:01:22 +01:00
|
|
|
|
75 000e 13D0 beq .L6
|
2023-07-02 17:09:41 +02:00
|
|
|
|
76 0010 042B cmp r3, #4
|
2025-01-28 19:01:22 +01:00
|
|
|
|
77 0012 02D1 bne .L7
|
2023-07-02 17:09:41 +02:00
|
|
|
|
234:Src/system_stm32g4xx.c **** {
|
|
|
|
|
|
235:Src/system_stm32g4xx.c **** case 0x04: /* HSI used as system clock source */
|
|
|
|
|
|
236:Src/system_stm32g4xx.c **** SystemCoreClock = HSI_VALUE;
|
2025-01-28 19:01:22 +01:00
|
|
|
|
78 .loc 1 236 7 is_stmt 1 view .LVU11
|
|
|
|
|
|
79 .loc 1 236 23 is_stmt 0 view .LVU12
|
|
|
|
|
|
80 0014 1A4B ldr r3, .L11+4
|
|
|
|
|
|
81 0016 1B4A ldr r2, .L11+8
|
|
|
|
|
|
82 0018 1A60 str r2, [r3]
|
2023-07-02 17:09:41 +02:00
|
|
|
|
237:Src/system_stm32g4xx.c **** break;
|
2025-01-28 19:01:22 +01:00
|
|
|
|
83 .loc 1 237 7 is_stmt 1 view .LVU13
|
|
|
|
|
|
84 .L7:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
238:Src/system_stm32g4xx.c ****
|
|
|
|
|
|
239:Src/system_stm32g4xx.c **** case 0x08: /* HSE used as system clock source */
|
|
|
|
|
|
240:Src/system_stm32g4xx.c **** SystemCoreClock = HSE_VALUE;
|
|
|
|
|
|
241:Src/system_stm32g4xx.c **** break;
|
|
|
|
|
|
242:Src/system_stm32g4xx.c ****
|
|
|
|
|
|
243:Src/system_stm32g4xx.c **** case 0x0C: /* PLL used as system clock source */
|
|
|
|
|
|
244:Src/system_stm32g4xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
|
|
|
|
245:Src/system_stm32g4xx.c **** SYSCLK = PLL_VCO / PLLR
|
|
|
|
|
|
246:Src/system_stm32g4xx.c **** */
|
|
|
|
|
|
247:Src/system_stm32g4xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
|
|
|
|
|
248:Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
|
|
|
|
|
|
249:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
|
|
|
|
|
|
250:Src/system_stm32g4xx.c **** {
|
|
|
|
|
|
251:Src/system_stm32g4xx.c **** pllvco = (HSI_VALUE / pllm);
|
|
|
|
|
|
252:Src/system_stm32g4xx.c **** }
|
|
|
|
|
|
253:Src/system_stm32g4xx.c **** else /* HSE used as PLL clock source */
|
|
|
|
|
|
254:Src/system_stm32g4xx.c **** {
|
|
|
|
|
|
255:Src/system_stm32g4xx.c **** pllvco = (HSE_VALUE / pllm);
|
|
|
|
|
|
256:Src/system_stm32g4xx.c **** }
|
|
|
|
|
|
257:Src/system_stm32g4xx.c **** pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
|
|
|
|
|
|
258:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
|
|
|
|
|
|
259:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
|
|
|
|
|
|
260:Src/system_stm32g4xx.c **** break;
|
|
|
|
|
|
261:Src/system_stm32g4xx.c ****
|
2025-06-28 00:58:29 +02:00
|
|
|
|
ARM GAS /tmp/ccvxi4x8.s page 7
|
2025-01-28 19:01:22 +01:00
|
|
|
|
|
|
|
|
|
|
|
2023-07-02 17:09:41 +02:00
|
|
|
|
262:Src/system_stm32g4xx.c **** default:
|
|
|
|
|
|
263:Src/system_stm32g4xx.c **** break;
|
|
|
|
|
|
264:Src/system_stm32g4xx.c **** }
|
|
|
|
|
|
265:Src/system_stm32g4xx.c **** /* Compute HCLK clock frequency --------------------------------------------*/
|
|
|
|
|
|
266:Src/system_stm32g4xx.c **** /* Get HCLK prescaler */
|
|
|
|
|
|
267:Src/system_stm32g4xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
2025-01-28 19:01:22 +01:00
|
|
|
|
85 .loc 1 267 3 view .LVU14
|
|
|
|
|
|
86 .loc 1 267 28 is_stmt 0 view .LVU15
|
|
|
|
|
|
87 001a 184B ldr r3, .L11
|
|
|
|
|
|
88 001c 9B68 ldr r3, [r3, #8]
|
|
|
|
|
|
89 .loc 1 267 52 view .LVU16
|
|
|
|
|
|
90 001e C3F30313 ubfx r3, r3, #4, #4
|
|
|
|
|
|
91 .loc 1 267 22 view .LVU17
|
|
|
|
|
|
92 0022 194A ldr r2, .L11+12
|
|
|
|
|
|
93 0024 D15C ldrb r1, [r2, r3] @ zero_extendqisi2
|
|
|
|
|
|
94 .LVL0:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
268:Src/system_stm32g4xx.c **** /* HCLK clock frequency */
|
|
|
|
|
|
269:Src/system_stm32g4xx.c **** SystemCoreClock >>= tmp;
|
2025-01-28 19:01:22 +01:00
|
|
|
|
95 .loc 1 269 3 is_stmt 1 view .LVU18
|
|
|
|
|
|
96 .loc 1 269 19 is_stmt 0 view .LVU19
|
|
|
|
|
|
97 0026 164A ldr r2, .L11+4
|
|
|
|
|
|
98 0028 1368 ldr r3, [r2]
|
|
|
|
|
|
99 002a CB40 lsrs r3, r3, r1
|
|
|
|
|
|
100 002c 1360 str r3, [r2]
|
2023-07-02 17:09:41 +02:00
|
|
|
|
270:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
|
|
|
|
101 .loc 1 270 1 view .LVU20
|
|
|
|
|
|
102 002e 7047 bx lr
|
|
|
|
|
|
103 .LVL1:
|
|
|
|
|
|
104 .L5:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
240:Src/system_stm32g4xx.c **** break;
|
2025-01-28 19:01:22 +01:00
|
|
|
|
105 .loc 1 240 7 is_stmt 1 view .LVU21
|
2023-07-02 17:09:41 +02:00
|
|
|
|
240:Src/system_stm32g4xx.c **** break;
|
2025-01-28 19:01:22 +01:00
|
|
|
|
106 .loc 1 240 23 is_stmt 0 view .LVU22
|
|
|
|
|
|
107 0030 134B ldr r3, .L11+4
|
|
|
|
|
|
108 0032 164A ldr r2, .L11+16
|
|
|
|
|
|
109 0034 1A60 str r2, [r3]
|
2023-07-02 17:09:41 +02:00
|
|
|
|
241:Src/system_stm32g4xx.c ****
|
2025-01-28 19:01:22 +01:00
|
|
|
|
110 .loc 1 241 7 is_stmt 1 view .LVU23
|
|
|
|
|
|
111 0036 F0E7 b .L7
|
|
|
|
|
|
112 .L6:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
247:Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
|
2025-01-28 19:01:22 +01:00
|
|
|
|
113 .loc 1 247 7 view .LVU24
|
2023-07-02 17:09:41 +02:00
|
|
|
|
247:Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
|
2025-01-28 19:01:22 +01:00
|
|
|
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114 .loc 1 247 23 is_stmt 0 view .LVU25
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115 0038 104A ldr r2, .L11
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116 003a D368 ldr r3, [r2, #12]
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2023-07-02 17:09:41 +02:00
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247:Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
|
2025-01-28 19:01:22 +01:00
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117 .loc 1 247 17 view .LVU26
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118 003c 03F00303 and r3, r3, #3
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119 .LVL2:
|
2023-07-02 17:09:41 +02:00
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248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
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2025-01-28 19:01:22 +01:00
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120 .loc 1 248 7 is_stmt 1 view .LVU27
|
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248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
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2025-01-28 19:01:22 +01:00
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121 .loc 1 248 19 is_stmt 0 view .LVU28
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122 0040 D268 ldr r2, [r2, #12]
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2023-07-02 17:09:41 +02:00
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248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
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2025-01-28 19:01:22 +01:00
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123 .loc 1 248 49 view .LVU29
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2025-06-28 00:58:29 +02:00
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ARM GAS /tmp/ccvxi4x8.s page 8
|
2025-01-28 19:01:22 +01:00
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124 0042 C2F30312 ubfx r2, r2, #4, #4
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2023-07-02 17:09:41 +02:00
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248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
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2025-01-28 19:01:22 +01:00
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125 .loc 1 248 12 view .LVU30
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126 0046 0132 adds r2, r2, #1
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127 .LVL3:
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2023-07-02 17:09:41 +02:00
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249:Src/system_stm32g4xx.c **** {
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2025-01-28 19:01:22 +01:00
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128 .loc 1 249 7 is_stmt 1 view .LVU31
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2023-07-02 17:09:41 +02:00
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249:Src/system_stm32g4xx.c **** {
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2025-01-28 19:01:22 +01:00
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129 .loc 1 249 10 is_stmt 0 view .LVU32
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130 0048 022B cmp r3, #2
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131 004a 12D0 beq .L10
|
2023-07-02 17:09:41 +02:00
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255:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
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132 .loc 1 255 9 is_stmt 1 view .LVU33
|
2023-07-02 17:09:41 +02:00
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|
255:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
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133 .loc 1 255 16 is_stmt 0 view .LVU34
|
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134 004c 0F4B ldr r3, .L11+16
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135 .LVL4:
|
2023-07-02 17:09:41 +02:00
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|
255:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
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|
136 .loc 1 255 16 view .LVU35
|
|
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|
137 004e B3FBF2F2 udiv r2, r3, r2
|
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|
138 .LVL5:
|
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|
139 .L9:
|
2023-07-02 17:09:41 +02:00
|
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|
257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
|
2025-01-28 19:01:22 +01:00
|
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|
140 .loc 1 257 7 is_stmt 1 view .LVU36
|
2023-07-02 17:09:41 +02:00
|
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|
257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
|
2025-01-28 19:01:22 +01:00
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141 .loc 1 257 30 is_stmt 0 view .LVU37
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142 0052 0A49 ldr r1, .L11
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143 0054 CB68 ldr r3, [r1, #12]
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2023-07-02 17:09:41 +02:00
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257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
|
2025-01-28 19:01:22 +01:00
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|
144 .loc 1 257 60 view .LVU38
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|
145 0056 C3F30623 ubfx r3, r3, #8, #7
|
2023-07-02 17:09:41 +02:00
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|
257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
|
2025-01-28 19:01:22 +01:00
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|
146 .loc 1 257 14 view .LVU39
|
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|
147 005a 02FB03F3 mul r3, r2, r3
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|
148 .LVL6:
|
2023-07-02 17:09:41 +02:00
|
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|
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
|
2025-01-28 19:01:22 +01:00
|
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|
149 .loc 1 258 7 is_stmt 1 view .LVU40
|
2023-07-02 17:09:41 +02:00
|
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|
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
|
2025-01-28 19:01:22 +01:00
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150 .loc 1 258 20 is_stmt 0 view .LVU41
|
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151 005e CA68 ldr r2, [r1, #12]
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2023-07-02 17:09:41 +02:00
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258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
|
2025-01-28 19:01:22 +01:00
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|
152 .loc 1 258 50 view .LVU42
|
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|
153 0060 C2F34162 ubfx r2, r2, #25, #2
|
2023-07-02 17:09:41 +02:00
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|
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
|
2025-01-28 19:01:22 +01:00
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154 .loc 1 258 57 view .LVU43
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|
155 0064 0132 adds r2, r2, #1
|
2023-07-02 17:09:41 +02:00
|
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258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
|
2025-01-28 19:01:22 +01:00
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|
156 .loc 1 258 12 view .LVU44
|
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|
157 0066 5200 lsls r2, r2, #1
|
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|
158 .LVL7:
|
2023-07-02 17:09:41 +02:00
|
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|
259:Src/system_stm32g4xx.c **** break;
|
2025-01-28 19:01:22 +01:00
|
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|
159 .loc 1 259 7 is_stmt 1 view .LVU45
|
2023-07-02 17:09:41 +02:00
|
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|
|
259:Src/system_stm32g4xx.c **** break;
|
2025-01-28 19:01:22 +01:00
|
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|
160 .loc 1 259 31 is_stmt 0 view .LVU46
|
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|
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|
161 0068 B3FBF2F3 udiv r3, r3, r2
|
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|
162 .LVL8:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
259:Src/system_stm32g4xx.c **** break;
|
2025-06-28 00:58:29 +02:00
|
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|
ARM GAS /tmp/ccvxi4x8.s page 9
|
2025-01-28 19:01:22 +01:00
|
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|
163 .loc 1 259 23 view .LVU47
|
|
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|
|
|
164 006c 044A ldr r2, .L11+4
|
|
|
|
|
|
165 .LVL9:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
259:Src/system_stm32g4xx.c **** break;
|
2025-01-28 19:01:22 +01:00
|
|
|
|
166 .loc 1 259 23 view .LVU48
|
|
|
|
|
|
167 006e 1360 str r3, [r2]
|
2023-07-02 17:09:41 +02:00
|
|
|
|
260:Src/system_stm32g4xx.c ****
|
2025-01-28 19:01:22 +01:00
|
|
|
|
168 .loc 1 260 7 is_stmt 1 view .LVU49
|
|
|
|
|
|
169 0070 D3E7 b .L7
|
|
|
|
|
|
170 .LVL10:
|
|
|
|
|
|
171 .L10:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
251:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
|
|
|
|
172 .loc 1 251 9 view .LVU50
|
2023-07-02 17:09:41 +02:00
|
|
|
|
251:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
|
|
|
|
173 .loc 1 251 16 is_stmt 0 view .LVU51
|
|
|
|
|
|
174 0072 044B ldr r3, .L11+8
|
|
|
|
|
|
175 .LVL11:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
251:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
|
|
|
|
176 .loc 1 251 16 view .LVU52
|
|
|
|
|
|
177 0074 B3FBF2F2 udiv r2, r3, r2
|
|
|
|
|
|
178 .LVL12:
|
2023-07-02 17:09:41 +02:00
|
|
|
|
251:Src/system_stm32g4xx.c **** }
|
2025-01-28 19:01:22 +01:00
|
|
|
|
179 .loc 1 251 16 view .LVU53
|
|
|
|
|
|
180 0078 EBE7 b .L9
|
|
|
|
|
|
181 .L12:
|
|
|
|
|
|
182 007a 00BF .align 2
|
|
|
|
|
|
183 .L11:
|
|
|
|
|
|
184 007c 00100240 .word 1073876992
|
|
|
|
|
|
185 0080 00000000 .word SystemCoreClock
|
|
|
|
|
|
186 0084 0024F400 .word 16000000
|
|
|
|
|
|
187 0088 00000000 .word AHBPrescTable
|
2025-06-28 00:58:29 +02:00
|
|
|
|
188 008c 00366E01 .word 24000000
|
2025-01-28 19:01:22 +01:00
|
|
|
|
189 .cfi_endproc
|
|
|
|
|
|
190 .LFE330:
|
|
|
|
|
|
192 .global APBPrescTable
|
|
|
|
|
|
193 .section .rodata.APBPrescTable,"a"
|
|
|
|
|
|
194 .align 2
|
|
|
|
|
|
197 APBPrescTable:
|
|
|
|
|
|
198 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
|
|
|
|
|
|
198 01020304
|
|
|
|
|
|
199 .global AHBPrescTable
|
|
|
|
|
|
200 .section .rodata.AHBPrescTable,"a"
|
|
|
|
|
|
201 .align 2
|
|
|
|
|
|
204 AHBPrescTable:
|
|
|
|
|
|
205 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
|
|
|
|
|
|
205 00000000
|
|
|
|
|
|
205 01020304
|
|
|
|
|
|
205 06
|
|
|
|
|
|
206 000d 070809 .ascii "\007\010\011"
|
|
|
|
|
|
207 .global SystemCoreClock
|
|
|
|
|
|
208 .section .data.SystemCoreClock,"aw"
|
|
|
|
|
|
209 .align 2
|
|
|
|
|
|
212 SystemCoreClock:
|
|
|
|
|
|
213 0000 0024F400 .word 16000000
|
|
|
|
|
|
214 .text
|
|
|
|
|
|
215 .Letext0:
|
2025-06-28 00:58:29 +02:00
|
|
|
|
216 .file 2 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach
|
|
|
|
|
|
ARM GAS /tmp/ccvxi4x8.s page 10
|
2023-07-02 17:09:41 +02:00
|
|
|
|
|
|
|
|
|
|
|
2025-06-28 00:58:29 +02:00
|
|
|
|
217 .file 3 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/
|
2025-01-28 19:01:22 +01:00
|
|
|
|
218 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
|
|
|
|
|
|
219 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
|
|
|
|
|
|
220 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
|
2025-06-28 00:58:29 +02:00
|
|
|
|
ARM GAS /tmp/ccvxi4x8.s page 11
|
2023-07-02 17:09:41 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DEFINED SYMBOLS
|
|
|
|
|
|
*ABS*:00000000 system_stm32g4xx.c
|
2025-06-28 00:58:29 +02:00
|
|
|
|
/tmp/ccvxi4x8.s:21 .text.SystemInit:00000000 $t
|
|
|
|
|
|
/tmp/ccvxi4x8.s:27 .text.SystemInit:00000000 SystemInit
|
|
|
|
|
|
/tmp/ccvxi4x8.s:46 .text.SystemInit:00000010 $d
|
|
|
|
|
|
/tmp/ccvxi4x8.s:51 .text.SystemCoreClockUpdate:00000000 $t
|
|
|
|
|
|
/tmp/ccvxi4x8.s:57 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
|
|
|
|
|
|
/tmp/ccvxi4x8.s:184 .text.SystemCoreClockUpdate:0000007c $d
|
|
|
|
|
|
/tmp/ccvxi4x8.s:212 .data.SystemCoreClock:00000000 SystemCoreClock
|
|
|
|
|
|
/tmp/ccvxi4x8.s:204 .rodata.AHBPrescTable:00000000 AHBPrescTable
|
|
|
|
|
|
/tmp/ccvxi4x8.s:197 .rodata.APBPrescTable:00000000 APBPrescTable
|
|
|
|
|
|
/tmp/ccvxi4x8.s:194 .rodata.APBPrescTable:00000000 $d
|
|
|
|
|
|
/tmp/ccvxi4x8.s:201 .rodata.AHBPrescTable:00000000 $d
|
|
|
|
|
|
/tmp/ccvxi4x8.s:209 .data.SystemCoreClock:00000000 $d
|
2023-07-02 17:09:41 +02:00
|
|
|
|
|
|
|
|
|
|
NO UNDEFINED SYMBOLS
|
