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squeow/squeow_sw/build/stm32g4xx_hal_pwr.lst

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primo commit
2023-07-02 17:09:41 +02:00
ARM GAS /tmp/cchsYltI.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32g4xx_hal_pwr.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c"
20 .section .text.HAL_PWR_DeInit,"ax",%progbits
21 .align 1
22 .global HAL_PWR_DeInit
23 .syntax unified
24 .thumb
25 .thumb_func
27 HAL_PWR_DeInit:
28 .LFB329:
1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ******************************************************************************
3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @file stm32g4xx_hal_pwr.c
4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @author MCD Application Team
5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief PWR HAL module driver.
6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * + Initialization/de-initialization functions
9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * + Peripheral Control functions
10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *
11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ******************************************************************************
12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @attention
13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *
14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Copyright (c) 2019 STMicroelectronics.
15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * All rights reserved.
16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *
17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file
18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * in the root directory of this software component.
19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *
21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ******************************************************************************
22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #include "stm32g4xx_hal.h"
26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @addtogroup STM32G4xx_HAL_Driver
28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{
29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
ARM GAS /tmp/cchsYltI.s page 2
31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR PWR
32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief PWR HAL module driver
33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{
34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Private_Defines PWR Private Defines
42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{
43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{
47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD
49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD thresh
50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trig
51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD tri
52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @}
54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @}
58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Exported functions --------------------------------------------------------*/
64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{
67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *
72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @verbatim
73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ===============================================================================
74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ===============================================================================
76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @endverbatim
79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{
80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
ARM GAS /tmp/cchsYltI.s page 3
29 .loc 1 87 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
34 .loc 1 88 3 view .LVU1
35 0000 044B ldr r3, .L2
36 0002 9A6B ldr r2, [r3, #56]
37 0004 42F08052 orr r2, r2, #268435456
38 0008 9A63 str r2, [r3, #56]
89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
39 .loc 1 89 3 view .LVU2
40 000a 9A6B ldr r2, [r3, #56]
41 000c 22F08052 bic r2, r2, #268435456
42 0010 9A63 str r2, [r3, #56]
90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
43 .loc 1 90 1 is_stmt 0 view .LVU3
44 0012 7047 bx lr
45 .L3:
46 .align 2
47 .L2:
48 0014 00100240 .word 1073876992
49 .cfi_endproc
50 .LFE329:
52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
53 .align 1
54 .global HAL_PWR_EnableBkUpAccess
55 .syntax unified
56 .thumb
57 .thumb_func
59 HAL_PWR_EnableBkUpAccess:
60 .LFB330:
91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable access to the backup domain
94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * (RTC registers, RTC backup data registers).
95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note After reset, the backup domain is protected against
96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * possible unwanted write accesses.
97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * In order to set or modify the RTC clock, the backup domain access must be
99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * disabled.
100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * back-up domain.
102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
61 .loc 1 105 1 is_stmt 1 view -0
62 .cfi_startproc
63 @ args = 0, pretend = 0, frame = 0
64 @ frame_needed = 0, uses_anonymous_args = 0
65 @ link register save eliminated.
106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP);
66 .loc 1 106 3 view .LVU5
67 0000 024A ldr r2, .L5
68 0002 1368 ldr r3, [r2]
ARM GAS /tmp/cchsYltI.s page 4
69 0004 43F48073 orr r3, r3, #256
70 0008 1360 str r3, [r2]
107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
71 .loc 1 107 1 is_stmt 0 view .LVU6
72 000a 7047 bx lr
73 .L6:
74 .align 2
75 .L5:
76 000c 00700040 .word 1073770496
77 .cfi_endproc
78 .LFE330:
80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
81 .align 1
82 .global HAL_PWR_DisableBkUpAccess
83 .syntax unified
84 .thumb
85 .thumb_func
87 HAL_PWR_DisableBkUpAccess:
88 .LFB331:
108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable access to the backup domain
111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * (RTC registers, RTC backup data registers).
112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
89 .loc 1 115 1 is_stmt 1 view -0
90 .cfi_startproc
91 @ args = 0, pretend = 0, frame = 0
92 @ frame_needed = 0, uses_anonymous_args = 0
93 @ link register save eliminated.
116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
94 .loc 1 116 3 view .LVU8
95 0000 024A ldr r2, .L8
96 0002 1368 ldr r3, [r2]
97 0004 23F48073 bic r3, r3, #256
98 0008 1360 str r3, [r2]
117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
99 .loc 1 117 1 is_stmt 0 view .LVU9
100 000a 7047 bx lr
101 .L9:
102 .align 2
103 .L8:
104 000c 00700040 .word 1073770496
105 .cfi_endproc
106 .LFE331:
108 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits
109 .align 1
110 .global HAL_PWR_ConfigPVD
111 .syntax unified
112 .thumb
113 .thumb_func
115 HAL_PWR_ConfigPVD:
116 .LVL0:
117 .LFB332:
118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
ARM GAS /tmp/cchsYltI.s page 5
119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @}
124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Low Power modes configuration functions
130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *
131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @verbatim
132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ===============================================================================
134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ##### Peripheral Control functions #####
135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ===============================================================================
136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** PVD configuration ***
139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =========================
140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a
142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI
146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through
147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PVD_EXTI_ENABLE_IT() macro.
148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode.
149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** WakeUp pin configuration ***
152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ================================
153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The polarity of these pins can be set to configure event detection on high
156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** level (rising edge) or low level (falling edge).
157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Low Power modes configuration ***
161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =====================================
162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The devices feature 8 low-power modes:
164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regul
165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulato
166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator of
167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power reg
169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserv
170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power
171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Low-power run mode ***
175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ==========================
ARM GAS /tmp/cchsYltI.s page 6
176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry: (from main run mode)
178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the syst
179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Exit:
181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMod
182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** then can the system clock frequency be increased above 2 MHz.
183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Sleep mode / Low-power sleep mode ***
186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =========================================
187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry:
189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** in specifying whether or not the regulator is forced to low-power mode and if exit is int
191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** In the latter case, the system clock frequency must have been decreased below 2 MHz befor
194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFI Exit:
198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** controller (NVIC) or any wake-up event.
200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFE Exit:
202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any wake-up event such as an EXTI line configured in event mode.
203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** the MCU is in Low-power Run mode.
206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Stop 0, Stop 1 modes ***
208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ===============================
209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry:
211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Stop 0, Stop 1 modes are entered through the following API's:
212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or fo
213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_MAINREGULATOR_ON
215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_LOWPOWERREGULATOR_ON
216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFI Exit:
221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** when programmed in wakeup mode.
224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) WFE Exit:
225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Event mode.
226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run m
229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** depending on the LPR bit setting.
230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Standby mode ***
232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ====================
ARM GAS /tmp/cchsYltI.s page 7
233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Standby mode offers two options:
235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low
236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC b
237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** and Standby circuitry.
238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disa
239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM and register contents are lost except for the RTC registers, RTC backup registers
240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** and Standby circuitry.
241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Entry:
243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM1 and register contents are lost except for registers in the Backup domain and
245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3
246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetentio
247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** to set RRS bit.
248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) Exit:
250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** external reset in NRST pin, IWDG reset.
252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] After waking up from Standby mode, program execution restarts in the same way as afte
254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Shutdown mode ***
257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** ======================
258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** In Shutdown mode,
260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SRAM and registers contents are lost except for backup domain registers.
262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Entry:
264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) Exit:
267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** external reset in NRST pin.
269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..] After waking up from Shutdown mode, program execution restarts in the same way as aft
271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** =============================================
275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** [..]
276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** Wakeup event, a tamper event or a time-stamp event, without depending on
278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** an external interrupt (Auto-wakeup mode).
279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the
288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
ARM GAS /tmp/cchsYltI.s page 8
290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer
292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** @endverbatim
294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @{
295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * configuration information.
303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for
304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * more details about the voltage thresholds corresponding to each
305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * detection level.
306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
118 .loc 1 309 1 is_stmt 1 view -0
119 .cfi_startproc
120 @ args = 0, pretend = 0, frame = 0
121 @ frame_needed = 0, uses_anonymous_args = 0
122 @ link register save eliminated.
310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */
311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
123 .loc 1 311 3 view .LVU11
312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
124 .loc 1 312 3 view .LVU12
313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set PLS bits according to PVDLevel value */
315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
125 .loc 1 315 3 view .LVU13
126 0000 1E4A ldr r2, .L15
127 0002 5368 ldr r3, [r2, #4]
128 0004 23F00E03 bic r3, r3, #14
129 0008 0168 ldr r1, [r0]
130 000a 0B43 orrs r3, r3, r1
131 000c 5360 str r3, [r2, #4]
316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */
318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
132 .loc 1 318 3 view .LVU14
133 000e 1C4B ldr r3, .L15+4
134 0010 5A68 ldr r2, [r3, #4]
135 0012 22F48032 bic r2, r2, #65536
136 0016 5A60 str r2, [r3, #4]
319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT();
137 .loc 1 319 3 view .LVU15
138 0018 1A68 ldr r2, [r3]
139 001a 22F48032 bic r2, r2, #65536
140 001e 1A60 str r2, [r3]
320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
141 .loc 1 320 3 view .LVU16
142 0020 DA68 ldr r2, [r3, #12]
143 0022 22F48032 bic r2, r2, #65536
ARM GAS /tmp/cchsYltI.s page 9
144 0026 DA60 str r2, [r3, #12]
321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
145 .loc 1 321 3 view .LVU17
146 0028 9A68 ldr r2, [r3, #8]
147 002a 22F48032 bic r2, r2, #65536
148 002e 9A60 str r2, [r3, #8]
322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Configure interrupt mode */
324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
149 .loc 1 324 3 view .LVU18
150 .loc 1 324 17 is_stmt 0 view .LVU19
151 0030 4368 ldr r3, [r0, #4]
152 .loc 1 324 5 view .LVU20
153 0032 13F4803F tst r3, #65536
154 0036 04D0 beq .L11
325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT();
155 .loc 1 326 5 is_stmt 1 view .LVU21
156 0038 114A ldr r2, .L15+4
157 003a 1368 ldr r3, [r2]
158 003c 43F48033 orr r3, r3, #65536
159 0040 1360 str r3, [r2]
160 .L11:
327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Configure event mode */
330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
161 .loc 1 330 3 view .LVU22
162 .loc 1 330 17 is_stmt 0 view .LVU23
163 0042 4368 ldr r3, [r0, #4]
164 .loc 1 330 5 view .LVU24
165 0044 13F4003F tst r3, #131072
166 0048 04D0 beq .L12
331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
167 .loc 1 332 5 is_stmt 1 view .LVU25
168 004a 0D4A ldr r2, .L15+4
169 004c 5368 ldr r3, [r2, #4]
170 004e 43F48033 orr r3, r3, #65536
171 0052 5360 str r3, [r2, #4]
172 .L12:
333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Configure the edge */
336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
173 .loc 1 336 3 view .LVU26
174 .loc 1 336 17 is_stmt 0 view .LVU27
175 0054 4368 ldr r3, [r0, #4]
176 .loc 1 336 5 view .LVU28
177 0056 13F0010F tst r3, #1
178 005a 04D0 beq .L13
337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
179 .loc 1 338 5 is_stmt 1 view .LVU29
180 005c 084A ldr r2, .L15+4
181 005e 9368 ldr r3, [r2, #8]
182 0060 43F48033 orr r3, r3, #65536
ARM GAS /tmp/cchsYltI.s page 10
183 0064 9360 str r3, [r2, #8]
184 .L13:
339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
185 .loc 1 341 3 view .LVU30
186 .loc 1 341 17 is_stmt 0 view .LVU31
187 0066 4368 ldr r3, [r0, #4]
188 .loc 1 341 5 view .LVU32
189 0068 13F0020F tst r3, #2
190 006c 04D0 beq .L14
342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
191 .loc 1 343 5 is_stmt 1 view .LVU33
192 006e 044A ldr r2, .L15+4
193 0070 D368 ldr r3, [r2, #12]
194 0072 43F48033 orr r3, r3, #65536
195 0076 D360 str r3, [r2, #12]
196 .L14:
344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** return HAL_OK;
197 .loc 1 346 3 view .LVU34
347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
198 .loc 1 347 1 is_stmt 0 view .LVU35
199 0078 0020 movs r0, #0
200 .LVL1:
201 .loc 1 347 1 view .LVU36
202 007a 7047 bx lr
203 .L16:
204 .align 2
205 .L15:
206 007c 00700040 .word 1073770496
207 0080 00040140 .word 1073808384
208 .cfi_endproc
209 .LFE332:
211 .section .text.HAL_PWR_EnablePVD,"ax",%progbits
212 .align 1
213 .global HAL_PWR_EnablePVD
214 .syntax unified
215 .thumb
216 .thumb_func
218 HAL_PWR_EnablePVD:
219 .LFB333:
348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable the Power Voltage Detector (PVD).
352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void)
355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
220 .loc 1 355 1 is_stmt 1 view -0
221 .cfi_startproc
222 @ args = 0, pretend = 0, frame = 0
223 @ frame_needed = 0, uses_anonymous_args = 0
224 @ link register save eliminated.
ARM GAS /tmp/cchsYltI.s page 11
356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(PWR->CR2, PWR_CR2_PVDE);
225 .loc 1 356 3 view .LVU38
226 0000 024A ldr r2, .L18
227 0002 5368 ldr r3, [r2, #4]
228 0004 43F00103 orr r3, r3, #1
229 0008 5360 str r3, [r2, #4]
357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
230 .loc 1 357 1 is_stmt 0 view .LVU39
231 000a 7047 bx lr
232 .L19:
233 .align 2
234 .L18:
235 000c 00700040 .word 1073770496
236 .cfi_endproc
237 .LFE333:
239 .section .text.HAL_PWR_DisablePVD,"ax",%progbits
240 .align 1
241 .global HAL_PWR_DisablePVD
242 .syntax unified
243 .thumb
244 .thumb_func
246 HAL_PWR_DisablePVD:
247 .LFB334:
358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable the Power Voltage Detector (PVD).
361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void)
364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
248 .loc 1 364 1 is_stmt 1 view -0
249 .cfi_startproc
250 @ args = 0, pretend = 0, frame = 0
251 @ frame_needed = 0, uses_anonymous_args = 0
252 @ link register save eliminated.
365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
253 .loc 1 365 3 view .LVU41
254 0000 024A ldr r2, .L21
255 0002 5368 ldr r3, [r2, #4]
256 0004 23F00103 bic r3, r3, #1
257 0008 5360 str r3, [r2, #4]
366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
258 .loc 1 366 1 is_stmt 0 view .LVU42
259 000a 7047 bx lr
260 .L22:
261 .align 2
262 .L21:
263 000c 00700040 .word 1073770496
264 .cfi_endproc
265 .LFE334:
267 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
268 .align 1
269 .global HAL_PWR_EnableWakeUpPin
270 .syntax unified
271 .thumb
272 .thumb_func
274 HAL_PWR_EnableWakeUpPin:
ARM GAS /tmp/cchsYltI.s page 12
275 .LVL2:
276 .LFB335:
367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable the WakeUp PINx functionality.
373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following legacy values which set the default polarity
375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * i.e. detection on high level (rising edge):
376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAK
377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** *
378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * or one of the following value where the user can explicitly specify the enabled pin and
379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the chosen polarity:
380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
277 .loc 1 389 1 is_stmt 1 view -0
278 .cfi_startproc
279 @ args = 0, pretend = 0, frame = 0
280 @ frame_needed = 0, uses_anonymous_args = 0
281 @ link register save eliminated.
390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
282 .loc 1 390 3 view .LVU44
391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Specifies the Wake-Up pin polarity for the event detection
393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (rising or falling edge) */
394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_S
283 .loc 1 394 3 view .LVU45
284 0000 064A ldr r2, .L24
285 0002 D368 ldr r3, [r2, #12]
286 0004 00F01F01 and r1, r0, #31
287 0008 23EA0103 bic r3, r3, r1
288 000c 43EA5010 orr r0, r3, r0, lsr #5
289 .LVL3:
290 .loc 1 394 3 is_stmt 0 view .LVU46
291 0010 D060 str r0, [r2, #12]
395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Enable wake-up pin */
397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
292 .loc 1 397 3 is_stmt 1 view .LVU47
293 0012 9368 ldr r3, [r2, #8]
294 0014 1943 orrs r1, r1, r3
295 0016 9160 str r1, [r2, #8]
398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
296 .loc 1 400 1 is_stmt 0 view .LVU48
297 0018 7047 bx lr
ARM GAS /tmp/cchsYltI.s page 13
298 .L25:
299 001a 00BF .align 2
300 .L24:
301 001c 00700040 .word 1073770496
302 .cfi_endproc
303 .LFE335:
305 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
306 .align 1
307 .global HAL_PWR_DisableWakeUpPin
308 .syntax unified
309 .thumb
310 .thumb_func
312 HAL_PWR_DisableWakeUpPin:
313 .LVL4:
314 .LFB336:
401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable the WakeUp PINx functionality.
404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values:
406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAK
407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
315 .loc 1 410 1 is_stmt 1 view -0
316 .cfi_startproc
317 @ args = 0, pretend = 0, frame = 0
318 @ frame_needed = 0, uses_anonymous_args = 0
319 @ link register save eliminated.
411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
320 .loc 1 411 3 view .LVU50
412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
321 .loc 1 413 3 view .LVU51
322 0000 034A ldr r2, .L27
323 0002 9368 ldr r3, [r2, #8]
324 0004 00F01F00 and r0, r0, #31
325 .LVL5:
326 .loc 1 413 3 is_stmt 0 view .LVU52
327 0008 23EA0003 bic r3, r3, r0
328 000c 9360 str r3, [r2, #8]
414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
329 .loc 1 414 1 view .LVU53
330 000e 7047 bx lr
331 .L28:
332 .align 2
333 .L27:
334 0010 00700040 .word 1073770496
335 .cfi_endproc
336 .LFE336:
338 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
339 .align 1
340 .global HAL_PWR_EnterSLEEPMode
341 .syntax unified
342 .thumb
343 .thumb_func
ARM GAS /tmp/cchsYltI.s page 14
345 HAL_PWR_EnterSLEEPMode:
346 .LVL6:
347 .LFB337:
415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enter Sleep or Low-power Sleep mode.
419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values:
422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode
424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Additionally, the clock frequency must be reduced below 2 MHz.
429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * be done before calling HAL_PWR_EnterSLEEPMode() API.
431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values:
435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instructio
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instructio
437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the interrupt wake up source.
439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
348 .loc 1 442 1 is_stmt 1 view -0
349 .cfi_startproc
350 @ args = 0, pretend = 0, frame = 0
351 @ frame_needed = 0, uses_anonymous_args = 0
352 .loc 1 442 1 is_stmt 0 view .LVU55
353 0000 10B5 push {r4, lr}
354 .LCFI0:
355 .cfi_def_cfa_offset 8
356 .cfi_offset 4, -8
357 .cfi_offset 14, -4
358 0002 0C46 mov r4, r1
443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */
444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
359 .loc 1 444 3 is_stmt 1 view .LVU56
445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
360 .loc 1 445 3 view .LVU57
446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set Regulator parameter */
448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if (Regulator == PWR_MAINREGULATOR_ON)
361 .loc 1 448 3 view .LVU58
362 .loc 1 448 6 is_stmt 0 view .LVU59
363 0004 90B9 cbnz r0, .L30
449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* If in low-power run mode at this point, exit it */
451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
364 .loc 1 451 5 is_stmt 1 view .LVU60
ARM GAS /tmp/cchsYltI.s page 15
365 .loc 1 451 9 is_stmt 0 view .LVU61
366 0006 0E4B ldr r3, .L37
367 0008 5B69 ldr r3, [r3, #20]
368 .loc 1 451 8 view .LVU62
369 000a 13F4007F tst r3, #512
370 000e 0AD1 bne .L35
371 .LVL7:
372 .L31:
452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** (void)HAL_PWREx_DisableLowPowerRunMode();
454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Regulator now in main mode. */
456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** else
458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* If in run mode, first move to low-power run mode.
460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** The system clock frequency must be below 2 MHz at this point. */
461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U)
462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_PWREx_EnableLowPowerRunMode();
464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
373 .loc 1 468 3 is_stmt 1 view .LVU63
374 0010 0C4A ldr r2, .L37+4
375 0012 1369 ldr r3, [r2, #16]
376 0014 23F00403 bic r3, r3, #4
377 0018 1361 str r3, [r2, #16]
469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
378 .loc 1 471 3 view .LVU64
379 .loc 1 471 5 is_stmt 0 view .LVU65
380 001a 012C cmp r4, #1
381 001c 0ED0 beq .L36
472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Request Wait For Interrupt */
474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFI();
475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** else
477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Request Wait For Event */
479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __SEV();
382 .loc 1 479 5 is_stmt 1 view .LVU66
383 .syntax unified
384 @ 479 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
385 001e 40BF sev
386 @ 0 "" 2
480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFE();
387 .loc 1 480 5 view .LVU67
388 @ 480 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
389 0020 20BF wfe
390 @ 0 "" 2
481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFE();
391 .loc 1 481 5 view .LVU68
ARM GAS /tmp/cchsYltI.s page 16
392 @ 481 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
393 0022 20BF wfe
394 @ 0 "" 2
395 .thumb
396 .syntax unified
397 .L29:
482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
398 .loc 1 484 1 is_stmt 0 view .LVU69
399 0024 10BD pop {r4, pc}
400 .LVL8:
401 .L35:
453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
402 .loc 1 453 7 is_stmt 1 view .LVU70
453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
403 .loc 1 453 13 is_stmt 0 view .LVU71
404 0026 FFF7FEFF bl HAL_PWREx_DisableLowPowerRunMode
405 .LVL9:
453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
406 .loc 1 453 13 view .LVU72
407 002a F1E7 b .L31
408 .LVL10:
409 .L30:
461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
410 .loc 1 461 5 is_stmt 1 view .LVU73
461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
411 .loc 1 461 9 is_stmt 0 view .LVU74
412 002c 044B ldr r3, .L37
413 002e 5B69 ldr r3, [r3, #20]
461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
414 .loc 1 461 8 view .LVU75
415 0030 13F4007F tst r3, #512
416 0034 ECD1 bne .L31
463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
417 .loc 1 463 7 is_stmt 1 view .LVU76
418 0036 FFF7FEFF bl HAL_PWREx_EnableLowPowerRunMode
419 .LVL11:
463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
420 .loc 1 463 7 is_stmt 0 view .LVU77
421 003a E9E7 b .L31
422 .L36:
474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
423 .loc 1 474 5 is_stmt 1 view .LVU78
424 .syntax unified
425 @ 474 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
426 003c 30BF wfi
427 @ 0 "" 2
428 .thumb
429 .syntax unified
430 003e F1E7 b .L29
431 .L38:
432 .align 2
433 .L37:
434 0040 00700040 .word 1073770496
435 0044 00ED00E0 .word -536810240
436 .cfi_endproc
ARM GAS /tmp/cchsYltI.s page 17
437 .LFE337:
439 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
440 .align 1
441 .global HAL_PWR_EnterSTOPMode
442 .syntax unified
443 .thumb
444 .thumb_func
446 HAL_PWR_EnterSTOPMode:
447 .LVL12:
448 .LFB338:
485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enter Stop mode
489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note All clocks in the VCORE domain are stopped; the PLL,
493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capabilit
494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the H
495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is pr
496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * only to the peripheral requesting it.
497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * SRAM1, SRAM2 and register contents are preserved.
498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * The BOR is available.
499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Sto
500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock.
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode (Stop 1), an additional
503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * startup delay is incurred when waking up.
504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * is higher although the startup time is reduced.
506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Stop mode.
507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values:
508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * This parameter can be one of the following values:
512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
449 .loc 1 517 1 view -0
450 .cfi_startproc
451 @ args = 0, pretend = 0, frame = 0
452 @ frame_needed = 0, uses_anonymous_args = 0
453 .loc 1 517 1 is_stmt 0 view .LVU80
454 0000 08B5 push {r3, lr}
455 .LCFI1:
456 .cfi_def_cfa_offset 8
457 .cfi_offset 3, -8
458 .cfi_offset 14, -4
518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Check the parameters */
519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
459 .loc 1 519 3 is_stmt 1 view .LVU81
520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
ARM GAS /tmp/cchsYltI.s page 18
521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** if(Regulator == PWR_LOWPOWERREGULATOR_ON)
460 .loc 1 521 3 view .LVU82
461 .loc 1 521 5 is_stmt 0 view .LVU83
462 0002 B0F5804F cmp r0, #16384
463 0006 03D0 beq .L43
522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_PWREx_EnterSTOP1Mode(STOPEntry);
524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** else
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** HAL_PWREx_EnterSTOP0Mode(STOPEntry);
464 .loc 1 527 5 is_stmt 1 view .LVU84
465 0008 0846 mov r0, r1
466 .LVL13:
467 .loc 1 527 5 is_stmt 0 view .LVU85
468 000a FFF7FEFF bl HAL_PWREx_EnterSTOP0Mode
469 .LVL14:
470 .L39:
528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
471 .loc 1 529 1 view .LVU86
472 000e 08BD pop {r3, pc}
473 .LVL15:
474 .L43:
523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
475 .loc 1 523 5 is_stmt 1 view .LVU87
476 0010 0846 mov r0, r1
477 .LVL16:
523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
478 .loc 1 523 5 is_stmt 0 view .LVU88
479 0012 FFF7FEFF bl HAL_PWREx_EnterSTOP1Mode
480 .LVL17:
523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
481 .loc 1 523 5 view .LVU89
482 0016 FAE7 b .L39
483 .cfi_endproc
484 .LFE338:
486 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
487 .align 1
488 .global HAL_PWR_EnterSTANDBYMode
489 .syntax unified
490 .thumb
491 .thumb_func
493 HAL_PWR_EnterSTANDBYMode:
494 .LFB339:
530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enter Standby mode.
533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched
534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * off. The voltage regulator is disabled, except when SRAM2 content is preserved
535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * in which case the regulator is in low-power mode.
536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * SRAM1 and register contents are lost except for registers in the Backup domain and
537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 regis
538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() A
539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * to set RRS bit.
540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * The BOR is available.
541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog s
ARM GAS /tmp/cchsYltI.s page 19
542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull
543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disab
544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * same.
545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * These states are effective in Standby mode only if APC bit is set through
546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * HAL_PWREx_EnablePullUpPullDownConfig() API.
547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
495 .loc 1 550 1 is_stmt 1 view -0
496 .cfi_startproc
497 @ args = 0, pretend = 0, frame = 0
498 @ frame_needed = 0, uses_anonymous_args = 0
499 @ link register save eliminated.
551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set Stand-by mode */
552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
500 .loc 1 552 3 view .LVU91
501 0000 064A ldr r2, .L45
502 0002 1368 ldr r3, [r2]
503 0004 23F00703 bic r3, r3, #7
504 0008 43F00303 orr r3, r3, #3
505 000c 1360 str r3, [r2]
553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
506 .loc 1 555 3 view .LVU92
507 000e 044A ldr r2, .L45+4
508 0010 1369 ldr r3, [r2, #16]
509 0012 43F00403 orr r3, r3, #4
510 0016 1361 str r3, [r2, #16]
556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #if defined ( __CC_ARM)
559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __force_stores();
560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** #endif
561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Request Wait For Interrupt */
562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __WFI();
511 .loc 1 562 3 view .LVU93
512 .syntax unified
513 @ 562 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c" 1
514 0018 30BF wfi
515 @ 0 "" 2
563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
516 .loc 1 563 1 is_stmt 0 view .LVU94
517 .thumb
518 .syntax unified
519 001a 7047 bx lr
520 .L46:
521 .align 2
522 .L45:
523 001c 00700040 .word 1073770496
524 0020 00ED00E0 .word -536810240
525 .cfi_endproc
526 .LFE339:
528 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
529 .align 1
530 .global HAL_PWR_EnableSleepOnExit
ARM GAS /tmp/cchsYltI.s page 20
531 .syntax unified
532 .thumb
533 .thumb_func
535 HAL_PWR_EnableSleepOnExit:
536 .LFB340:
564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * interruptions handling.
573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
537 .loc 1 576 1 is_stmt 1 view -0
538 .cfi_startproc
539 @ args = 0, pretend = 0, frame = 0
540 @ frame_needed = 0, uses_anonymous_args = 0
541 @ link register save eliminated.
577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
542 .loc 1 578 3 view .LVU96
543 0000 024A ldr r2, .L48
544 0002 1369 ldr r3, [r2, #16]
545 0004 43F00203 orr r3, r3, #2
546 0008 1361 str r3, [r2, #16]
579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
547 .loc 1 579 1 is_stmt 0 view .LVU97
548 000a 7047 bx lr
549 .L49:
550 .align 2
551 .L48:
552 000c 00ED00E0 .word -536810240
553 .cfi_endproc
554 .LFE340:
556 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
557 .align 1
558 .global HAL_PWR_DisableSleepOnExit
559 .syntax unified
560 .thumb
561 .thumb_func
563 HAL_PWR_DisableSleepOnExit:
564 .LFB341:
580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
ARM GAS /tmp/cchsYltI.s page 21
565 .loc 1 589 1 is_stmt 1 view -0
566 .cfi_startproc
567 @ args = 0, pretend = 0, frame = 0
568 @ frame_needed = 0, uses_anonymous_args = 0
569 @ link register save eliminated.
590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
570 .loc 1 591 3 view .LVU99
571 0000 024A ldr r2, .L51
572 0002 1369 ldr r3, [r2, #16]
573 0004 23F00203 bic r3, r3, #2
574 0008 1361 str r3, [r2, #16]
592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
575 .loc 1 592 1 is_stmt 0 view .LVU100
576 000a 7047 bx lr
577 .L52:
578 .align 2
579 .L51:
580 000c 00ED00E0 .word -536810240
581 .cfi_endproc
582 .LFE341:
584 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
585 .align 1
586 .global HAL_PWR_EnableSEVOnPend
587 .syntax unified
588 .thumb
589 .thumb_func
591 HAL_PWR_EnableSEVOnPend:
592 .LFB342:
593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Enable CORTEX M4 SEVONPEND bit.
598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
593 .loc 1 603 1 is_stmt 1 view -0
594 .cfi_startproc
595 @ args = 0, pretend = 0, frame = 0
596 @ frame_needed = 0, uses_anonymous_args = 0
597 @ link register save eliminated.
604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
598 .loc 1 605 3 view .LVU102
599 0000 024A ldr r2, .L54
600 0002 1369 ldr r3, [r2, #16]
601 0004 43F01003 orr r3, r3, #16
602 0008 1361 str r3, [r2, #16]
606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
603 .loc 1 606 1 is_stmt 0 view .LVU103
604 000a 7047 bx lr
605 .L55:
606 .align 2
ARM GAS /tmp/cchsYltI.s page 22
607 .L54:
608 000c 00ED00E0 .word -536810240
609 .cfi_endproc
610 .LFE342:
612 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
613 .align 1
614 .global HAL_PWR_DisableSEVOnPend
615 .syntax unified
616 .thumb
617 .thumb_func
619 HAL_PWR_DisableSEVOnPend:
620 .LFB343:
607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief Disable CORTEX M4 SEVONPEND bit.
611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
621 .loc 1 616 1 is_stmt 1 view -0
622 .cfi_startproc
623 @ args = 0, pretend = 0, frame = 0
624 @ frame_needed = 0, uses_anonymous_args = 0
625 @ link register save eliminated.
617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
626 .loc 1 618 3 view .LVU105
627 0000 024A ldr r2, .L57
628 0002 1369 ldr r3, [r2, #16]
629 0004 23F01003 bic r3, r3, #16
630 0008 1361 str r3, [r2, #16]
619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
631 .loc 1 619 1 is_stmt 0 view .LVU106
632 000a 7047 bx lr
633 .L58:
634 .align 2
635 .L57:
636 000c 00ED00E0 .word -536810240
637 .cfi_endproc
638 .LFE343:
640 .section .text.HAL_PWR_PVDCallback,"ax",%progbits
641 .align 1
642 .weak HAL_PWR_PVDCallback
643 .syntax unified
644 .thumb
645 .thumb_func
647 HAL_PWR_PVDCallback:
648 .LFB344:
620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ****
625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /**
ARM GAS /tmp/cchsYltI.s page 23
626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @brief PWR PVD interrupt callback
627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** * @retval None
628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void)
630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** {
649 .loc 1 630 1 is_stmt 1 view -0
650 .cfi_startproc
651 @ args = 0, pretend = 0, frame = 0
652 @ frame_needed = 0, uses_anonymous_args = 0
653 @ link register save eliminated.
631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** /* NOTE : This function should not be modified; when the callback is needed,
632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** the HAL_PWR_PVDCallback can be implemented in the user file
633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** */
634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c **** }
654 .loc 1 634 1 view .LVU108
655 0000 7047 bx lr
656 .cfi_endproc
657 .LFE344:
659 .text
660 .Letext0:
661 .file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
662 .file 3 "Drivers/CMSIS/Include/core_cm4.h"
663 .file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
664 .file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
665 .file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"
666 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
ARM GAS /tmp/cchsYltI.s page 24
DEFINED SYMBOLS
*ABS*:00000000 stm32g4xx_hal_pwr.c
/tmp/cchsYltI.s:21 .text.HAL_PWR_DeInit:00000000 $t
/tmp/cchsYltI.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
/tmp/cchsYltI.s:48 .text.HAL_PWR_DeInit:00000014 $d
/tmp/cchsYltI.s:53 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
/tmp/cchsYltI.s:59 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
/tmp/cchsYltI.s:76 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
/tmp/cchsYltI.s:81 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
/tmp/cchsYltI.s:87 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
/tmp/cchsYltI.s:104 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
/tmp/cchsYltI.s:109 .text.HAL_PWR_ConfigPVD:00000000 $t
/tmp/cchsYltI.s:115 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD
/tmp/cchsYltI.s:206 .text.HAL_PWR_ConfigPVD:0000007c $d
/tmp/cchsYltI.s:212 .text.HAL_PWR_EnablePVD:00000000 $t
/tmp/cchsYltI.s:218 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD
/tmp/cchsYltI.s:235 .text.HAL_PWR_EnablePVD:0000000c $d
/tmp/cchsYltI.s:240 .text.HAL_PWR_DisablePVD:00000000 $t
/tmp/cchsYltI.s:246 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD
/tmp/cchsYltI.s:263 .text.HAL_PWR_DisablePVD:0000000c $d
/tmp/cchsYltI.s:268 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
/tmp/cchsYltI.s:274 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
/tmp/cchsYltI.s:301 .text.HAL_PWR_EnableWakeUpPin:0000001c $d
/tmp/cchsYltI.s:306 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
/tmp/cchsYltI.s:312 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
/tmp/cchsYltI.s:334 .text.HAL_PWR_DisableWakeUpPin:00000010 $d
/tmp/cchsYltI.s:339 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
/tmp/cchsYltI.s:345 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
/tmp/cchsYltI.s:434 .text.HAL_PWR_EnterSLEEPMode:00000040 $d
/tmp/cchsYltI.s:440 .text.HAL_PWR_EnterSTOPMode:00000000 $t
/tmp/cchsYltI.s:446 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
/tmp/cchsYltI.s:487 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
/tmp/cchsYltI.s:493 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
/tmp/cchsYltI.s:523 .text.HAL_PWR_EnterSTANDBYMode:0000001c $d
/tmp/cchsYltI.s:529 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
/tmp/cchsYltI.s:535 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
/tmp/cchsYltI.s:552 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
/tmp/cchsYltI.s:557 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
/tmp/cchsYltI.s:563 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
/tmp/cchsYltI.s:580 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
/tmp/cchsYltI.s:585 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
/tmp/cchsYltI.s:591 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
/tmp/cchsYltI.s:608 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
/tmp/cchsYltI.s:613 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
/tmp/cchsYltI.s:619 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
/tmp/cchsYltI.s:636 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
/tmp/cchsYltI.s:641 .text.HAL_PWR_PVDCallback:00000000 $t
/tmp/cchsYltI.s:647 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback
UNDEFINED SYMBOLS
HAL_PWREx_DisableLowPowerRunMode
HAL_PWREx_EnableLowPowerRunMode
HAL_PWREx_EnterSTOP0Mode
HAL_PWREx_EnterSTOP1Mode
Reference in New Issue Copy Permalink