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squeow/squeow_sw/build/stm32g4xx_hal_uart_ex.lst

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primo commit
2023-07-02 17:09:41 +02:00
ARM GAS /tmp/ccEfj1JP.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32g4xx_hal_uart_ex.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c"
20 .section .text.UARTEx_Wakeup_AddressConfig,"ax",%progbits
21 .align 1
22 .syntax unified
23 .thumb
24 .thumb_func
26 UARTEx_Wakeup_AddressConfig:
27 .LVL0:
28 .LFB344:
1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ******************************************************************************
3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @file stm32g4xx_hal_uart_ex.c
4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @author MCD Application Team
5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended UART HAL module driver.
6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This file provides firmware functions to manage the following extended
7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * + Initialization and de-initialization functions
9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * + Peripheral Control functions
10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ******************************************************************************
13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @attention
14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * Copyright (c) 2019 STMicroelectronics.
16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * All rights reserved.
17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This software is licensed under terms that can be found in the LICENSE file
19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * in the root directory of this software component.
20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ******************************************************************************
23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim
24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ==============================================================================
25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### UART peripheral extended features #####
26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ==============================================================================
27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Declare a UART_HandleTypeDef handle structure.
29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) For the UART RS485 Driver Enable mode, initialize the UART registers
ARM GAS /tmp/ccEfj1JP.s page 2
31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** by calling the HAL_RS485Ex_Init() API.
32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** starting RX/TX transfers. Also RX/TX FIFO thresholds must be
37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** configured prior starting RX/TX transfers.
38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim
40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ******************************************************************************
41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Includes ------------------------------------------------------------------*/
44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #include "stm32g4xx_hal.h"
45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver
47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx UARTEx
51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART Extended HAL module driver
52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #ifdef HAL_UART_MODULE_ENABLED
56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private typedef -----------------------------------------------------------*/
58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private define ------------------------------------------------------------*/
59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEX_Private_Constants UARTEx Private Constants
60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* UART RX FIFO depth */
63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #define RX_FIFO_DEPTH 8U
64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* UART TX FIFO depth */
66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #define TX_FIFO_DEPTH 8U
67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @}
69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private macros ------------------------------------------------------------*/
72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private variables ---------------------------------------------------------*/
73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private function prototypes -----------------------------------------------*/
74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Private_Functions UARTEx Private Functions
75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti
78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @}
81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Exported functions --------------------------------------------------------*/
84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
ARM GAS /tmp/ccEfj1JP.s page 3
88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended Initialization and Configuration Functions
91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim
93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ===============================================================================
94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### Initialization and Configuration functions #####
95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ===============================================================================
96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..]
97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** in asynchronous mode.
99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) For the asynchronous mode the parameters below can be configured:
100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Baud Rate
101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Word Length
102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Stop Bit
103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Parity: If the parity is enabled, then the MSB bit of the data written
104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** in the data register is transmitted but is changed by the parity bit.
105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Hardware flow control
106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Receiver/transmitter modes
107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Over Sampling Method
108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) One-Bit Sampling Method
109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) For the asynchronous mode, the following advanced features can be configured as well:
110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) TX and/or RX pin level inversion
111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) data logical level inversion
112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX and TX pins swap
113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX overrun detection disabling
114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) DMA disabling on RX error
115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) MSB first on communication line
116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) auto Baud rate detection
117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..]
118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** procedures (details for the procedures are available in reference manual).
120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim
122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Depending on the frame length defined by the M1 and M0 bits (7-bit,
124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 8-bit or 9-bit), the possible UART formats are listed in the
125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** following table.
126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Table 1. UART frame format.
128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+
129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | M1 bit | M0 bit | PCE bit | UART frame |
130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------|
131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 0 | 0 | | SB | 8 bit data | STB | |
132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------|
133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------|
135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 1 | 0 | | SB | 9 bit data | STB | |
136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------|
137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------|
139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 1 | 0 | 0 | | SB | 7 bit data | STB | |
140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------|
141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+
143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
ARM GAS /tmp/ccEfj1JP.s page 4
145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Initialize the RS485 Driver enable feature according to the specified
149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * parameters in the UART_InitTypeDef and creates the associated handle.
150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Polarity Select the driver enable polarity.
152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values:
153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param AssertionTime Driver Enable assertion time:
156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 5-bit value defining the time between the activation of the DE (Driver Enable)
157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * signal and the beginning of the start bit. It is expressed in sample time
158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * units (1/8 or 1/16 bit time, depending on the oversampling rate)
159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param DeassertionTime Driver Enable deassertion time:
160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 5-bit value defining the time between the end of the last stop bit, in a
161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * transmitted message, and the de-activation of the DE (Driver Enable) signal.
162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * oversampling rate).
164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t Assertion
167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t DeassertionTime)
168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t temp;
170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */
172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart == NULL)
173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR;
175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable UART instance */
177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable polarity */
180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_DE_POLARITY(Polarity));
181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable assertion time */
183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable deassertion time */
186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->gState == HAL_UART_STATE_RESET)
189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Allocate lock resource and initialize it */
191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->Lock = HAL_UNLOCKED;
192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UART_InitCallbacksToDefault(huart);
195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->MspInitCallback == NULL)
197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->MspInitCallback = HAL_UART_MspInit;
199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init the low level hardware */
ARM GAS /tmp/ccEfj1JP.s page 5
202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->MspInitCallback(huart);
203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #else
204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX */
205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_UART_MspInit(huart);
206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY;
210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable the Peripheral */
212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart);
213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the UART Communication parameters */
215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (UART_SetConfig(huart) == HAL_ERROR)
216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR;
218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UART_AdvFeatureConfig(huart);
223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the Driver Enable polarity */
229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the Driver Enable assertion and deassertion times */
232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Peripheral */
237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart);
238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart));
241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @}
245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended functions
249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim
251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ===============================================================================
252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### IO operation functions #####
253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ===============================================================================
254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** This subsection provides a set of Wakeup and FIFO mode related callback functions.
255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Wakeup from Stop mode Callback:
257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_WakeupCallback()
258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 6
259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) TX/RX Fifos Callbacks:
260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_RxFifoFullCallback()
261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_TxFifoEmptyCallback()
262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim
264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART wakeup from Stop mode callback.
269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None
271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */
275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UNUSED(huart);
276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** the HAL_UARTEx_WakeupCallback can be implemented in the user file.
279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART RX Fifo full callback.
284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None
286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */
290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UNUSED(huart);
291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART TX Fifo empty callback.
299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None
301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */
305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UNUSED(huart);
306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed,
308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @}
314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 7
316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended Peripheral Control functions
318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *
319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim
320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ===============================================================================
321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### Peripheral Control functions #####
322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ===============================================================================
323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..] This section provides the following functions:
324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** detection length to more than 4 bits for multiprocessor address mark wake up.
326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** trigger: address match, Start Bit detection or RXNE bit status.
328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..] This subsection also provides a set of additional functions providing enhanced reception
336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** services to user. (For example, these functions allow application to handle use cases
337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** where number of data to be received is unknown).
338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Compared to standard reception services which only consider number of received
340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** data elements as reception completion criteria, these functions also consider additional ev
341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** as triggers for updating reception status to caller :
342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Detection of inactivity period (RX line has not been active for a given period).
343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally
344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** for 1 frame time, after last received byte.
345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX inactivity detected by RTO, i.e. line has been in idle state
346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** for a programmable time, after last received byte.
347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Detection that a specific character has been received.
348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) There are two mode of transfer:
350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Blocking mode: The reception is performed in polling mode, until either expected number
351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** or till IDLE event occurs. Reception is handled only during function execution.
352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** When function exits, no data reception could occur. HAL status and number of actually re
353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** are returned by function after finishing transfer.
354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** These API's return the HAL status.
356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The end of the data processing will be indicated through the
357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The HAL_UART_ErrorCallback()user callback will be executed when a reception error is det
360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Blocking mode API:
362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle()
363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Non-Blocking mode API with Interrupt:
365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle_IT()
366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Non-Blocking mode API with DMA:
368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle_DMA()
369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim
371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
ARM GAS /tmp/ccEfj1JP.s page 8
373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief By default in multiprocessor mode, when the wake up method is set
376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * to address mark, the UART handles only 4-bit long addresses detection;
377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * this API allows to enable longer addresses detection (6-, 7- or 8-bit
378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * long).
379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param AddressLength This parameter can be one of the following values:
383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t Addres
388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */
390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart == NULL)
391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR;
393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the address length parameter */
396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY;
399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable the Peripheral */
401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart);
402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the address length */
404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Peripheral */
407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart);
408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState to Ready */
410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart));
411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Set Wakeup from Stop mode interrupt flag selection.
415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note It is the application responsibility to enable the interrupt used as
416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * usart_wkup interrupt source before entering low-power mode.
417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values:
420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_ADDRESS
421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_STARTBIT
422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeD
426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK;
428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart;
429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 9
430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* check the wake-up from stop mode UART instance */
431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* check the wake-up selection parameter */
433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY;
439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable the Peripheral */
441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart);
442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the wake-up selection scheme */
444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Peripheral */
452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart);
453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init tickstart for timeout management */
455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tickstart = HAL_GetTick();
456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Wait until REACK flag is set */
458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE)
459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = HAL_TIMEOUT;
461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Initialize the UART State */
465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY;
466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */
469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return status;
472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Enable UART Stop Mode.
476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set UESM bit */
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
ARM GAS /tmp/ccEfj1JP.s page 10
487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */
489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Disable UART Stop Mode.
496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Clear UESM bit */
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */
508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Enable the FIFO mode.
515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check parameters */
523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY;
529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */
531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1);
532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */
534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart);
535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable FIFO mode */
537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** SET_BIT(tmpcr1, USART_CR1_FIFOEN);
538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_ENABLE;
539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */
541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1);
542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */
ARM GAS /tmp/ccEfj1JP.s page 11
544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart);
545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY;
547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */
549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Disable the FIFO mode.
556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check parameters */
564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY;
570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */
572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1);
573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */
575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart);
576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable FIFO mode */
578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_DISABLE;
580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */
582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1);
583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY;
585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */
587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Set the TXFIFO threshold.
594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Threshold TX FIFO threshold value
596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values:
597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_8
598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_4
599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_2
600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_3_4
ARM GAS /tmp/ccEfj1JP.s page 12
601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_7_8
602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_8_8
603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check parameters */
610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY;
617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */
619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1);
620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */
622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart);
623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Update TX threshold configuration */
625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */
628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart);
629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */
631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1);
632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY;
634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */
636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Set the RXFIFO threshold.
643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Threshold RX FIFO threshold value
645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values:
646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_8
647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_4
648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_2
649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_3_4
650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_7_8
651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_8_8
652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 13
658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the parameters */
659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY;
666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */
668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1);
669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */
671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart);
672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Update RX threshold configuration */
674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */
677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart);
678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */
680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1);
681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY;
683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */
685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Receive an amount of data in blocking mode till either the expected number of data
692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * is received or an IDLE event occurs.
693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note HAL_OK is returned if reception is completed (expected number of data has been received)
694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * or if reception is stopped after IDLE event (less than the expected number of data has b
695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * In this case, RxLen output parameter indicates number of data available in reception buf
696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M
697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the
698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of uint16_t available through pData.
699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * is not empty. Read operations from the RDR register are performed when
701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * RXFNE flag is set. From hardware perspective, RXFNE flag and
702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * RXNE are mapped on the same bit-field.
703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param RxLen Number of data elements finally received
707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * (could be lower than Size, in case reception ends on IDLE event)
708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size
712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t Timeout)
713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t *pdata8bits;
ARM GAS /tmp/ccEfj1JP.s page 14
715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t *pdata16bits;
716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t uhMask;
717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart;
718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */
720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY)
721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U))
723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR;
725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ErrorCode = HAL_UART_ERROR_NONE;
730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX;
731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init tickstart for timeout management */
734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tickstart = HAL_GetTick();
735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferSize = Size;
737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount = Size;
738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Computation of UART mask to apply to RDR register */
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UART_MASK_COMPUTATION(huart);
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits = NULL;
747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData;
748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits = pData;
752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = NULL;
753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart);
756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Initialize output number of received elements */
758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *RxLen = 0U;
759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* as long as data have to be received */
761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** while (huart->RxXferCount > 0U)
762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check if IDLE flag is set */
764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Clear IDLE flag in ISR */
767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* If Set, but no data ever received, clear flag without exiting loop */
770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* If Set, and data has already been received, this means Idle Event is valid : End recepti
771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (*RxLen > 0U)
ARM GAS /tmp/ccEfj1JP.s page 15
772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY;
774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check if RXNE flag is set */
780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (pdata8bits == NULL)
783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++;
786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++;
791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Increment number of received elements */
793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *RxLen += 1U;
794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount--;
795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check for the Timeout */
798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (Timeout != HAL_MAX_DELAY)
799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY;
803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_TIMEOUT;
805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set number of received elements in output parameter : RxLen */
810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *RxLen = huart->RxXferSize - huart->RxXferCount;
811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */
812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY;
813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK;
815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_BUSY;
819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Receive an amount of data in interrupt mode till either the expected number of data
824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * is received or an IDLE event occurs.
825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note Reception is initiated by this function call. Further progress of reception is achieved
826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of receptio
827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * number of received data elements.
828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M
ARM GAS /tmp/ccEfj1JP.s page 16
829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the
830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of uint16_t available through pData.
831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t S
837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status;
839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */
841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY)
842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U))
844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR;
846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set Reception type to reception till IDLE Event*/
851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = UART_Start_Receive_IT(huart, pData, Size);
854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check Rx process has been successfully started */
856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (status == HAL_OK)
857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* In case of errors already pending when reception is started,
866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Interrupts may have already been raised and lead to reception abortion.
867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (Overrun error for instance).
868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = HAL_ERROR;
870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return status;
874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_BUSY;
878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Receive an amount of data in DMA mode till either the expected number
883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of data is received or an IDLE event occurs.
884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note Reception is initiated by this function call. Further progress of reception is achieved
885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * to DMA services, transferring automatically received data elements in user reception buf
ARM GAS /tmp/ccEfj1JP.s page 17
886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * calling registered callbacks at half/end of reception. UART IDLE events are also used to
887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * reception phase as ended. In all cases, callback execution will indicate number of recei
888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When the UART parity is enabled (PCE = 1), the received data contain
889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the parity bit (MSB position).
890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M
891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the
892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of uint16_t available through pData.
893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status
897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t
899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status;
901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY)
904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U))
906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR;
908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart);
911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set Reception type to reception till IDLE Event*/
913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = UART_Start_Receive_DMA(huart, pData, Size);
916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check Rx process has been successfully started */
918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (status == HAL_OK)
919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* In case of errors already pending when reception is started,
928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Interrupts may have already been raised and lead to reception abortion.
929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (Overrun error for instance).
930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = HAL_ERROR;
932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return status;
936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_BUSY;
940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 18
943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @}
945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @}
949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @addtogroup UARTEx_Private_Functions
952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{
953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detectio
957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param WakeUpSelection UART wake up from stop mode parameters.
959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None
960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti
962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
29 .loc 1 962 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 8
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
34 .loc 1 962 1 is_stmt 0 view .LVU1
35 0000 82B0 sub sp, sp, #8
36 .LCFI0:
37 .cfi_def_cfa_offset 8
38 0002 02AB add r3, sp, #8
39 0004 03E90600 stmdb r3, {r1, r2}
963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
40 .loc 1 963 3 is_stmt 1 view .LVU2
964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the USART address length */
966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
41 .loc 1 966 3 view .LVU3
42 0008 0268 ldr r2, [r0]
43 000a 5368 ldr r3, [r2, #4]
44 000c 23F01003 bic r3, r3, #16
45 0010 BDF80410 ldrh r1, [sp, #4]
46 0014 0B43 orrs r3, r3, r1
47 0016 5360 str r3, [r2, #4]
967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the USART address node */
969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_AD
48 .loc 1 969 3 view .LVU4
49 0018 0268 ldr r2, [r0]
50 001a 5368 ldr r3, [r2, #4]
51 001c 23F07F43 bic r3, r3, #-16777216
52 0020 9DF80610 ldrb r1, [sp, #6] @ zero_extendqisi2
53 0024 43EA0163 orr r3, r3, r1, lsl #24
54 0028 5360 str r3, [r2, #4]
970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
55 .loc 1 970 1 is_stmt 0 view .LVU5
56 002a 02B0 add sp, sp, #8
57 .LCFI1:
ARM GAS /tmp/ccEfj1JP.s page 19
58 .cfi_def_cfa_offset 0
59 @ sp needed
60 002c 7047 bx lr
61 .cfi_endproc
62 .LFE344:
64 .section .text.UARTEx_SetNbDataToProcess,"ax",%progbits
65 .align 1
66 .syntax unified
67 .thumb
68 .thumb_func
70 UARTEx_SetNbDataToProcess:
71 .LVL1:
72 .LFB345:
971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /**
973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Calculate the number of data to process in RX/TX ISR.
974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note The RX FIFO depth and the TX FIFO depth is extracted from
975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the UART configuration registers.
976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle.
977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None
978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */
979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
73 .loc 1 980 1 is_stmt 1 view -0
74 .cfi_startproc
75 @ args = 0, pretend = 0, frame = 0
76 @ frame_needed = 0, uses_anonymous_args = 0
77 @ link register save eliminated.
981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t rx_fifo_depth;
78 .loc 1 981 3 view .LVU7
982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t tx_fifo_depth;
79 .loc 1 982 3 view .LVU8
983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t rx_fifo_threshold;
80 .loc 1 983 3 view .LVU9
984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t tx_fifo_threshold;
81 .loc 1 984 3 view .LVU10
985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
82 .loc 1 985 3 view .LVU11
986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
83 .loc 1 986 3 view .LVU12
987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->FifoMode == UART_FIFOMODE_DISABLE)
84 .loc 1 988 3 view .LVU13
85 .loc 1 988 12 is_stmt 0 view .LVU14
86 0000 436E ldr r3, [r0, #100]
87 .loc 1 988 6 view .LVU15
88 0002 2BB9 cbnz r3, .L4
989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = 1U;
89 .loc 1 990 5 is_stmt 1 view .LVU16
90 .loc 1 990 30 is_stmt 0 view .LVU17
91 0004 0123 movs r3, #1
92 0006 A0F86A30 strh r3, [r0, #106] @ movhi
991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = 1U;
93 .loc 1 991 5 is_stmt 1 view .LVU18
94 .loc 1 991 30 is_stmt 0 view .LVU19
95 000a A0F86830 strh r3, [r0, #104] @ movhi
ARM GAS /tmp/ccEfj1JP.s page 20
96 000e 7047 bx lr
97 .L4:
980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t rx_fifo_depth;
98 .loc 1 980 1 view .LVU20
99 0010 30B4 push {r4, r5}
100 .LCFI2:
101 .cfi_def_cfa_offset 8
102 .cfi_offset 4, -8
103 .cfi_offset 5, -4
992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else
994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** rx_fifo_depth = RX_FIFO_DEPTH;
104 .loc 1 995 5 is_stmt 1 view .LVU21
105 .LVL2:
996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tx_fifo_depth = TX_FIFO_DEPTH;
106 .loc 1 996 5 view .LVU22
997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RX
107 .loc 1 997 5 view .LVU23
108 .loc 1 997 35 is_stmt 0 view .LVU24
109 0012 0368 ldr r3, [r0]
110 0014 9A68 ldr r2, [r3, #8]
111 .loc 1 997 23 view .LVU25
112 0016 C2F34262 ubfx r2, r2, #25, #3
113 .LVL3:
998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TX
114 .loc 1 998 5 is_stmt 1 view .LVU26
115 .loc 1 998 35 is_stmt 0 view .LVU27
116 001a 9968 ldr r1, [r3, #8]
117 .loc 1 998 23 view .LVU28
118 001c 490F lsrs r1, r1, #29
119 .LVL4:
999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
120 .loc 1 999 5 is_stmt 1 view .LVU29
121 .loc 1 999 68 is_stmt 0 view .LVU30
122 001e 094D ldr r5, .L9
123 0020 6B5C ldrb r3, [r5, r1] @ zero_extendqisi2
124 .loc 1 999 57 view .LVU31
125 0022 DB00 lsls r3, r3, #3
1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (uint16_t)denominator[tx_fifo_threshold];
126 .loc 1 1000 53 view .LVU32
127 0024 084C ldr r4, .L9+4
128 0026 615C ldrb r1, [r4, r1] @ zero_extendqisi2
129 .LVL5:
999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
130 .loc 1 999 89 view .LVU33
131 0028 93FBF1F3 sdiv r3, r3, r1
999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
132 .loc 1 999 30 view .LVU34
133 002c A0F86A30 strh r3, [r0, #106] @ movhi
1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
134 .loc 1 1001 5 is_stmt 1 view .LVU35
135 .loc 1 1001 68 is_stmt 0 view .LVU36
136 0030 AB5C ldrb r3, [r5, r2] @ zero_extendqisi2
137 .loc 1 1001 57 view .LVU37
138 0032 DB00 lsls r3, r3, #3
1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (uint16_t)denominator[rx_fifo_threshold];
ARM GAS /tmp/ccEfj1JP.s page 21
139 .loc 1 1002 53 view .LVU38
140 0034 A25C ldrb r2, [r4, r2] @ zero_extendqisi2
141 .LVL6:
1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
142 .loc 1 1001 89 view .LVU39
143 0036 93FBF2F3 sdiv r3, r3, r2
1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
144 .loc 1 1001 30 view .LVU40
145 003a A0F86830 strh r3, [r0, #104] @ movhi
1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
146 .loc 1 1004 1 view .LVU41
147 003e 30BC pop {r4, r5}
148 .LCFI3:
149 .cfi_restore 5
150 .cfi_restore 4
151 .cfi_def_cfa_offset 0
152 0040 7047 bx lr
153 .L10:
154 0042 00BF .align 2
155 .L9:
156 0044 00000000 .word numerator.1
157 0048 00000000 .word denominator.0
158 .cfi_endproc
159 .LFE345:
161 .section .text.HAL_RS485Ex_Init,"ax",%progbits
162 .align 1
163 .global HAL_RS485Ex_Init
164 .syntax unified
165 .thumb
166 .thumb_func
168 HAL_RS485Ex_Init:
169 .LVL7:
170 .LFB329:
168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t temp;
171 .loc 1 168 1 is_stmt 1 view -0
172 .cfi_startproc
173 @ args = 0, pretend = 0, frame = 0
174 @ frame_needed = 0, uses_anonymous_args = 0
169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
175 .loc 1 169 3 view .LVU43
172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
176 .loc 1 172 3 view .LVU44
172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
177 .loc 1 172 6 is_stmt 0 view .LVU45
178 0000 0028 cmp r0, #0
179 0002 3ED0 beq .L15
168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t temp;
180 .loc 1 168 1 view .LVU46
181 0004 F8B5 push {r3, r4, r5, r6, r7, lr}
182 .LCFI4:
183 .cfi_def_cfa_offset 24
184 .cfi_offset 3, -24
185 .cfi_offset 4, -20
186 .cfi_offset 5, -16
187 .cfi_offset 6, -12
188 .cfi_offset 7, -8
ARM GAS /tmp/ccEfj1JP.s page 22
189 .cfi_offset 14, -4
190 0006 0F46 mov r7, r1
191 0008 1646 mov r6, r2
192 000a 1D46 mov r5, r3
193 000c 0446 mov r4, r0
177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
194 .loc 1 177 3 is_stmt 1 view .LVU47
180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
195 .loc 1 180 3 view .LVU48
183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
196 .loc 1 183 3 view .LVU49
186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
197 .loc 1 186 3 view .LVU50
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
198 .loc 1 188 3 view .LVU51
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
199 .loc 1 188 12 is_stmt 0 view .LVU52
200 000e D0F88430 ldr r3, [r0, #132]
201 .LVL8:
188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
202 .loc 1 188 6 view .LVU53
203 0012 6BB3 cbz r3, .L20
204 .LVL9:
205 .L13:
209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
206 .loc 1 209 3 is_stmt 1 view .LVU54
209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
207 .loc 1 209 17 is_stmt 0 view .LVU55
208 0014 2423 movs r3, #36
209 0016 C4F88430 str r3, [r4, #132]
212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
210 .loc 1 212 3 is_stmt 1 view .LVU56
211 001a 2268 ldr r2, [r4]
212 001c 1368 ldr r3, [r2]
213 001e 23F00103 bic r3, r3, #1
214 0022 1360 str r3, [r2]
215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
215 .loc 1 215 3 view .LVU57
215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
216 .loc 1 215 7 is_stmt 0 view .LVU58
217 0024 2046 mov r0, r4
218 0026 FFF7FEFF bl UART_SetConfig
219 .LVL10:
215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
220 .loc 1 215 6 view .LVU59
221 002a 0128 cmp r0, #1
222 002c 1FD0 beq .L12
220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
223 .loc 1 220 3 is_stmt 1 view .LVU60
220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
224 .loc 1 220 26 is_stmt 0 view .LVU61
225 002e A36A ldr r3, [r4, #40]
220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
226 .loc 1 220 6 view .LVU62
227 0030 1BBB cbnz r3, .L21
228 .L14:
226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 23
229 .loc 1 226 3 is_stmt 1 view .LVU63
230 0032 2268 ldr r2, [r4]
231 0034 9368 ldr r3, [r2, #8]
232 0036 43F48043 orr r3, r3, #16384
233 003a 9360 str r3, [r2, #8]
229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
234 .loc 1 229 3 view .LVU64
235 003c 2268 ldr r2, [r4]
236 003e 9368 ldr r3, [r2, #8]
237 0040 23F40043 bic r3, r3, #32768
238 0044 3B43 orrs r3, r3, r7
239 0046 9360 str r3, [r2, #8]
232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
240 .loc 1 232 3 view .LVU65
241 .LVL11:
233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
242 .loc 1 233 3 view .LVU66
233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
243 .loc 1 233 28 is_stmt 0 view .LVU67
244 0048 2D04 lsls r5, r5, #16
245 .LVL12:
233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
246 .loc 1 233 8 view .LVU68
247 004a 45EA4652 orr r2, r5, r6, lsl #21
248 .LVL13:
234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
249 .loc 1 234 3 is_stmt 1 view .LVU69
250 004e 2168 ldr r1, [r4]
251 0050 0B68 ldr r3, [r1]
252 0052 23F07F73 bic r3, r3, #66846720
253 0056 23F44033 bic r3, r3, #196608
254 005a 1343 orrs r3, r3, r2
255 005c 0B60 str r3, [r1]
237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
256 .loc 1 237 3 view .LVU70
257 005e 2268 ldr r2, [r4]
258 .LVL14:
237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
259 .loc 1 237 3 is_stmt 0 view .LVU71
260 0060 1368 ldr r3, [r2]
261 0062 43F00103 orr r3, r3, #1
262 0066 1360 str r3, [r2]
240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
263 .loc 1 240 3 is_stmt 1 view .LVU72
240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
264 .loc 1 240 11 is_stmt 0 view .LVU73
265 0068 2046 mov r0, r4
266 006a FFF7FEFF bl UART_CheckIdleState
267 .LVL15:
268 .L12:
241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
269 .loc 1 241 1 view .LVU74
270 006e F8BD pop {r3, r4, r5, r6, r7, pc}
271 .LVL16:
272 .L20:
191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
273 .loc 1 191 5 is_stmt 1 view .LVU75
ARM GAS /tmp/ccEfj1JP.s page 24
191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
274 .loc 1 191 17 is_stmt 0 view .LVU76
275 0070 80F88030 strb r3, [r0, #128]
205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
276 .loc 1 205 5 is_stmt 1 view .LVU77
277 0074 FFF7FEFF bl HAL_UART_MspInit
278 .LVL17:
205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
279 .loc 1 205 5 is_stmt 0 view .LVU78
280 0078 CCE7 b .L13
281 .L21:
222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
282 .loc 1 222 5 is_stmt 1 view .LVU79
283 007a 2046 mov r0, r4
284 007c FFF7FEFF bl UART_AdvFeatureConfig
285 .LVL18:
286 0080 D7E7 b .L14
287 .LVL19:
288 .L15:
289 .LCFI5:
290 .cfi_def_cfa_offset 0
291 .cfi_restore 3
292 .cfi_restore 4
293 .cfi_restore 5
294 .cfi_restore 6
295 .cfi_restore 7
296 .cfi_restore 14
174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
297 .loc 1 174 12 is_stmt 0 view .LVU80
298 0082 0120 movs r0, #1
299 .LVL20:
241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
300 .loc 1 241 1 view .LVU81
301 0084 7047 bx lr
302 .cfi_endproc
303 .LFE329:
305 .section .text.HAL_UARTEx_WakeupCallback,"ax",%progbits
306 .align 1
307 .weak HAL_UARTEx_WakeupCallback
308 .syntax unified
309 .thumb
310 .thumb_func
312 HAL_UARTEx_WakeupCallback:
313 .LVL21:
314 .LFB330:
273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */
315 .loc 1 273 1 is_stmt 1 view -0
316 .cfi_startproc
317 @ args = 0, pretend = 0, frame = 0
318 @ frame_needed = 0, uses_anonymous_args = 0
319 @ link register save eliminated.
275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
320 .loc 1 275 3 view .LVU83
280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
321 .loc 1 280 1 is_stmt 0 view .LVU84
322 0000 7047 bx lr
323 .cfi_endproc
ARM GAS /tmp/ccEfj1JP.s page 25
324 .LFE330:
326 .section .text.HAL_UARTEx_RxFifoFullCallback,"ax",%progbits
327 .align 1
328 .weak HAL_UARTEx_RxFifoFullCallback
329 .syntax unified
330 .thumb
331 .thumb_func
333 HAL_UARTEx_RxFifoFullCallback:
334 .LVL22:
335 .LFB331:
288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */
336 .loc 1 288 1 is_stmt 1 view -0
337 .cfi_startproc
338 @ args = 0, pretend = 0, frame = 0
339 @ frame_needed = 0, uses_anonymous_args = 0
340 @ link register save eliminated.
290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
341 .loc 1 290 3 view .LVU86
295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
342 .loc 1 295 1 is_stmt 0 view .LVU87
343 0000 7047 bx lr
344 .cfi_endproc
345 .LFE331:
347 .section .text.HAL_UARTEx_TxFifoEmptyCallback,"ax",%progbits
348 .align 1
349 .weak HAL_UARTEx_TxFifoEmptyCallback
350 .syntax unified
351 .thumb
352 .thumb_func
354 HAL_UARTEx_TxFifoEmptyCallback:
355 .LVL23:
356 .LFB332:
303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */
357 .loc 1 303 1 is_stmt 1 view -0
358 .cfi_startproc
359 @ args = 0, pretend = 0, frame = 0
360 @ frame_needed = 0, uses_anonymous_args = 0
361 @ link register save eliminated.
305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
362 .loc 1 305 3 view .LVU89
310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
363 .loc 1 310 1 is_stmt 0 view .LVU90
364 0000 7047 bx lr
365 .cfi_endproc
366 .LFE332:
368 .section .text.HAL_MultiProcessorEx_AddressLength_Set,"ax",%progbits
369 .align 1
370 .global HAL_MultiProcessorEx_AddressLength_Set
371 .syntax unified
372 .thumb
373 .thumb_func
375 HAL_MultiProcessorEx_AddressLength_Set:
376 .LVL24:
377 .LFB333:
388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */
378 .loc 1 388 1 is_stmt 1 view -0
379 .cfi_startproc
ARM GAS /tmp/ccEfj1JP.s page 26
380 @ args = 0, pretend = 0, frame = 0
381 @ frame_needed = 0, uses_anonymous_args = 0
390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
382 .loc 1 390 3 view .LVU92
390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
383 .loc 1 390 6 is_stmt 0 view .LVU93
384 0000 C0B1 cbz r0, .L27
388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */
385 .loc 1 388 1 view .LVU94
386 0002 08B5 push {r3, lr}
387 .LCFI6:
388 .cfi_def_cfa_offset 8
389 .cfi_offset 3, -8
390 .cfi_offset 14, -4
391 0004 0346 mov r3, r0
396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
392 .loc 1 396 3 is_stmt 1 view .LVU95
398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
393 .loc 1 398 3 view .LVU96
398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
394 .loc 1 398 17 is_stmt 0 view .LVU97
395 0006 2422 movs r2, #36
396 0008 C0F88420 str r2, [r0, #132]
401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
397 .loc 1 401 3 is_stmt 1 view .LVU98
398 000c 0068 ldr r0, [r0]
399 .LVL25:
401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
400 .loc 1 401 3 is_stmt 0 view .LVU99
401 000e 0268 ldr r2, [r0]
402 0010 22F00102 bic r2, r2, #1
403 0014 0260 str r2, [r0]
404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
404 .loc 1 404 3 is_stmt 1 view .LVU100
405 0016 1868 ldr r0, [r3]
406 0018 4268 ldr r2, [r0, #4]
407 001a 22F01002 bic r2, r2, #16
408 001e 1143 orrs r1, r1, r2
409 .LVL26:
404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
410 .loc 1 404 3 is_stmt 0 view .LVU101
411 0020 4160 str r1, [r0, #4]
407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
412 .loc 1 407 3 is_stmt 1 view .LVU102
413 0022 1968 ldr r1, [r3]
414 0024 0A68 ldr r2, [r1]
415 0026 42F00102 orr r2, r2, #1
416 002a 0A60 str r2, [r1]
410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
417 .loc 1 410 3 view .LVU103
410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
418 .loc 1 410 11 is_stmt 0 view .LVU104
419 002c 1846 mov r0, r3
420 002e FFF7FEFF bl UART_CheckIdleState
421 .LVL27:
411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
422 .loc 1 411 1 view .LVU105
ARM GAS /tmp/ccEfj1JP.s page 27
423 0032 08BD pop {r3, pc}
424 .LVL28:
425 .L27:
426 .LCFI7:
427 .cfi_def_cfa_offset 0
428 .cfi_restore 3
429 .cfi_restore 14
392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
430 .loc 1 392 12 view .LVU106
431 0034 0120 movs r0, #1
432 .LVL29:
411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
433 .loc 1 411 1 view .LVU107
434 0036 7047 bx lr
435 .cfi_endproc
436 .LFE333:
438 .section .text.HAL_UARTEx_StopModeWakeUpSourceConfig,"ax",%progbits
439 .align 1
440 .global HAL_UARTEx_StopModeWakeUpSourceConfig
441 .syntax unified
442 .thumb
443 .thumb_func
445 HAL_UARTEx_StopModeWakeUpSourceConfig:
446 .LVL30:
447 .LFB334:
426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK;
448 .loc 1 426 1 is_stmt 1 view -0
449 .cfi_startproc
450 @ args = 0, pretend = 0, frame = 8
451 @ frame_needed = 0, uses_anonymous_args = 0
426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK;
452 .loc 1 426 1 is_stmt 0 view .LVU109
453 0000 10B5 push {r4, lr}
454 .LCFI8:
455 .cfi_def_cfa_offset 8
456 .cfi_offset 4, -8
457 .cfi_offset 14, -4
458 0002 84B0 sub sp, sp, #16
459 .LCFI9:
460 .cfi_def_cfa_offset 24
461 0004 04AB add r3, sp, #16
462 0006 03E90600 stmdb r3, {r1, r2}
427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart;
463 .loc 1 427 3 is_stmt 1 view .LVU110
464 .LVL31:
428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
465 .loc 1 428 3 view .LVU111
431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* check the wake-up selection parameter */
466 .loc 1 431 3 view .LVU112
433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
467 .loc 1 433 3 view .LVU113
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
468 .loc 1 436 3 view .LVU114
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
469 .loc 1 436 3 view .LVU115
470 000a 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
471 000e 012B cmp r3, #1
ARM GAS /tmp/ccEfj1JP.s page 28
472 0010 35D0 beq .L36
473 0012 0446 mov r4, r0
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
474 .loc 1 436 3 discriminator 2 view .LVU116
475 0014 0123 movs r3, #1
476 0016 80F88030 strb r3, [r0, #128]
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
477 .loc 1 436 3 discriminator 2 view .LVU117
438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
478 .loc 1 438 3 discriminator 2 view .LVU118
438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
479 .loc 1 438 17 is_stmt 0 discriminator 2 view .LVU119
480 001a 2423 movs r3, #36
481 001c C0F88430 str r3, [r0, #132]
441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
482 .loc 1 441 3 is_stmt 1 discriminator 2 view .LVU120
483 0020 0268 ldr r2, [r0]
484 0022 1368 ldr r3, [r2]
485 0024 23F00103 bic r3, r3, #1
486 0028 1360 str r3, [r2]
444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
487 .loc 1 444 3 discriminator 2 view .LVU121
488 002a 0168 ldr r1, [r0]
489 002c 8B68 ldr r3, [r1, #8]
490 002e 23F44013 bic r3, r3, #3145728
491 0032 029A ldr r2, [sp, #8]
492 0034 1343 orrs r3, r3, r2
493 0036 8B60 str r3, [r1, #8]
446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
494 .loc 1 446 3 discriminator 2 view .LVU122
446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
495 .loc 1 446 6 is_stmt 0 discriminator 2 view .LVU123
496 0038 AAB1 cbz r2, .L39
497 .LVL32:
498 .L34:
452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
499 .loc 1 452 3 is_stmt 1 view .LVU124
500 003a 2268 ldr r2, [r4]
501 003c 1368 ldr r3, [r2]
502 003e 43F00103 orr r3, r3, #1
503 0042 1360 str r3, [r2]
455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
504 .loc 1 455 3 view .LVU125
455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
505 .loc 1 455 15 is_stmt 0 view .LVU126
506 0044 FFF7FEFF bl HAL_GetTick
507 .LVL33:
508 0048 0346 mov r3, r0
509 .LVL34:
458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
510 .loc 1 458 3 is_stmt 1 view .LVU127
458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
511 .loc 1 458 7 is_stmt 0 view .LVU128
512 004a 6FF07E42 mvn r2, #-33554432
513 004e 0092 str r2, [sp]
514 0050 0022 movs r2, #0
515 0052 4FF48001 mov r1, #4194304
ARM GAS /tmp/ccEfj1JP.s page 29
516 0056 2046 mov r0, r4
517 .LVL35:
458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
518 .loc 1 458 7 view .LVU129
519 0058 FFF7FEFF bl UART_WaitOnFlagUntilTimeout
520 .LVL36:
458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
521 .loc 1 458 6 view .LVU130
522 005c 48B9 cbnz r0, .L37
465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
523 .loc 1 465 5 is_stmt 1 view .LVU131
465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
524 .loc 1 465 19 is_stmt 0 view .LVU132
525 005e 2023 movs r3, #32
526 0060 C4F88430 str r3, [r4, #132]
527 0064 06E0 b .L35
528 .LVL37:
529 .L39:
448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
530 .loc 1 448 5 is_stmt 1 view .LVU133
531 0066 04AB add r3, sp, #16
532 0068 13E90600 ldmdb r3, {r1, r2}
533 006c FFF7FEFF bl UARTEx_Wakeup_AddressConfig
534 .LVL38:
448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
535 .loc 1 448 5 is_stmt 0 view .LVU134
536 0070 E3E7 b .L34
537 .LVL39:
538 .L37:
460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
539 .loc 1 460 12 view .LVU135
540 0072 0320 movs r0, #3
541 .L35:
542 .LVL40:
469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
543 .loc 1 469 3 is_stmt 1 view .LVU136
469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
544 .loc 1 469 3 view .LVU137
545 0074 0023 movs r3, #0
546 0076 84F88030 strb r3, [r4, #128]
469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
547 .loc 1 469 3 view .LVU138
471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
548 .loc 1 471 3 view .LVU139
549 .LVL41:
550 .L33:
472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
551 .loc 1 472 1 is_stmt 0 view .LVU140
552 007a 04B0 add sp, sp, #16
553 .LCFI10:
554 .cfi_remember_state
555 .cfi_def_cfa_offset 8
556 @ sp needed
557 007c 10BD pop {r4, pc}
558 .LVL42:
559 .L36:
560 .LCFI11:
ARM GAS /tmp/ccEfj1JP.s page 30
561 .cfi_restore_state
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
562 .loc 1 436 3 view .LVU141
563 007e 0220 movs r0, #2
564 .LVL43:
436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
565 .loc 1 436 3 view .LVU142
566 0080 FBE7 b .L33
567 .cfi_endproc
568 .LFE334:
570 .section .text.HAL_UARTEx_EnableStopMode,"ax",%progbits
571 .align 1
572 .global HAL_UARTEx_EnableStopMode
573 .syntax unified
574 .thumb
575 .thumb_func
577 HAL_UARTEx_EnableStopMode:
578 .LVL44:
579 .LFB335:
481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
580 .loc 1 481 1 is_stmt 1 view -0
581 .cfi_startproc
582 @ args = 0, pretend = 0, frame = 0
583 @ frame_needed = 0, uses_anonymous_args = 0
584 @ link register save eliminated.
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
585 .loc 1 483 3 view .LVU144
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
586 .loc 1 483 3 view .LVU145
587 0000 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
588 0004 012B cmp r3, #1
589 0006 10D0 beq .L43
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
590 .loc 1 483 3 discriminator 2 view .LVU146
591 0008 0123 movs r3, #1
592 000a 80F88030 strb r3, [r0, #128]
593 .L42:
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
594 .loc 1 483 3 discriminator 1 view .LVU147
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
595 .loc 1 486 3 discriminator 1 view .LVU148
596 .LBB22:
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
597 .loc 1 486 3 discriminator 1 view .LVU149
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
598 .loc 1 486 3 discriminator 1 view .LVU150
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
599 .loc 1 486 3 discriminator 1 view .LVU151
600 000e 0268 ldr r2, [r0]
601 .LVL45:
602 .LBB23:
603 .LBI23:
604 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0
ARM GAS /tmp/ccEfj1JP.s page 31
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
ARM GAS /tmp/ccEfj1JP.s page 32
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER
117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/ccEfj1JP.s page 33
119:Drivers/CMSIS/Include/cmsis_gcc.h ****
120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */
121:Drivers/CMSIS/Include/cmsis_gcc.h ****
122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss
127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly
128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script.
129:Drivers/CMSIS/Include/cmsis_gcc.h ****
130:Drivers/CMSIS/Include/cmsis_gcc.h **** */
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN;
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src;
137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t;
140:Drivers/CMSIS/Include/cmsis_gcc.h ****
141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t;
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__;
147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__;
148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__;
149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__;
150:Drivers/CMSIS/Include/cmsis_gcc.h ****
151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i];
154:Drivers/CMSIS/Include/cmsis_gcc.h **** }
155:Drivers/CMSIS/Include/cmsis_gcc.h **** }
156:Drivers/CMSIS/Include/cmsis_gcc.h ****
157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u;
160:Drivers/CMSIS/Include/cmsis_gcc.h **** }
161:Drivers/CMSIS/Include/cmsis_gcc.h **** }
162:Drivers/CMSIS/Include/cmsis_gcc.h ****
163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start();
164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
165:Drivers/CMSIS/Include/cmsis_gcc.h ****
166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start
167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
168:Drivers/CMSIS/Include/cmsis_gcc.h ****
169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop
171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
172:Drivers/CMSIS/Include/cmsis_gcc.h ****
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit
175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/ccEfj1JP.s page 34
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors
179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
180:Drivers/CMSIS/Include/cmsis_gcc.h ****
181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
184:Drivers/CMSIS/Include/cmsis_gcc.h ****
185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
189:Drivers/CMSIS/Include/cmsis_gcc.h **** */
190:Drivers/CMSIS/Include/cmsis_gcc.h ****
191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
195:Drivers/CMSIS/Include/cmsis_gcc.h **** */
196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
200:Drivers/CMSIS/Include/cmsis_gcc.h ****
201:Drivers/CMSIS/Include/cmsis_gcc.h ****
202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
206:Drivers/CMSIS/Include/cmsis_gcc.h **** */
207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
211:Drivers/CMSIS/Include/cmsis_gcc.h ****
212:Drivers/CMSIS/Include/cmsis_gcc.h ****
213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
214:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
215:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
216:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
217:Drivers/CMSIS/Include/cmsis_gcc.h **** */
218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
220:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
221:Drivers/CMSIS/Include/cmsis_gcc.h ****
222:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
223:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
225:Drivers/CMSIS/Include/cmsis_gcc.h ****
226:Drivers/CMSIS/Include/cmsis_gcc.h ****
227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure)
230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode.
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccEfj1JP.s page 35
233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
236:Drivers/CMSIS/Include/cmsis_gcc.h ****
237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
241:Drivers/CMSIS/Include/cmsis_gcc.h ****
242:Drivers/CMSIS/Include/cmsis_gcc.h ****
243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
246:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
247:Drivers/CMSIS/Include/cmsis_gcc.h **** */
248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
250:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
252:Drivers/CMSIS/Include/cmsis_gcc.h ****
253:Drivers/CMSIS/Include/cmsis_gcc.h ****
254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
256:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure)
257:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state.
258:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
259:Drivers/CMSIS/Include/cmsis_gcc.h **** */
260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
265:Drivers/CMSIS/Include/cmsis_gcc.h ****
266:Drivers/CMSIS/Include/cmsis_gcc.h ****
267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
268:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
269:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
270:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
271:Drivers/CMSIS/Include/cmsis_gcc.h **** */
272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
274:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
275:Drivers/CMSIS/Include/cmsis_gcc.h ****
276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
277:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
279:Drivers/CMSIS/Include/cmsis_gcc.h ****
280:Drivers/CMSIS/Include/cmsis_gcc.h ****
281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
282:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
283:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
284:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
285:Drivers/CMSIS/Include/cmsis_gcc.h **** */
286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
288:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
289:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccEfj1JP.s page 36
290:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
291:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
293:Drivers/CMSIS/Include/cmsis_gcc.h ****
294:Drivers/CMSIS/Include/cmsis_gcc.h ****
295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
296:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
297:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
298:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
299:Drivers/CMSIS/Include/cmsis_gcc.h **** */
300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
302:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
303:Drivers/CMSIS/Include/cmsis_gcc.h ****
304:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
305:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
307:Drivers/CMSIS/Include/cmsis_gcc.h ****
308:Drivers/CMSIS/Include/cmsis_gcc.h ****
309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
313:Drivers/CMSIS/Include/cmsis_gcc.h **** */
314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
316:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
317:Drivers/CMSIS/Include/cmsis_gcc.h ****
318:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) );
319:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
321:Drivers/CMSIS/Include/cmsis_gcc.h ****
322:Drivers/CMSIS/Include/cmsis_gcc.h ****
323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
325:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure)
326:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
327:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
328:Drivers/CMSIS/Include/cmsis_gcc.h **** */
329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
331:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
332:Drivers/CMSIS/Include/cmsis_gcc.h ****
333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
334:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
337:Drivers/CMSIS/Include/cmsis_gcc.h ****
338:Drivers/CMSIS/Include/cmsis_gcc.h ****
339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
343:Drivers/CMSIS/Include/cmsis_gcc.h **** */
344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
346:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
ARM GAS /tmp/ccEfj1JP.s page 37
347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
349:Drivers/CMSIS/Include/cmsis_gcc.h ****
350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
354:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
355:Drivers/CMSIS/Include/cmsis_gcc.h **** */
356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
358:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
361:Drivers/CMSIS/Include/cmsis_gcc.h ****
362:Drivers/CMSIS/Include/cmsis_gcc.h ****
363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
364:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
365:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
366:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
367:Drivers/CMSIS/Include/cmsis_gcc.h **** */
368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
370:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
371:Drivers/CMSIS/Include/cmsis_gcc.h ****
372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) );
373:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
375:Drivers/CMSIS/Include/cmsis_gcc.h ****
376:Drivers/CMSIS/Include/cmsis_gcc.h ****
377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
379:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure)
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
381:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
382:Drivers/CMSIS/Include/cmsis_gcc.h **** */
383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
385:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
386:Drivers/CMSIS/Include/cmsis_gcc.h ****
387:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
388:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
391:Drivers/CMSIS/Include/cmsis_gcc.h ****
392:Drivers/CMSIS/Include/cmsis_gcc.h ****
393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
394:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
395:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
396:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
397:Drivers/CMSIS/Include/cmsis_gcc.h **** */
398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
400:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
402:Drivers/CMSIS/Include/cmsis_gcc.h ****
403:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccEfj1JP.s page 38
404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
406:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure)
407:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
408:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
409:Drivers/CMSIS/Include/cmsis_gcc.h **** */
410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
412:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
415:Drivers/CMSIS/Include/cmsis_gcc.h ****
416:Drivers/CMSIS/Include/cmsis_gcc.h ****
417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
419:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure)
420:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
421:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value
422:Drivers/CMSIS/Include/cmsis_gcc.h **** */
423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
425:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
426:Drivers/CMSIS/Include/cmsis_gcc.h ****
427:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
428:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
430:Drivers/CMSIS/Include/cmsis_gcc.h ****
431:Drivers/CMSIS/Include/cmsis_gcc.h ****
432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
433:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure)
434:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
435:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set
436:Drivers/CMSIS/Include/cmsis_gcc.h **** */
437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
439:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
442:Drivers/CMSIS/Include/cmsis_gcc.h ****
443:Drivers/CMSIS/Include/cmsis_gcc.h ****
444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
445:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
446:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
447:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
448:Drivers/CMSIS/Include/cmsis_gcc.h **** */
449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
451:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
452:Drivers/CMSIS/Include/cmsis_gcc.h ****
453:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
454:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
456:Drivers/CMSIS/Include/cmsis_gcc.h ****
457:Drivers/CMSIS/Include/cmsis_gcc.h ****
458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
460:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure)
ARM GAS /tmp/ccEfj1JP.s page 39
461:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
462:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
463:Drivers/CMSIS/Include/cmsis_gcc.h **** */
464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
466:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
467:Drivers/CMSIS/Include/cmsis_gcc.h ****
468:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
469:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
472:Drivers/CMSIS/Include/cmsis_gcc.h ****
473:Drivers/CMSIS/Include/cmsis_gcc.h ****
474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
475:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
476:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
477:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
478:Drivers/CMSIS/Include/cmsis_gcc.h **** */
479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
481:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
483:Drivers/CMSIS/Include/cmsis_gcc.h ****
484:Drivers/CMSIS/Include/cmsis_gcc.h ****
485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure)
488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
490:Drivers/CMSIS/Include/cmsis_gcc.h **** */
491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
496:Drivers/CMSIS/Include/cmsis_gcc.h ****
497:Drivers/CMSIS/Include/cmsis_gcc.h ****
498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
499:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
500:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
502:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
503:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
504:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
505:Drivers/CMSIS/Include/cmsis_gcc.h **** */
506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
508:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
510:Drivers/CMSIS/Include/cmsis_gcc.h ****
511:Drivers/CMSIS/Include/cmsis_gcc.h ****
512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
513:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
514:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
515:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
516:Drivers/CMSIS/Include/cmsis_gcc.h **** */
517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
ARM GAS /tmp/ccEfj1JP.s page 40
518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
519:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
521:Drivers/CMSIS/Include/cmsis_gcc.h ****
522:Drivers/CMSIS/Include/cmsis_gcc.h ****
523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
524:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
525:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
526:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
527:Drivers/CMSIS/Include/cmsis_gcc.h **** */
528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
530:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
531:Drivers/CMSIS/Include/cmsis_gcc.h ****
532:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
533:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
535:Drivers/CMSIS/Include/cmsis_gcc.h ****
536:Drivers/CMSIS/Include/cmsis_gcc.h ****
537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
539:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure)
540:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state.
541:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
542:Drivers/CMSIS/Include/cmsis_gcc.h **** */
543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
545:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
546:Drivers/CMSIS/Include/cmsis_gcc.h ****
547:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
548:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
551:Drivers/CMSIS/Include/cmsis_gcc.h ****
552:Drivers/CMSIS/Include/cmsis_gcc.h ****
553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
554:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
555:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
556:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
557:Drivers/CMSIS/Include/cmsis_gcc.h **** */
558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
560:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
562:Drivers/CMSIS/Include/cmsis_gcc.h ****
563:Drivers/CMSIS/Include/cmsis_gcc.h ****
564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
566:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure)
567:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state.
568:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
569:Drivers/CMSIS/Include/cmsis_gcc.h **** */
570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
572:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/ccEfj1JP.s page 41
575:Drivers/CMSIS/Include/cmsis_gcc.h ****
576:Drivers/CMSIS/Include/cmsis_gcc.h ****
577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
578:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
579:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
580:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
581:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
582:Drivers/CMSIS/Include/cmsis_gcc.h **** */
583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
585:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
587:Drivers/CMSIS/Include/cmsis_gcc.h ****
588:Drivers/CMSIS/Include/cmsis_gcc.h ****
589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
590:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
591:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
592:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
593:Drivers/CMSIS/Include/cmsis_gcc.h **** */
594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
596:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
597:Drivers/CMSIS/Include/cmsis_gcc.h ****
598:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
599:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
601:Drivers/CMSIS/Include/cmsis_gcc.h ****
602:Drivers/CMSIS/Include/cmsis_gcc.h ****
603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
605:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure)
606:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state.
607:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
608:Drivers/CMSIS/Include/cmsis_gcc.h **** */
609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
611:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
612:Drivers/CMSIS/Include/cmsis_gcc.h ****
613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
614:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
617:Drivers/CMSIS/Include/cmsis_gcc.h ****
618:Drivers/CMSIS/Include/cmsis_gcc.h ****
619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
620:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
621:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
622:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
623:Drivers/CMSIS/Include/cmsis_gcc.h **** */
624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
626:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
628:Drivers/CMSIS/Include/cmsis_gcc.h ****
629:Drivers/CMSIS/Include/cmsis_gcc.h ****
630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS /tmp/ccEfj1JP.s page 42
632:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure)
633:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state.
634:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
635:Drivers/CMSIS/Include/cmsis_gcc.h **** */
636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
638:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
641:Drivers/CMSIS/Include/cmsis_gcc.h ****
642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
643:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
644:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
645:Drivers/CMSIS/Include/cmsis_gcc.h ****
646:Drivers/CMSIS/Include/cmsis_gcc.h ****
647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
648:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
649:Drivers/CMSIS/Include/cmsis_gcc.h ****
650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit
652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
654:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
655:Drivers/CMSIS/Include/cmsis_gcc.h ****
656:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
657:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
658:Drivers/CMSIS/Include/cmsis_gcc.h **** */
659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
662:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
663:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
664:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
666:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
667:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) );
668:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
671:Drivers/CMSIS/Include/cmsis_gcc.h ****
672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure)
675:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
676:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
677:Drivers/CMSIS/Include/cmsis_gcc.h ****
678:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
679:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value
680:Drivers/CMSIS/Include/cmsis_gcc.h **** */
681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
684:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
685:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
687:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
688:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
ARM GAS /tmp/ccEfj1JP.s page 43
689:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
693:Drivers/CMSIS/Include/cmsis_gcc.h ****
694:Drivers/CMSIS/Include/cmsis_gcc.h ****
695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
696:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
697:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
698:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
699:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
700:Drivers/CMSIS/Include/cmsis_gcc.h ****
701:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
702:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
703:Drivers/CMSIS/Include/cmsis_gcc.h **** */
704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
707:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
708:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
709:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
711:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
714:Drivers/CMSIS/Include/cmsis_gcc.h ****
715:Drivers/CMSIS/Include/cmsis_gcc.h ****
716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
718:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure)
719:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
720:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
721:Drivers/CMSIS/Include/cmsis_gcc.h ****
722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
724:Drivers/CMSIS/Include/cmsis_gcc.h **** */
725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
728:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI
729:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit;
730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
731:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
735:Drivers/CMSIS/Include/cmsis_gcc.h ****
736:Drivers/CMSIS/Include/cmsis_gcc.h ****
737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
738:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit
739:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
740:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure
741:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
742:Drivers/CMSIS/Include/cmsis_gcc.h ****
743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
744:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccEfj1JP.s page 44
746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
749:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
750:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
751:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
753:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
754:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
755:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
758:Drivers/CMSIS/Include/cmsis_gcc.h ****
759:Drivers/CMSIS/Include/cmsis_gcc.h ****
760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure)
763:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
764:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always.
765:Drivers/CMSIS/Include/cmsis_gcc.h ****
766:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
767:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value
768:Drivers/CMSIS/Include/cmsis_gcc.h **** */
769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
772:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
773:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U;
774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
775:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
776:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
777:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
781:Drivers/CMSIS/Include/cmsis_gcc.h ****
782:Drivers/CMSIS/Include/cmsis_gcc.h ****
783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
784:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit
785:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
786:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
787:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
788:Drivers/CMSIS/Include/cmsis_gcc.h ****
789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
791:Drivers/CMSIS/Include/cmsis_gcc.h **** */
792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
795:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
796:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
797:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
799:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
802:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccEfj1JP.s page 45
803:Drivers/CMSIS/Include/cmsis_gcc.h ****
804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
806:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure)
807:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
808:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored.
809:Drivers/CMSIS/Include/cmsis_gcc.h ****
810:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
811:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
812:Drivers/CMSIS/Include/cmsis_gcc.h **** */
813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
816:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI
817:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit;
818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
819:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
823:Drivers/CMSIS/Include/cmsis_gcc.h ****
824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
825:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
826:Drivers/CMSIS/Include/cmsis_gcc.h ****
827:Drivers/CMSIS/Include/cmsis_gcc.h ****
828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
829:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
830:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
831:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
832:Drivers/CMSIS/Include/cmsis_gcc.h **** */
833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
836:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr)
838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
840:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
841:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr();
842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
843:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
844:Drivers/CMSIS/Include/cmsis_gcc.h ****
845:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
846:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
849:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U);
850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
852:Drivers/CMSIS/Include/cmsis_gcc.h ****
853:Drivers/CMSIS/Include/cmsis_gcc.h ****
854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
855:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
856:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
857:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
858:Drivers/CMSIS/Include/cmsis_gcc.h **** */
859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
ARM GAS /tmp/ccEfj1JP.s page 46
860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
862:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
866:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
867:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
869:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
872:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr;
873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
875:Drivers/CMSIS/Include/cmsis_gcc.h ****
876:Drivers/CMSIS/Include/cmsis_gcc.h ****
877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
878:Drivers/CMSIS/Include/cmsis_gcc.h ****
879:Drivers/CMSIS/Include/cmsis_gcc.h ****
880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
882:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
883:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
885:Drivers/CMSIS/Include/cmsis_gcc.h ****
886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
887:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
888:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
898:Drivers/CMSIS/Include/cmsis_gcc.h ****
899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
902:Drivers/CMSIS/Include/cmsis_gcc.h **** */
903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop")
904:Drivers/CMSIS/Include/cmsis_gcc.h ****
905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
906:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
907:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
908:Drivers/CMSIS/Include/cmsis_gcc.h **** */
909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi")
910:Drivers/CMSIS/Include/cmsis_gcc.h ****
911:Drivers/CMSIS/Include/cmsis_gcc.h ****
912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
913:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
914:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
915:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
916:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccEfj1JP.s page 47
917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe")
918:Drivers/CMSIS/Include/cmsis_gcc.h ****
919:Drivers/CMSIS/Include/cmsis_gcc.h ****
920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
921:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
922:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
923:Drivers/CMSIS/Include/cmsis_gcc.h **** */
924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
925:Drivers/CMSIS/Include/cmsis_gcc.h ****
926:Drivers/CMSIS/Include/cmsis_gcc.h ****
927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
928:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
929:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
930:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
931:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
932:Drivers/CMSIS/Include/cmsis_gcc.h **** */
933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
935:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
937:Drivers/CMSIS/Include/cmsis_gcc.h ****
938:Drivers/CMSIS/Include/cmsis_gcc.h ****
939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
940:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
941:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
942:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
943:Drivers/CMSIS/Include/cmsis_gcc.h **** */
944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
946:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
948:Drivers/CMSIS/Include/cmsis_gcc.h ****
949:Drivers/CMSIS/Include/cmsis_gcc.h ****
950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
951:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier
952:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before
953:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
954:Drivers/CMSIS/Include/cmsis_gcc.h **** */
955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
957:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
958:Drivers/CMSIS/Include/cmsis_gcc.h **** }
959:Drivers/CMSIS/Include/cmsis_gcc.h ****
960:Drivers/CMSIS/Include/cmsis_gcc.h ****
961:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
962:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit)
963:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
964:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
965:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
966:Drivers/CMSIS/Include/cmsis_gcc.h **** */
967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
968:Drivers/CMSIS/Include/cmsis_gcc.h **** {
969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
970:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value);
971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
972:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
973:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccEfj1JP.s page 48
974:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
975:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
977:Drivers/CMSIS/Include/cmsis_gcc.h **** }
978:Drivers/CMSIS/Include/cmsis_gcc.h ****
979:Drivers/CMSIS/Include/cmsis_gcc.h ****
980:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
981:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
982:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes
983:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
984:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
985:Drivers/CMSIS/Include/cmsis_gcc.h **** */
986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
987:Drivers/CMSIS/Include/cmsis_gcc.h **** {
988:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
989:Drivers/CMSIS/Include/cmsis_gcc.h ****
990:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
991:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
992:Drivers/CMSIS/Include/cmsis_gcc.h **** }
993:Drivers/CMSIS/Include/cmsis_gcc.h ****
994:Drivers/CMSIS/Include/cmsis_gcc.h ****
995:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
996:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
997:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
998:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
999:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
1000:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
1002:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1004:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value);
1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
1006:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result;
1007:Drivers/CMSIS/Include/cmsis_gcc.h ****
1008:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1009:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
1011:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1012:Drivers/CMSIS/Include/cmsis_gcc.h ****
1013:Drivers/CMSIS/Include/cmsis_gcc.h ****
1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1015:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
1016:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
1017:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate
1018:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate
1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value
1020:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
1022:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1023:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U;
1024:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U)
1025:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1026:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1;
1027:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1028:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2));
1029:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1030:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccEfj1JP.s page 49
1031:Drivers/CMSIS/Include/cmsis_gcc.h ****
1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1033:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint
1034:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state.
1035:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula
1036:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor.
1037:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break
1038:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value)
1040:Drivers/CMSIS/Include/cmsis_gcc.h ****
1041:Drivers/CMSIS/Include/cmsis_gcc.h ****
1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value
1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value.
1045:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse
1046:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value
1047:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
1049:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1050:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
1051:Drivers/CMSIS/Include/cmsis_gcc.h ****
1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1053:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1054:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1055:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
1057:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
1058:Drivers/CMSIS/Include/cmsis_gcc.h ****
1059:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
1060:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U)
1061:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1062:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U;
1063:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U;
1064:Drivers/CMSIS/Include/cmsis_gcc.h **** s--;
1065:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1066:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */
1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
1068:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
1069:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1070:Drivers/CMSIS/Include/cmsis_gcc.h ****
1071:Drivers/CMSIS/Include/cmsis_gcc.h ****
1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1073:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros
1074:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value.
1075:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros
1076:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value
1077:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
1079:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1080:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
1081:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_clz(0) is undefined behaviour, so handle this case specially.
1082:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM
1083:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any
1084:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it
1085:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero".
1086:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
1087:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction.
ARM GAS /tmp/ccEfj1JP.s page 50
1088:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1089:Drivers/CMSIS/Include/cmsis_gcc.h **** if (value == 0U)
1090:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1091:Drivers/CMSIS/Include/cmsis_gcc.h **** return 32U;
1092:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1093:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_clz(value);
1094:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1095:Drivers/CMSIS/Include/cmsis_gcc.h ****
1096:Drivers/CMSIS/Include/cmsis_gcc.h ****
1097:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1098:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1099:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1100:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1101:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1102:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit)
1103:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value.
1104:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
1105:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr)
1106:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1107:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
1108:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1109:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
1110:Drivers/CMSIS/Include/cmsis_gcc.h ****
1111:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1112:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
1113:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
1114:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1115:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern.
1116:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1117:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
1118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
1119:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */
1120:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1121:Drivers/CMSIS/Include/cmsis_gcc.h ****
1122:Drivers/CMSIS/Include/cmsis_gcc.h ****
1123:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1124:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit)
1125:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values.
1126:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
1127:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr)
1128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
1130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1131:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
1132:Drivers/CMSIS/Include/cmsis_gcc.h ****
1133:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1134:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
1135:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
1136:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1137:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern.
1138:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1139:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
1140:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
1141:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */
1142:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1143:Drivers/CMSIS/Include/cmsis_gcc.h ****
1144:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccEfj1JP.s page 51
1145:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1146:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit)
1147:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values.
1148:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data
1149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr)
1150:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
605 .loc 2 1151 31 discriminator 1 view .LVU152
606 .LBB24:
1152:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
607 .loc 2 1153 5 discriminator 1 view .LVU153
1154:Drivers/CMSIS/Include/cmsis_gcc.h ****
1155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
608 .loc 2 1155 4 discriminator 1 view .LVU154
609 .syntax unified
610 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
611 0010 52E8003F ldrex r3, [r2]
612 @ 0 "" 2
613 .LVL46:
1156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
614 .loc 2 1156 4 discriminator 1 view .LVU155
615 .loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU156
616 .thumb
617 .syntax unified
618 .LBE24:
619 .LBE23:
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
620 .loc 1 486 3 discriminator 1 view .LVU157
621 0014 43F00203 orr r3, r3, #2
622 .LVL47:
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
623 .loc 1 486 3 is_stmt 1 discriminator 1 view .LVU158
624 .LBB25:
625 .LBI25:
1157:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1158:Drivers/CMSIS/Include/cmsis_gcc.h ****
1159:Drivers/CMSIS/Include/cmsis_gcc.h ****
1160:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1161:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit)
1162:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values.
1163:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
1164:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
1165:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
1166:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
1167:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1168:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
1169:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1170:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
1171:Drivers/CMSIS/Include/cmsis_gcc.h ****
1172:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
1173:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
1174:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1175:Drivers/CMSIS/Include/cmsis_gcc.h ****
1176:Drivers/CMSIS/Include/cmsis_gcc.h ****
1177:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1178:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit)
ARM GAS /tmp/ccEfj1JP.s page 52
1179:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values.
1180:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
1181:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
1182:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
1183:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
1184:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1185:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
1186:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1187:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
1188:Drivers/CMSIS/Include/cmsis_gcc.h ****
1189:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
1190:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
1191:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1192:Drivers/CMSIS/Include/cmsis_gcc.h ****
1193:Drivers/CMSIS/Include/cmsis_gcc.h ****
1194:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit)
1196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values.
1197:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store
1198:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location
1199:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded
1200:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed
1201:Drivers/CMSIS/Include/cmsis_gcc.h **** */
1202:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
626 .loc 2 1202 31 discriminator 1 view .LVU159
627 .LBB26:
1203:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1204:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
628 .loc 2 1204 4 discriminator 1 view .LVU160
1205:Drivers/CMSIS/Include/cmsis_gcc.h ****
1206:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
629 .loc 2 1206 4 discriminator 1 view .LVU161
630 .syntax unified
631 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
632 0018 42E80031 strex r1, r3, [r2]
633 @ 0 "" 2
634 .LVL48:
1207:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
635 .loc 2 1207 4 discriminator 1 view .LVU162
636 .loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU163
637 .thumb
638 .syntax unified
639 .LBE26:
640 .LBE25:
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
641 .loc 1 486 3 discriminator 1 view .LVU164
642 001c 0029 cmp r1, #0
643 001e F6D1 bne .L42
644 .LBE22:
486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
645 .loc 1 486 3 is_stmt 1 discriminator 2 view .LVU165
489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
646 .loc 1 489 3 discriminator 2 view .LVU166
489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
647 .loc 1 489 3 discriminator 2 view .LVU167
648 0020 0023 movs r3, #0
649 .LVL49:
ARM GAS /tmp/ccEfj1JP.s page 53
489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
650 .loc 1 489 3 is_stmt 0 discriminator 2 view .LVU168
651 0022 80F88030 strb r3, [r0, #128]
489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
652 .loc 1 489 3 is_stmt 1 discriminator 2 view .LVU169
491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
653 .loc 1 491 3 discriminator 2 view .LVU170
491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
654 .loc 1 491 10 is_stmt 0 discriminator 2 view .LVU171
655 0026 1846 mov r0, r3
656 .LVL50:
491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
657 .loc 1 491 10 discriminator 2 view .LVU172
658 0028 7047 bx lr
659 .LVL51:
660 .L43:
483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
661 .loc 1 483 3 view .LVU173
662 002a 0220 movs r0, #2
663 .LVL52:
492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
664 .loc 1 492 1 view .LVU174
665 002c 7047 bx lr
666 .cfi_endproc
667 .LFE335:
669 .section .text.HAL_UARTEx_DisableStopMode,"ax",%progbits
670 .align 1
671 .global HAL_UARTEx_DisableStopMode
672 .syntax unified
673 .thumb
674 .thumb_func
676 HAL_UARTEx_DisableStopMode:
677 .LVL53:
678 .LFB336:
500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */
679 .loc 1 500 1 is_stmt 1 view -0
680 .cfi_startproc
681 @ args = 0, pretend = 0, frame = 0
682 @ frame_needed = 0, uses_anonymous_args = 0
683 @ link register save eliminated.
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
684 .loc 1 502 3 view .LVU176
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
685 .loc 1 502 3 view .LVU177
686 0000 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
687 0004 012B cmp r3, #1
688 0006 10D0 beq .L47
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
689 .loc 1 502 3 discriminator 2 view .LVU178
690 0008 0123 movs r3, #1
691 000a 80F88030 strb r3, [r0, #128]
692 .L46:
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
693 .loc 1 502 3 discriminator 1 view .LVU179
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
694 .loc 1 505 3 discriminator 1 view .LVU180
695 .LBB27:
ARM GAS /tmp/ccEfj1JP.s page 54
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
696 .loc 1 505 3 discriminator 1 view .LVU181
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
697 .loc 1 505 3 discriminator 1 view .LVU182
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
698 .loc 1 505 3 discriminator 1 view .LVU183
699 000e 0268 ldr r2, [r0]
700 .LVL54:
701 .LBB28:
702 .LBI28:
1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
703 .loc 2 1151 31 discriminator 1 view .LVU184
704 .LBB29:
1153:Drivers/CMSIS/Include/cmsis_gcc.h ****
705 .loc 2 1153 5 discriminator 1 view .LVU185
1155:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
706 .loc 2 1155 4 discriminator 1 view .LVU186
707 .syntax unified
708 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
709 0010 52E8003F ldrex r3, [r2]
710 @ 0 "" 2
711 .LVL55:
1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
712 .loc 2 1156 4 discriminator 1 view .LVU187
1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
713 .loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU188
714 .thumb
715 .syntax unified
716 .LBE29:
717 .LBE28:
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
718 .loc 1 505 3 discriminator 1 view .LVU189
719 0014 23F00203 bic r3, r3, #2
720 .LVL56:
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
721 .loc 1 505 3 is_stmt 1 discriminator 1 view .LVU190
722 .LBB30:
723 .LBI30:
1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
724 .loc 2 1202 31 discriminator 1 view .LVU191
725 .LBB31:
1204:Drivers/CMSIS/Include/cmsis_gcc.h ****
726 .loc 2 1204 4 discriminator 1 view .LVU192
1206:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
727 .loc 2 1206 4 discriminator 1 view .LVU193
728 .syntax unified
729 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
730 0018 42E80031 strex r1, r3, [r2]
731 @ 0 "" 2
732 .LVL57:
733 .loc 2 1207 4 discriminator 1 view .LVU194
734 .loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU195
735 .thumb
736 .syntax unified
737 .LBE31:
738 .LBE30:
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 55
739 .loc 1 505 3 discriminator 1 view .LVU196
740 001c 0029 cmp r1, #0
741 001e F6D1 bne .L46
742 .LBE27:
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
743 .loc 1 505 3 is_stmt 1 discriminator 2 view .LVU197
508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
744 .loc 1 508 3 discriminator 2 view .LVU198
508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
745 .loc 1 508 3 discriminator 2 view .LVU199
746 0020 0023 movs r3, #0
747 .LVL58:
508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
748 .loc 1 508 3 is_stmt 0 discriminator 2 view .LVU200
749 0022 80F88030 strb r3, [r0, #128]
508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
750 .loc 1 508 3 is_stmt 1 discriminator 2 view .LVU201
510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
751 .loc 1 510 3 discriminator 2 view .LVU202
510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
752 .loc 1 510 10 is_stmt 0 discriminator 2 view .LVU203
753 0026 1846 mov r0, r3
754 .LVL59:
510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
755 .loc 1 510 10 discriminator 2 view .LVU204
756 0028 7047 bx lr
757 .LVL60:
758 .L47:
502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
759 .loc 1 502 3 view .LVU205
760 002a 0220 movs r0, #2
761 .LVL61:
511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
762 .loc 1 511 1 view .LVU206
763 002c 7047 bx lr
764 .cfi_endproc
765 .LFE336:
767 .section .text.HAL_UARTEx_EnableFifoMode,"ax",%progbits
768 .align 1
769 .global HAL_UARTEx_EnableFifoMode
770 .syntax unified
771 .thumb
772 .thumb_func
774 HAL_UARTEx_EnableFifoMode:
775 .LVL62:
776 .LFB337:
519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
777 .loc 1 519 1 is_stmt 1 view -0
778 .cfi_startproc
779 @ args = 0, pretend = 0, frame = 0
780 @ frame_needed = 0, uses_anonymous_args = 0
520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
781 .loc 1 520 3 view .LVU208
523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
782 .loc 1 523 3 view .LVU209
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
783 .loc 1 526 3 view .LVU210
ARM GAS /tmp/ccEfj1JP.s page 56
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
784 .loc 1 526 3 view .LVU211
785 0000 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
786 0004 012B cmp r3, #1
787 0006 1DD0 beq .L50
519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
788 .loc 1 519 1 is_stmt 0 discriminator 2 view .LVU212
789 0008 10B5 push {r4, lr}
790 .LCFI12:
791 .cfi_def_cfa_offset 8
792 .cfi_offset 4, -8
793 .cfi_offset 14, -4
794 000a 0446 mov r4, r0
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
795 .loc 1 526 3 is_stmt 1 discriminator 2 view .LVU213
796 000c 0123 movs r3, #1
797 000e 80F88030 strb r3, [r0, #128]
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
798 .loc 1 526 3 discriminator 2 view .LVU214
528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
799 .loc 1 528 3 discriminator 2 view .LVU215
528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
800 .loc 1 528 17 is_stmt 0 discriminator 2 view .LVU216
801 0012 2423 movs r3, #36
802 0014 C0F88430 str r3, [r0, #132]
531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
803 .loc 1 531 3 is_stmt 1 discriminator 2 view .LVU217
531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
804 .loc 1 531 12 is_stmt 0 discriminator 2 view .LVU218
805 0018 0268 ldr r2, [r0]
531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
806 .loc 1 531 10 discriminator 2 view .LVU219
807 001a 1368 ldr r3, [r2]
808 .LVL63:
534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
809 .loc 1 534 3 is_stmt 1 discriminator 2 view .LVU220
810 001c 1168 ldr r1, [r2]
811 001e 21F00101 bic r1, r1, #1
812 0022 1160 str r1, [r2]
537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_ENABLE;
813 .loc 1 537 3 discriminator 2 view .LVU221
814 0024 43F00053 orr r3, r3, #536870912
815 .LVL64:
538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
816 .loc 1 538 3 discriminator 2 view .LVU222
538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
817 .loc 1 538 19 is_stmt 0 discriminator 2 view .LVU223
818 0028 4FF00052 mov r2, #536870912
819 002c 4266 str r2, [r0, #100]
541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
820 .loc 1 541 3 is_stmt 1 discriminator 2 view .LVU224
821 002e 0268 ldr r2, [r0]
822 0030 1360 str r3, [r2]
544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
823 .loc 1 544 3 discriminator 2 view .LVU225
824 0032 FFF7FEFF bl UARTEx_SetNbDataToProcess
825 .LVL65:
ARM GAS /tmp/ccEfj1JP.s page 57
546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
826 .loc 1 546 3 discriminator 2 view .LVU226
546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
827 .loc 1 546 17 is_stmt 0 discriminator 2 view .LVU227
828 0036 2023 movs r3, #32
829 0038 C4F88430 str r3, [r4, #132]
549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
830 .loc 1 549 3 is_stmt 1 discriminator 2 view .LVU228
549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
831 .loc 1 549 3 discriminator 2 view .LVU229
832 003c 0020 movs r0, #0
833 003e 84F88000 strb r0, [r4, #128]
549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
834 .loc 1 549 3 discriminator 2 view .LVU230
551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
835 .loc 1 551 3 discriminator 2 view .LVU231
552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
836 .loc 1 552 1 is_stmt 0 discriminator 2 view .LVU232
837 0042 10BD pop {r4, pc}
838 .LVL66:
839 .L50:
840 .LCFI13:
841 .cfi_def_cfa_offset 0
842 .cfi_restore 4
843 .cfi_restore 14
526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
844 .loc 1 526 3 view .LVU233
845 0044 0220 movs r0, #2
846 .LVL67:
552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
847 .loc 1 552 1 view .LVU234
848 0046 7047 bx lr
849 .cfi_endproc
850 .LFE337:
852 .section .text.HAL_UARTEx_DisableFifoMode,"ax",%progbits
853 .align 1
854 .global HAL_UARTEx_DisableFifoMode
855 .syntax unified
856 .thumb
857 .thumb_func
859 HAL_UARTEx_DisableFifoMode:
860 .LVL68:
861 .LFB338:
560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
862 .loc 1 560 1 is_stmt 1 view -0
863 .cfi_startproc
864 @ args = 0, pretend = 0, frame = 0
865 @ frame_needed = 0, uses_anonymous_args = 0
866 @ link register save eliminated.
561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
867 .loc 1 561 3 view .LVU236
564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
868 .loc 1 564 3 view .LVU237
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
869 .loc 1 567 3 view .LVU238
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
870 .loc 1 567 3 view .LVU239
ARM GAS /tmp/ccEfj1JP.s page 58
871 0000 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
872 0004 012B cmp r3, #1
873 0006 18D0 beq .L57
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
874 .loc 1 567 3 discriminator 2 view .LVU240
875 0008 0123 movs r3, #1
876 000a 80F88030 strb r3, [r0, #128]
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
877 .loc 1 567 3 discriminator 2 view .LVU241
569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
878 .loc 1 569 3 discriminator 2 view .LVU242
569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
879 .loc 1 569 17 is_stmt 0 discriminator 2 view .LVU243
880 000e 2423 movs r3, #36
881 0010 C0F88430 str r3, [r0, #132]
572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
882 .loc 1 572 3 is_stmt 1 discriminator 2 view .LVU244
572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
883 .loc 1 572 12 is_stmt 0 discriminator 2 view .LVU245
884 0014 0368 ldr r3, [r0]
572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
885 .loc 1 572 10 discriminator 2 view .LVU246
886 0016 1A68 ldr r2, [r3]
887 .LVL69:
575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
888 .loc 1 575 3 is_stmt 1 discriminator 2 view .LVU247
889 0018 1968 ldr r1, [r3]
890 001a 21F00101 bic r1, r1, #1
891 001e 1960 str r1, [r3]
578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_DISABLE;
892 .loc 1 578 3 discriminator 2 view .LVU248
893 0020 22F00052 bic r2, r2, #536870912
894 .LVL70:
579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
895 .loc 1 579 3 discriminator 2 view .LVU249
579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
896 .loc 1 579 19 is_stmt 0 discriminator 2 view .LVU250
897 0024 0023 movs r3, #0
898 0026 4366 str r3, [r0, #100]
582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
899 .loc 1 582 3 is_stmt 1 discriminator 2 view .LVU251
900 0028 0168 ldr r1, [r0]
901 002a 0A60 str r2, [r1]
584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
902 .loc 1 584 3 discriminator 2 view .LVU252
584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
903 .loc 1 584 17 is_stmt 0 discriminator 2 view .LVU253
904 002c 2022 movs r2, #32
905 .LVL71:
584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
906 .loc 1 584 17 discriminator 2 view .LVU254
907 002e C0F88420 str r2, [r0, #132]
908 .LVL72:
587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
909 .loc 1 587 3 is_stmt 1 discriminator 2 view .LVU255
587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
910 .loc 1 587 3 discriminator 2 view .LVU256
ARM GAS /tmp/ccEfj1JP.s page 59
911 0032 80F88030 strb r3, [r0, #128]
587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
912 .loc 1 587 3 discriminator 2 view .LVU257
589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
913 .loc 1 589 3 discriminator 2 view .LVU258
589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
914 .loc 1 589 10 is_stmt 0 discriminator 2 view .LVU259
915 0036 1846 mov r0, r3
916 .LVL73:
589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
917 .loc 1 589 10 discriminator 2 view .LVU260
918 0038 7047 bx lr
919 .LVL74:
920 .L57:
567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
921 .loc 1 567 3 view .LVU261
922 003a 0220 movs r0, #2
923 .LVL75:
590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
924 .loc 1 590 1 view .LVU262
925 003c 7047 bx lr
926 .cfi_endproc
927 .LFE338:
929 .section .text.HAL_UARTEx_SetTxFifoThreshold,"ax",%progbits
930 .align 1
931 .global HAL_UARTEx_SetTxFifoThreshold
932 .syntax unified
933 .thumb
934 .thumb_func
936 HAL_UARTEx_SetTxFifoThreshold:
937 .LVL76:
938 .LFB339:
606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
939 .loc 1 606 1 is_stmt 1 view -0
940 .cfi_startproc
941 @ args = 0, pretend = 0, frame = 0
942 @ frame_needed = 0, uses_anonymous_args = 0
606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
943 .loc 1 606 1 is_stmt 0 view .LVU264
944 0000 38B5 push {r3, r4, r5, lr}
945 .LCFI14:
946 .cfi_def_cfa_offset 16
947 .cfi_offset 3, -16
948 .cfi_offset 4, -12
949 .cfi_offset 5, -8
950 .cfi_offset 14, -4
607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
951 .loc 1 607 3 is_stmt 1 view .LVU265
610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
952 .loc 1 610 3 view .LVU266
611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
953 .loc 1 611 3 view .LVU267
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
954 .loc 1 614 3 view .LVU268
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
955 .loc 1 614 3 view .LVU269
956 0002 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
ARM GAS /tmp/ccEfj1JP.s page 60
957 0006 012B cmp r3, #1
958 0008 1DD0 beq .L60
959 000a 0446 mov r4, r0
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
960 .loc 1 614 3 discriminator 2 view .LVU270
961 000c 0123 movs r3, #1
962 000e 80F88030 strb r3, [r0, #128]
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
963 .loc 1 614 3 discriminator 2 view .LVU271
616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
964 .loc 1 616 3 discriminator 2 view .LVU272
616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
965 .loc 1 616 17 is_stmt 0 discriminator 2 view .LVU273
966 0012 2423 movs r3, #36
967 0014 C0F88430 str r3, [r0, #132]
619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
968 .loc 1 619 3 is_stmt 1 discriminator 2 view .LVU274
619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
969 .loc 1 619 12 is_stmt 0 discriminator 2 view .LVU275
970 0018 0368 ldr r3, [r0]
619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
971 .loc 1 619 10 discriminator 2 view .LVU276
972 001a 1D68 ldr r5, [r3]
973 .LVL77:
622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
974 .loc 1 622 3 is_stmt 1 discriminator 2 view .LVU277
975 001c 1A68 ldr r2, [r3]
976 001e 22F00102 bic r2, r2, #1
977 0022 1A60 str r2, [r3]
625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
978 .loc 1 625 3 discriminator 2 view .LVU278
979 0024 0268 ldr r2, [r0]
980 0026 9368 ldr r3, [r2, #8]
981 0028 23F06043 bic r3, r3, #-536870912
982 002c 1943 orrs r1, r1, r3
983 .LVL78:
625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
984 .loc 1 625 3 is_stmt 0 discriminator 2 view .LVU279
985 002e 9160 str r1, [r2, #8]
628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
986 .loc 1 628 3 is_stmt 1 discriminator 2 view .LVU280
987 0030 FFF7FEFF bl UARTEx_SetNbDataToProcess
988 .LVL79:
631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
989 .loc 1 631 3 discriminator 2 view .LVU281
990 0034 2368 ldr r3, [r4]
991 0036 1D60 str r5, [r3]
633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
992 .loc 1 633 3 discriminator 2 view .LVU282
633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
993 .loc 1 633 17 is_stmt 0 discriminator 2 view .LVU283
994 0038 2023 movs r3, #32
995 003a C4F88430 str r3, [r4, #132]
636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
996 .loc 1 636 3 is_stmt 1 discriminator 2 view .LVU284
636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
997 .loc 1 636 3 discriminator 2 view .LVU285
ARM GAS /tmp/ccEfj1JP.s page 61
998 003e 0020 movs r0, #0
999 0040 84F88000 strb r0, [r4, #128]
636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1000 .loc 1 636 3 discriminator 2 view .LVU286
638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1001 .loc 1 638 3 discriminator 2 view .LVU287
1002 .LVL80:
1003 .L59:
639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1004 .loc 1 639 1 is_stmt 0 view .LVU288
1005 0044 38BD pop {r3, r4, r5, pc}
1006 .LVL81:
1007 .L60:
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1008 .loc 1 614 3 view .LVU289
1009 0046 0220 movs r0, #2
1010 .LVL82:
614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1011 .loc 1 614 3 view .LVU290
1012 0048 FCE7 b .L59
1013 .cfi_endproc
1014 .LFE339:
1016 .section .text.HAL_UARTEx_SetRxFifoThreshold,"ax",%progbits
1017 .align 1
1018 .global HAL_UARTEx_SetRxFifoThreshold
1019 .syntax unified
1020 .thumb
1021 .thumb_func
1023 HAL_UARTEx_SetRxFifoThreshold:
1024 .LVL83:
1025 .LFB340:
655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
1026 .loc 1 655 1 is_stmt 1 view -0
1027 .cfi_startproc
1028 @ args = 0, pretend = 0, frame = 0
1029 @ frame_needed = 0, uses_anonymous_args = 0
655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1;
1030 .loc 1 655 1 is_stmt 0 view .LVU292
1031 0000 38B5 push {r3, r4, r5, lr}
1032 .LCFI15:
1033 .cfi_def_cfa_offset 16
1034 .cfi_offset 3, -16
1035 .cfi_offset 4, -12
1036 .cfi_offset 5, -8
1037 .cfi_offset 14, -4
656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1038 .loc 1 656 3 is_stmt 1 view .LVU293
659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
1039 .loc 1 659 3 view .LVU294
660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1040 .loc 1 660 3 view .LVU295
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1041 .loc 1 663 3 view .LVU296
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1042 .loc 1 663 3 view .LVU297
1043 0002 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
1044 0006 012B cmp r3, #1
ARM GAS /tmp/ccEfj1JP.s page 62
1045 0008 1DD0 beq .L64
1046 000a 0446 mov r4, r0
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1047 .loc 1 663 3 discriminator 2 view .LVU298
1048 000c 0123 movs r3, #1
1049 000e 80F88030 strb r3, [r0, #128]
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1050 .loc 1 663 3 discriminator 2 view .LVU299
665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1051 .loc 1 665 3 discriminator 2 view .LVU300
665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1052 .loc 1 665 17 is_stmt 0 discriminator 2 view .LVU301
1053 0012 2423 movs r3, #36
1054 0014 C0F88430 str r3, [r0, #132]
668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1055 .loc 1 668 3 is_stmt 1 discriminator 2 view .LVU302
668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1056 .loc 1 668 12 is_stmt 0 discriminator 2 view .LVU303
1057 0018 0368 ldr r3, [r0]
668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1058 .loc 1 668 10 discriminator 2 view .LVU304
1059 001a 1D68 ldr r5, [r3]
1060 .LVL84:
671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1061 .loc 1 671 3 is_stmt 1 discriminator 2 view .LVU305
1062 001c 1A68 ldr r2, [r3]
1063 001e 22F00102 bic r2, r2, #1
1064 0022 1A60 str r2, [r3]
674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1065 .loc 1 674 3 discriminator 2 view .LVU306
1066 0024 0268 ldr r2, [r0]
1067 0026 9368 ldr r3, [r2, #8]
1068 0028 23F06063 bic r3, r3, #234881024
1069 002c 1943 orrs r1, r1, r3
1070 .LVL85:
674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1071 .loc 1 674 3 is_stmt 0 discriminator 2 view .LVU307
1072 002e 9160 str r1, [r2, #8]
677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1073 .loc 1 677 3 is_stmt 1 discriminator 2 view .LVU308
1074 0030 FFF7FEFF bl UARTEx_SetNbDataToProcess
1075 .LVL86:
680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1076 .loc 1 680 3 discriminator 2 view .LVU309
1077 0034 2368 ldr r3, [r4]
1078 0036 1D60 str r5, [r3]
682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1079 .loc 1 682 3 discriminator 2 view .LVU310
682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1080 .loc 1 682 17 is_stmt 0 discriminator 2 view .LVU311
1081 0038 2023 movs r3, #32
1082 003a C4F88430 str r3, [r4, #132]
685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1083 .loc 1 685 3 is_stmt 1 discriminator 2 view .LVU312
685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1084 .loc 1 685 3 discriminator 2 view .LVU313
1085 003e 0020 movs r0, #0
ARM GAS /tmp/ccEfj1JP.s page 63
1086 0040 84F88000 strb r0, [r4, #128]
685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1087 .loc 1 685 3 discriminator 2 view .LVU314
687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1088 .loc 1 687 3 discriminator 2 view .LVU315
1089 .LVL87:
1090 .L63:
688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1091 .loc 1 688 1 is_stmt 0 view .LVU316
1092 0044 38BD pop {r3, r4, r5, pc}
1093 .LVL88:
1094 .L64:
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1095 .loc 1 663 3 view .LVU317
1096 0046 0220 movs r0, #2
1097 .LVL89:
663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1098 .loc 1 663 3 view .LVU318
1099 0048 FCE7 b .L63
1100 .cfi_endproc
1101 .LFE340:
1103 .section .text.HAL_UARTEx_ReceiveToIdle,"ax",%progbits
1104 .align 1
1105 .global HAL_UARTEx_ReceiveToIdle
1106 .syntax unified
1107 .thumb
1108 .thumb_func
1110 HAL_UARTEx_ReceiveToIdle:
1111 .LVL90:
1112 .LFB341:
713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t *pdata8bits;
1113 .loc 1 713 1 is_stmt 1 view -0
1114 .cfi_startproc
1115 @ args = 4, pretend = 0, frame = 0
1116 @ frame_needed = 0, uses_anonymous_args = 0
713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t *pdata8bits;
1117 .loc 1 713 1 is_stmt 0 view .LVU320
1118 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr}
1119 .LCFI16:
1120 .cfi_def_cfa_offset 32
1121 .cfi_offset 4, -32
1122 .cfi_offset 5, -28
1123 .cfi_offset 6, -24
1124 .cfi_offset 7, -20
1125 .cfi_offset 8, -16
1126 .cfi_offset 9, -12
1127 .cfi_offset 10, -8
1128 .cfi_offset 14, -4
1129 0004 1D46 mov r5, r3
1130 0006 089E ldr r6, [sp, #32]
714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t *pdata16bits;
1131 .loc 1 714 3 is_stmt 1 view .LVU321
715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t uhMask;
1132 .loc 1 715 3 view .LVU322
716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart;
1133 .loc 1 716 3 view .LVU323
717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
ARM GAS /tmp/ccEfj1JP.s page 64
1134 .loc 1 717 3 view .LVU324
720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1135 .loc 1 720 3 view .LVU325
720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1136 .loc 1 720 12 is_stmt 0 view .LVU326
1137 0008 D0F88830 ldr r3, [r0, #136]
1138 .LVL91:
720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1139 .loc 1 720 6 view .LVU327
1140 000c 202B cmp r3, #32
1141 000e 40F0A980 bne .L84
1142 0012 0446 mov r4, r0
1143 0014 0F46 mov r7, r1
1144 0016 9146 mov r9, r2
722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1145 .loc 1 722 5 is_stmt 1 view .LVU328
722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1146 .loc 1 722 8 is_stmt 0 view .LVU329
1147 0018 0029 cmp r1, #0
1148 001a 00F0A680 beq .L85
722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1149 .loc 1 722 25 discriminator 1 view .LVU330
1150 001e 002A cmp r2, #0
1151 0020 00F0A580 beq .L86
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1152 .loc 1 727 5 is_stmt 1 view .LVU331
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1153 .loc 1 727 5 view .LVU332
1154 0024 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
1155 0028 012B cmp r3, #1
1156 002a 00F0A280 beq .L87
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1157 .loc 1 727 5 discriminator 2 view .LVU333
1158 002e 0123 movs r3, #1
1159 0030 80F88030 strb r3, [r0, #128]
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1160 .loc 1 727 5 discriminator 2 view .LVU334
729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX;
1161 .loc 1 729 5 discriminator 2 view .LVU335
729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX;
1162 .loc 1 729 22 is_stmt 0 discriminator 2 view .LVU336
1163 0034 0022 movs r2, #0
1164 .LVL92:
729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX;
1165 .loc 1 729 22 discriminator 2 view .LVU337
1166 0036 C0F88C20 str r2, [r0, #140]
730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
1167 .loc 1 730 5 is_stmt 1 discriminator 2 view .LVU338
730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
1168 .loc 1 730 20 is_stmt 0 discriminator 2 view .LVU339
1169 003a 2222 movs r2, #34
1170 003c C0F88820 str r2, [r0, #136]
731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1171 .loc 1 731 5 is_stmt 1 discriminator 2 view .LVU340
731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1172 .loc 1 731 26 is_stmt 0 discriminator 2 view .LVU341
1173 0040 C366 str r3, [r0, #108]
ARM GAS /tmp/ccEfj1JP.s page 65
734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1174 .loc 1 734 5 is_stmt 1 discriminator 2 view .LVU342
734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1175 .loc 1 734 17 is_stmt 0 discriminator 2 view .LVU343
1176 0042 FFF7FEFF bl HAL_GetTick
1177 .LVL93:
734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1178 .loc 1 734 17 discriminator 2 view .LVU344
1179 0046 8046 mov r8, r0
1180 .LVL94:
736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount = Size;
1181 .loc 1 736 5 is_stmt 1 discriminator 2 view .LVU345
736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount = Size;
1182 .loc 1 736 24 is_stmt 0 discriminator 2 view .LVU346
1183 0048 A4F85C90 strh r9, [r4, #92] @ movhi
737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1184 .loc 1 737 5 is_stmt 1 discriminator 2 view .LVU347
737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1185 .loc 1 737 24 is_stmt 0 discriminator 2 view .LVU348
1186 004c A4F85E90 strh r9, [r4, #94] @ movhi
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1187 .loc 1 740 5 is_stmt 1 discriminator 2 view .LVU349
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1188 .loc 1 740 5 discriminator 2 view .LVU350
1189 0050 A368 ldr r3, [r4, #8]
1190 0052 B3F5805F cmp r3, #4096
1191 0056 06D0 beq .L91
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1192 .loc 1 740 5 discriminator 2 view .LVU351
1193 0058 A3B9 cbnz r3, .L71
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1194 .loc 1 740 5 discriminator 5 view .LVU352
1195 005a 2269 ldr r2, [r4, #16]
1196 005c 72B9 cbnz r2, .L72
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1197 .loc 1 740 5 discriminator 7 view .LVU353
1198 005e FF22 movs r2, #255
1199 0060 A4F86020 strh r2, [r4, #96] @ movhi
1200 0064 14E0 b .L70
1201 .L91:
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1202 .loc 1 740 5 discriminator 1 view .LVU354
1203 0066 2269 ldr r2, [r4, #16]
1204 0068 22B9 cbnz r2, .L69
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1205 .loc 1 740 5 discriminator 3 view .LVU355
1206 006a 40F2FF12 movw r2, #511
1207 006e A4F86020 strh r2, [r4, #96] @ movhi
1208 0072 0DE0 b .L70
1209 .L69:
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1210 .loc 1 740 5 discriminator 4 view .LVU356
1211 0074 FF22 movs r2, #255
1212 0076 A4F86020 strh r2, [r4, #96] @ movhi
1213 007a 09E0 b .L70
1214 .L72:
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
ARM GAS /tmp/ccEfj1JP.s page 66
1215 .loc 1 740 5 discriminator 8 view .LVU357
1216 007c 7F22 movs r2, #127
1217 007e A4F86020 strh r2, [r4, #96] @ movhi
1218 0082 05E0 b .L70
1219 .L71:
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1220 .loc 1 740 5 discriminator 6 view .LVU358
1221 0084 B3F1805F cmp r3, #268435456
1222 0088 0ED0 beq .L92
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1223 .loc 1 740 5 discriminator 10 view .LVU359
1224 008a 0022 movs r2, #0
1225 008c A4F86020 strh r2, [r4, #96] @ movhi
1226 .L70:
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1227 .loc 1 740 5 discriminator 13 view .LVU360
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1228 .loc 1 741 5 discriminator 13 view .LVU361
741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1229 .loc 1 741 12 is_stmt 0 discriminator 13 view .LVU362
1230 0090 B4F86090 ldrh r9, [r4, #96]
1231 .LVL95:
744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1232 .loc 1 744 5 is_stmt 1 discriminator 13 view .LVU363
744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1233 .loc 1 744 8 is_stmt 0 discriminator 13 view .LVU364
1234 0094 B3F5805F cmp r3, #4096
1235 0098 10D0 beq .L93
752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1236 .loc 1 752 19 view .LVU365
1237 009a 4FF0000A mov r10, #0
1238 .LVL96:
1239 .L75:
755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1240 .loc 1 755 5 is_stmt 1 view .LVU366
755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1241 .loc 1 755 5 view .LVU367
1242 009e 0023 movs r3, #0
1243 00a0 84F88030 strb r3, [r4, #128]
755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1244 .loc 1 755 5 view .LVU368
758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1245 .loc 1 758 5 view .LVU369
758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1246 .loc 1 758 12 is_stmt 0 view .LVU370
1247 00a4 2B80 strh r3, [r5] @ movhi
761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1248 .loc 1 761 5 is_stmt 1 view .LVU371
761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1249 .loc 1 761 11 is_stmt 0 view .LVU372
1250 00a6 28E0 b .L76
1251 .LVL97:
1252 .L92:
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1253 .loc 1 740 5 is_stmt 1 discriminator 9 view .LVU373
1254 00a8 2269 ldr r2, [r4, #16]
1255 00aa 1AB9 cbnz r2, .L74
ARM GAS /tmp/ccEfj1JP.s page 67
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1256 .loc 1 740 5 discriminator 11 view .LVU374
1257 00ac 7F22 movs r2, #127
1258 00ae A4F86020 strh r2, [r4, #96] @ movhi
1259 00b2 EDE7 b .L70
1260 .L74:
740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask;
1261 .loc 1 740 5 discriminator 12 view .LVU375
1262 00b4 3F22 movs r2, #63
1263 00b6 A4F86020 strh r2, [r4, #96] @ movhi
1264 00ba E9E7 b .L70
1265 .LVL98:
1266 .L93:
744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1267 .loc 1 744 71 is_stmt 0 discriminator 1 view .LVU376
1268 00bc 2369 ldr r3, [r4, #16]
744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1269 .loc 1 744 56 discriminator 1 view .LVU377
1270 00be 13B1 cbz r3, .L89
752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1271 .loc 1 752 19 view .LVU378
1272 00c0 4FF0000A mov r10, #0
1273 00c4 EBE7 b .L75
1274 .L89:
747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1275 .loc 1 747 19 view .LVU379
1276 00c6 BA46 mov r10, r7
746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData;
1277 .loc 1 746 19 view .LVU380
1278 00c8 0027 movs r7, #0
1279 .LVL99:
746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData;
1280 .loc 1 746 19 view .LVU381
1281 00ca E8E7 b .L75
1282 .LVL100:
1283 .L96:
773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1284 .loc 1 773 11 is_stmt 1 view .LVU382
773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1285 .loc 1 773 26 is_stmt 0 view .LVU383
1286 00cc 2023 movs r3, #32
1287 00ce C4F88830 str r3, [r4, #136]
775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1288 .loc 1 775 11 is_stmt 1 view .LVU384
775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1289 .loc 1 775 18 is_stmt 0 view .LVU385
1290 00d2 0020 movs r0, #0
1291 00d4 47E0 b .L67
1292 .L97:
784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++;
1293 .loc 1 784 11 is_stmt 1 view .LVU386
784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++;
1294 .loc 1 784 52 is_stmt 0 view .LVU387
1295 00d6 5B6A ldr r3, [r3, #36]
784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++;
1296 .loc 1 784 26 view .LVU388
1297 00d8 09EA0303 and r3, r9, r3
ARM GAS /tmp/ccEfj1JP.s page 68
784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++;
1298 .loc 1 784 24 view .LVU389
1299 00dc 2AF8023B strh r3, [r10], #2 @ movhi
1300 .LVL101:
785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1301 .loc 1 785 11 is_stmt 1 view .LVU390
1302 .L80:
793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount--;
1303 .loc 1 793 9 view .LVU391
1304 00e0 2B88 ldrh r3, [r5]
793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount--;
1305 .loc 1 793 16 is_stmt 0 view .LVU392
1306 00e2 0133 adds r3, r3, #1
1307 00e4 2B80 strh r3, [r5] @ movhi
794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1308 .loc 1 794 9 is_stmt 1 view .LVU393
794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1309 .loc 1 794 14 is_stmt 0 view .LVU394
1310 00e6 B4F85E30 ldrh r3, [r4, #94]
1311 00ea 9BB2 uxth r3, r3
794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1312 .loc 1 794 27 view .LVU395
1313 00ec 013B subs r3, r3, #1
1314 00ee 9BB2 uxth r3, r3
1315 00f0 A4F85E30 strh r3, [r4, #94] @ movhi
1316 .L78:
798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1317 .loc 1 798 7 is_stmt 1 view .LVU396
798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1318 .loc 1 798 10 is_stmt 0 view .LVU397
1319 00f4 B6F1FF3F cmp r6, #-1
1320 00f8 1BD1 bne .L94
1321 .L76:
761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1322 .loc 1 761 31 is_stmt 1 view .LVU398
761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1323 .loc 1 761 17 is_stmt 0 view .LVU399
1324 00fa B4F85E20 ldrh r2, [r4, #94]
1325 00fe 92B2 uxth r2, r2
761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1326 .loc 1 761 31 view .LVU400
1327 0100 22B3 cbz r2, .L95
764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1328 .loc 1 764 7 is_stmt 1 view .LVU401
764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1329 .loc 1 764 11 is_stmt 0 view .LVU402
1330 0102 2368 ldr r3, [r4]
1331 0104 DA69 ldr r2, [r3, #28]
764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1332 .loc 1 764 10 view .LVU403
1333 0106 12F0100F tst r2, #16
1334 010a 04D0 beq .L77
767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1335 .loc 1 767 9 is_stmt 1 view .LVU404
1336 010c 1022 movs r2, #16
1337 010e 1A62 str r2, [r3, #32]
771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
ARM GAS /tmp/ccEfj1JP.s page 69
1338 .loc 1 771 9 view .LVU405
771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1339 .loc 1 771 13 is_stmt 0 view .LVU406
1340 0110 2B88 ldrh r3, [r5]
771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1341 .loc 1 771 12 view .LVU407
1342 0112 002B cmp r3, #0
1343 0114 DAD1 bne .L96
1344 .L77:
780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1345 .loc 1 780 7 is_stmt 1 view .LVU408
780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1346 .loc 1 780 11 is_stmt 0 view .LVU409
1347 0116 2368 ldr r3, [r4]
1348 0118 DA69 ldr r2, [r3, #28]
780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1349 .loc 1 780 10 view .LVU410
1350 011a 12F0200F tst r2, #32
1351 011e E9D0 beq .L78
782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1352 .loc 1 782 9 is_stmt 1 view .LVU411
782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1353 .loc 1 782 12 is_stmt 0 view .LVU412
1354 0120 002F cmp r7, #0
1355 0122 D8D0 beq .L97
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++;
1356 .loc 1 789 11 is_stmt 1 view .LVU413
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++;
1357 .loc 1 789 50 is_stmt 0 view .LVU414
1358 0124 5A6A ldr r2, [r3, #36]
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++;
1359 .loc 1 789 58 view .LVU415
1360 0126 5FFA89F3 uxtb r3, r9
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++;
1361 .loc 1 789 25 view .LVU416
1362 012a 1340 ands r3, r3, r2
789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++;
1363 .loc 1 789 23 view .LVU417
1364 012c 07F8013B strb r3, [r7], #1
1365 .LVL102:
790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1366 .loc 1 790 11 is_stmt 1 view .LVU418
790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1367 .loc 1 790 11 is_stmt 0 view .LVU419
1368 0130 D6E7 b .L80
1369 .L94:
800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1370 .loc 1 800 9 is_stmt 1 view .LVU420
800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1371 .loc 1 800 15 is_stmt 0 view .LVU421
1372 0132 FFF7FEFF bl HAL_GetTick
1373 .LVL103:
800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1374 .loc 1 800 29 view .LVU422
1375 0136 A0EB0800 sub r0, r0, r8
800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1376 .loc 1 800 12 view .LVU423
ARM GAS /tmp/ccEfj1JP.s page 70
1377 013a B042 cmp r0, r6
1378 013c 01D8 bhi .L82
800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1379 .loc 1 800 53 discriminator 1 view .LVU424
1380 013e 002E cmp r6, #0
1381 0140 DBD1 bne .L76
1382 .L82:
802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1383 .loc 1 802 11 is_stmt 1 view .LVU425
802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1384 .loc 1 802 26 is_stmt 0 view .LVU426
1385 0142 2023 movs r3, #32
1386 0144 C4F88830 str r3, [r4, #136]
804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1387 .loc 1 804 11 is_stmt 1 view .LVU427
804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1388 .loc 1 804 18 is_stmt 0 view .LVU428
1389 0148 0320 movs r0, #3
1390 014a 0CE0 b .L67
1391 .L95:
810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */
1392 .loc 1 810 5 is_stmt 1 view .LVU429
810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */
1393 .loc 1 810 19 is_stmt 0 view .LVU430
1394 014c B4F85C30 ldrh r3, [r4, #92]
810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */
1395 .loc 1 810 39 view .LVU431
1396 0150 B4F85E20 ldrh r2, [r4, #94]
1397 0154 92B2 uxth r2, r2
810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */
1398 .loc 1 810 32 view .LVU432
1399 0156 9B1A subs r3, r3, r2
810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */
1400 .loc 1 810 12 view .LVU433
1401 0158 2B80 strh r3, [r5] @ movhi
812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1402 .loc 1 812 5 is_stmt 1 view .LVU434
812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1403 .loc 1 812 20 is_stmt 0 view .LVU435
1404 015a 2023 movs r3, #32
1405 015c C4F88830 str r3, [r4, #136]
814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1406 .loc 1 814 5 is_stmt 1 view .LVU436
814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1407 .loc 1 814 12 is_stmt 0 view .LVU437
1408 0160 0020 movs r0, #0
1409 0162 00E0 b .L67
1410 .LVL104:
1411 .L84:
818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1412 .loc 1 818 12 view .LVU438
1413 0164 0220 movs r0, #2
1414 .LVL105:
1415 .L67:
820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1416 .loc 1 820 1 view .LVU439
1417 0166 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc}
ARM GAS /tmp/ccEfj1JP.s page 71
1418 .LVL106:
1419 .L85:
724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1420 .loc 1 724 15 view .LVU440
1421 016a 0120 movs r0, #1
1422 .LVL107:
724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1423 .loc 1 724 15 view .LVU441
1424 016c FBE7 b .L67
1425 .LVL108:
1426 .L86:
724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1427 .loc 1 724 15 view .LVU442
1428 016e 0120 movs r0, #1
1429 .LVL109:
724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1430 .loc 1 724 15 view .LVU443
1431 0170 F9E7 b .L67
1432 .LVL110:
1433 .L87:
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1434 .loc 1 727 5 view .LVU444
1435 0172 0220 movs r0, #2
1436 .LVL111:
727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1437 .loc 1 727 5 view .LVU445
1438 0174 F7E7 b .L67
1439 .cfi_endproc
1440 .LFE341:
1442 .section .text.HAL_UARTEx_ReceiveToIdle_IT,"ax",%progbits
1443 .align 1
1444 .global HAL_UARTEx_ReceiveToIdle_IT
1445 .syntax unified
1446 .thumb
1447 .thumb_func
1449 HAL_UARTEx_ReceiveToIdle_IT:
1450 .LVL112:
1451 .LFB342:
837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status;
1452 .loc 1 837 1 is_stmt 1 view -0
1453 .cfi_startproc
1454 @ args = 0, pretend = 0, frame = 0
1455 @ frame_needed = 0, uses_anonymous_args = 0
838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1456 .loc 1 838 3 view .LVU447
841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1457 .loc 1 841 3 view .LVU448
841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1458 .loc 1 841 12 is_stmt 0 view .LVU449
1459 0000 D0F88830 ldr r3, [r0, #136]
841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1460 .loc 1 841 6 view .LVU450
1461 0004 202B cmp r3, #32
1462 0006 20D1 bne .L102
837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status;
1463 .loc 1 837 1 view .LVU451
1464 0008 10B5 push {r4, lr}
ARM GAS /tmp/ccEfj1JP.s page 72
1465 .LCFI17:
1466 .cfi_def_cfa_offset 8
1467 .cfi_offset 4, -8
1468 .cfi_offset 14, -4
1469 000a 0446 mov r4, r0
843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1470 .loc 1 843 5 is_stmt 1 view .LVU452
843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1471 .loc 1 843 8 is_stmt 0 view .LVU453
1472 000c F9B1 cbz r1, .L103
843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1473 .loc 1 843 25 discriminator 1 view .LVU454
1474 000e 02B3 cbz r2, .L104
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1475 .loc 1 848 5 is_stmt 1 view .LVU455
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1476 .loc 1 848 5 view .LVU456
1477 0010 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
1478 0014 012B cmp r3, #1
1479 0016 1ED0 beq .L105
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1480 .loc 1 848 5 discriminator 2 view .LVU457
1481 0018 0123 movs r3, #1
1482 001a 80F88030 strb r3, [r0, #128]
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1483 .loc 1 848 5 discriminator 2 view .LVU458
851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1484 .loc 1 851 5 discriminator 2 view .LVU459
851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1485 .loc 1 851 26 is_stmt 0 discriminator 2 view .LVU460
1486 001e C366 str r3, [r0, #108]
853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1487 .loc 1 853 5 is_stmt 1 discriminator 2 view .LVU461
853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1488 .loc 1 853 15 is_stmt 0 discriminator 2 view .LVU462
1489 0020 FFF7FEFF bl UART_Start_Receive_IT
1490 .LVL113:
856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1491 .loc 1 856 5 is_stmt 1 discriminator 2 view .LVU463
856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1492 .loc 1 856 8 is_stmt 0 discriminator 2 view .LVU464
1493 0024 B0B9 cbnz r0, .L99
858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1494 .loc 1 858 7 is_stmt 1 view .LVU465
858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1495 .loc 1 858 16 is_stmt 0 view .LVU466
1496 0026 E36E ldr r3, [r4, #108]
858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1497 .loc 1 858 10 view .LVU467
1498 0028 012B cmp r3, #1
1499 002a 01D0 beq .L111
869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1500 .loc 1 869 16 view .LVU468
1501 002c 0120 movs r0, #1
1502 .LVL114:
873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1503 .loc 1 873 5 is_stmt 1 view .LVU469
ARM GAS /tmp/ccEfj1JP.s page 73
873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1504 .loc 1 873 12 is_stmt 0 view .LVU470
1505 002e 11E0 b .L99
1506 .LVL115:
1507 .L111:
860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
1508 .loc 1 860 9 is_stmt 1 view .LVU471
1509 0030 2368 ldr r3, [r4]
1510 0032 1022 movs r2, #16
1511 0034 1A62 str r2, [r3, #32]
1512 .L101:
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1513 .loc 1 861 9 discriminator 1 view .LVU472
1514 .LBB32:
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1515 .loc 1 861 9 discriminator 1 view .LVU473
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1516 .loc 1 861 9 discriminator 1 view .LVU474
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1517 .loc 1 861 9 discriminator 1 view .LVU475
1518 0036 2268 ldr r2, [r4]
1519 .LVL116:
1520 .LBB33:
1521 .LBI33:
1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1522 .loc 2 1151 31 discriminator 1 view .LVU476
1523 .LBB34:
1153:Drivers/CMSIS/Include/cmsis_gcc.h ****
1524 .loc 2 1153 5 discriminator 1 view .LVU477
1155:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
1525 .loc 2 1155 4 discriminator 1 view .LVU478
1526 .syntax unified
1527 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1528 0038 52E8003F ldrex r3, [r2]
1529 @ 0 "" 2
1530 .LVL117:
1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1531 .loc 2 1156 4 discriminator 1 view .LVU479
1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1532 .loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU480
1533 .thumb
1534 .syntax unified
1535 .LBE34:
1536 .LBE33:
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1537 .loc 1 861 9 discriminator 1 view .LVU481
1538 003c 43F01003 orr r3, r3, #16
1539 .LVL118:
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1540 .loc 1 861 9 is_stmt 1 discriminator 1 view .LVU482
1541 .LBB35:
1542 .LBI35:
1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1543 .loc 2 1202 31 discriminator 1 view .LVU483
1544 .LBB36:
1204:Drivers/CMSIS/Include/cmsis_gcc.h ****
1545 .loc 2 1204 4 discriminator 1 view .LVU484
ARM GAS /tmp/ccEfj1JP.s page 74
1206:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
1546 .loc 2 1206 4 discriminator 1 view .LVU485
1547 .syntax unified
1548 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1549 0040 42E80031 strex r1, r3, [r2]
1550 @ 0 "" 2
1551 .LVL119:
1552 .loc 2 1207 4 discriminator 1 view .LVU486
1553 .loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU487
1554 .thumb
1555 .syntax unified
1556 .LBE36:
1557 .LBE35:
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1558 .loc 1 861 9 discriminator 1 view .LVU488
1559 0044 0029 cmp r1, #0
1560 0046 F6D1 bne .L101
1561 0048 04E0 b .L99
1562 .LVL120:
1563 .L102:
1564 .LCFI18:
1565 .cfi_def_cfa_offset 0
1566 .cfi_restore 4
1567 .cfi_restore 14
861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1568 .loc 1 861 9 discriminator 1 view .LVU489
1569 .LBE32:
877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1570 .loc 1 877 12 view .LVU490
1571 004a 0220 movs r0, #2
1572 .LVL121:
879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1573 .loc 1 879 1 view .LVU491
1574 004c 7047 bx lr
1575 .LVL122:
1576 .L103:
1577 .LCFI19:
1578 .cfi_def_cfa_offset 8
1579 .cfi_offset 4, -8
1580 .cfi_offset 14, -4
845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1581 .loc 1 845 14 view .LVU492
1582 004e 0120 movs r0, #1
1583 .LVL123:
845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1584 .loc 1 845 14 view .LVU493
1585 0050 00E0 b .L99
1586 .LVL124:
1587 .L104:
845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1588 .loc 1 845 14 view .LVU494
1589 0052 0120 movs r0, #1
1590 .LVL125:
1591 .L99:
879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1592 .loc 1 879 1 view .LVU495
1593 0054 10BD pop {r4, pc}
ARM GAS /tmp/ccEfj1JP.s page 75
1594 .LVL126:
1595 .L105:
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1596 .loc 1 848 5 view .LVU496
1597 0056 0220 movs r0, #2
1598 .LVL127:
848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1599 .loc 1 848 5 view .LVU497
1600 0058 FCE7 b .L99
1601 .cfi_endproc
1602 .LFE342:
1604 .section .text.HAL_UARTEx_ReceiveToIdle_DMA,"ax",%progbits
1605 .align 1
1606 .global HAL_UARTEx_ReceiveToIdle_DMA
1607 .syntax unified
1608 .thumb
1609 .thumb_func
1611 HAL_UARTEx_ReceiveToIdle_DMA:
1612 .LVL128:
1613 .LFB343:
899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status;
1614 .loc 1 899 1 is_stmt 1 view -0
1615 .cfi_startproc
1616 @ args = 0, pretend = 0, frame = 0
1617 @ frame_needed = 0, uses_anonymous_args = 0
900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1618 .loc 1 900 3 view .LVU499
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1619 .loc 1 903 3 view .LVU500
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1620 .loc 1 903 12 is_stmt 0 view .LVU501
1621 0000 D0F88830 ldr r3, [r0, #136]
903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1622 .loc 1 903 6 view .LVU502
1623 0004 202B cmp r3, #32
1624 0006 20D1 bne .L116
899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status;
1625 .loc 1 899 1 view .LVU503
1626 0008 10B5 push {r4, lr}
1627 .LCFI20:
1628 .cfi_def_cfa_offset 8
1629 .cfi_offset 4, -8
1630 .cfi_offset 14, -4
1631 000a 0446 mov r4, r0
905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1632 .loc 1 905 5 is_stmt 1 view .LVU504
905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1633 .loc 1 905 8 is_stmt 0 view .LVU505
1634 000c F9B1 cbz r1, .L117
905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1635 .loc 1 905 25 discriminator 1 view .LVU506
1636 000e 02B3 cbz r2, .L118
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1637 .loc 1 910 5 is_stmt 1 view .LVU507
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1638 .loc 1 910 5 view .LVU508
1639 0010 90F88030 ldrb r3, [r0, #128] @ zero_extendqisi2
ARM GAS /tmp/ccEfj1JP.s page 76
1640 0014 012B cmp r3, #1
1641 0016 1ED0 beq .L119
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1642 .loc 1 910 5 discriminator 2 view .LVU509
1643 0018 0123 movs r3, #1
1644 001a 80F88030 strb r3, [r0, #128]
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1645 .loc 1 910 5 discriminator 2 view .LVU510
913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1646 .loc 1 913 5 discriminator 2 view .LVU511
913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1647 .loc 1 913 26 is_stmt 0 discriminator 2 view .LVU512
1648 001e C366 str r3, [r0, #108]
915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1649 .loc 1 915 5 is_stmt 1 discriminator 2 view .LVU513
915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1650 .loc 1 915 15 is_stmt 0 discriminator 2 view .LVU514
1651 0020 FFF7FEFF bl UART_Start_Receive_DMA
1652 .LVL129:
918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1653 .loc 1 918 5 is_stmt 1 discriminator 2 view .LVU515
918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1654 .loc 1 918 8 is_stmt 0 discriminator 2 view .LVU516
1655 0024 B0B9 cbnz r0, .L113
920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1656 .loc 1 920 7 is_stmt 1 view .LVU517
920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1657 .loc 1 920 16 is_stmt 0 view .LVU518
1658 0026 E36E ldr r3, [r4, #108]
920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** {
1659 .loc 1 920 10 view .LVU519
1660 0028 012B cmp r3, #1
1661 002a 01D0 beq .L125
931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1662 .loc 1 931 16 view .LVU520
1663 002c 0120 movs r0, #1
1664 .LVL130:
935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1665 .loc 1 935 5 is_stmt 1 view .LVU521
935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1666 .loc 1 935 12 is_stmt 0 view .LVU522
1667 002e 11E0 b .L113
1668 .LVL131:
1669 .L125:
922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
1670 .loc 1 922 9 is_stmt 1 view .LVU523
1671 0030 2368 ldr r3, [r4]
1672 0032 1022 movs r2, #16
1673 0034 1A62 str r2, [r3, #32]
1674 .L115:
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1675 .loc 1 923 9 discriminator 1 view .LVU524
1676 .LBB37:
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1677 .loc 1 923 9 discriminator 1 view .LVU525
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1678 .loc 1 923 9 discriminator 1 view .LVU526
ARM GAS /tmp/ccEfj1JP.s page 77
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1679 .loc 1 923 9 discriminator 1 view .LVU527
1680 0036 2268 ldr r2, [r4]
1681 .LVL132:
1682 .LBB38:
1683 .LBI38:
1151:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1684 .loc 2 1151 31 discriminator 1 view .LVU528
1685 .LBB39:
1153:Drivers/CMSIS/Include/cmsis_gcc.h ****
1686 .loc 2 1153 5 discriminator 1 view .LVU529
1155:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
1687 .loc 2 1155 4 discriminator 1 view .LVU530
1688 .syntax unified
1689 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1690 0038 52E8003F ldrex r3, [r2]
1691 @ 0 "" 2
1692 .LVL133:
1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1693 .loc 2 1156 4 discriminator 1 view .LVU531
1156:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1694 .loc 2 1156 4 is_stmt 0 discriminator 1 view .LVU532
1695 .thumb
1696 .syntax unified
1697 .LBE39:
1698 .LBE38:
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1699 .loc 1 923 9 discriminator 1 view .LVU533
1700 003c 43F01003 orr r3, r3, #16
1701 .LVL134:
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1702 .loc 1 923 9 is_stmt 1 discriminator 1 view .LVU534
1703 .LBB40:
1704 .LBI40:
1202:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1705 .loc 2 1202 31 discriminator 1 view .LVU535
1706 .LBB41:
1204:Drivers/CMSIS/Include/cmsis_gcc.h ****
1707 .loc 2 1204 4 discriminator 1 view .LVU536
1206:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
1708 .loc 2 1206 4 discriminator 1 view .LVU537
1709 .syntax unified
1710 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
1711 0040 42E80031 strex r1, r3, [r2]
1712 @ 0 "" 2
1713 .LVL135:
1714 .loc 2 1207 4 discriminator 1 view .LVU538
1715 .loc 2 1207 4 is_stmt 0 discriminator 1 view .LVU539
1716 .thumb
1717 .syntax unified
1718 .LBE41:
1719 .LBE40:
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1720 .loc 1 923 9 discriminator 1 view .LVU540
1721 0044 0029 cmp r1, #0
1722 0046 F6D1 bne .L115
1723 0048 04E0 b .L113
ARM GAS /tmp/ccEfj1JP.s page 78
1724 .LVL136:
1725 .L116:
1726 .LCFI21:
1727 .cfi_def_cfa_offset 0
1728 .cfi_restore 4
1729 .cfi_restore 14
923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1730 .loc 1 923 9 discriminator 1 view .LVU541
1731 .LBE37:
939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1732 .loc 1 939 12 view .LVU542
1733 004a 0220 movs r0, #2
1734 .LVL137:
941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1735 .loc 1 941 1 view .LVU543
1736 004c 7047 bx lr
1737 .LVL138:
1738 .L117:
1739 .LCFI22:
1740 .cfi_def_cfa_offset 8
1741 .cfi_offset 4, -8
1742 .cfi_offset 14, -4
907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1743 .loc 1 907 14 view .LVU544
1744 004e 0120 movs r0, #1
1745 .LVL139:
907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1746 .loc 1 907 14 view .LVU545
1747 0050 00E0 b .L113
1748 .LVL140:
1749 .L118:
907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** }
1750 .loc 1 907 14 view .LVU546
1751 0052 0120 movs r0, #1
1752 .LVL141:
1753 .L113:
941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1754 .loc 1 941 1 view .LVU547
1755 0054 10BD pop {r4, pc}
1756 .LVL142:
1757 .L119:
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1758 .loc 1 910 5 view .LVU548
1759 0056 0220 movs r0, #2
1760 .LVL143:
910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c ****
1761 .loc 1 910 5 view .LVU549
1762 0058 FCE7 b .L113
1763 .cfi_endproc
1764 .LFE343:
1766 .section .rodata.denominator.0,"a"
1767 .align 2
1770 denominator.0:
1771 0000 08040204 .ascii "\010\004\002\004\010\001\001\001"
1771 08010101
1772 .section .rodata.numerator.1,"a"
1773 .align 2
ARM GAS /tmp/ccEfj1JP.s page 79
1776 numerator.1:
1777 0000 01010103 .ascii "\001\001\001\003\007\001\000\000"
1777 07010000
1778 .text
1779 .Letext0:
1780 .file 3 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
1781 .file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
1782 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
1783 .file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
1784 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
1785 .file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
1786 .file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h"
1787 .file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
ARM GAS /tmp/ccEfj1JP.s page 80
DEFINED SYMBOLS
*ABS*:00000000 stm32g4xx_hal_uart_ex.c
/tmp/ccEfj1JP.s:21 .text.UARTEx_Wakeup_AddressConfig:00000000 $t
/tmp/ccEfj1JP.s:26 .text.UARTEx_Wakeup_AddressConfig:00000000 UARTEx_Wakeup_AddressConfig
/tmp/ccEfj1JP.s:65 .text.UARTEx_SetNbDataToProcess:00000000 $t
/tmp/ccEfj1JP.s:70 .text.UARTEx_SetNbDataToProcess:00000000 UARTEx_SetNbDataToProcess
/tmp/ccEfj1JP.s:156 .text.UARTEx_SetNbDataToProcess:00000044 $d
/tmp/ccEfj1JP.s:1776 .rodata.numerator.1:00000000 numerator.1
/tmp/ccEfj1JP.s:1770 .rodata.denominator.0:00000000 denominator.0
/tmp/ccEfj1JP.s:162 .text.HAL_RS485Ex_Init:00000000 $t
/tmp/ccEfj1JP.s:168 .text.HAL_RS485Ex_Init:00000000 HAL_RS485Ex_Init
/tmp/ccEfj1JP.s:306 .text.HAL_UARTEx_WakeupCallback:00000000 $t
/tmp/ccEfj1JP.s:312 .text.HAL_UARTEx_WakeupCallback:00000000 HAL_UARTEx_WakeupCallback
/tmp/ccEfj1JP.s:327 .text.HAL_UARTEx_RxFifoFullCallback:00000000 $t
/tmp/ccEfj1JP.s:333 .text.HAL_UARTEx_RxFifoFullCallback:00000000 HAL_UARTEx_RxFifoFullCallback
/tmp/ccEfj1JP.s:348 .text.HAL_UARTEx_TxFifoEmptyCallback:00000000 $t
/tmp/ccEfj1JP.s:354 .text.HAL_UARTEx_TxFifoEmptyCallback:00000000 HAL_UARTEx_TxFifoEmptyCallback
/tmp/ccEfj1JP.s:369 .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 $t
/tmp/ccEfj1JP.s:375 .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 HAL_MultiProcessorEx_AddressLength_Set
/tmp/ccEfj1JP.s:439 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 $t
/tmp/ccEfj1JP.s:445 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 HAL_UARTEx_StopModeWakeUpSourceConfig
/tmp/ccEfj1JP.s:571 .text.HAL_UARTEx_EnableStopMode:00000000 $t
/tmp/ccEfj1JP.s:577 .text.HAL_UARTEx_EnableStopMode:00000000 HAL_UARTEx_EnableStopMode
/tmp/ccEfj1JP.s:670 .text.HAL_UARTEx_DisableStopMode:00000000 $t
/tmp/ccEfj1JP.s:676 .text.HAL_UARTEx_DisableStopMode:00000000 HAL_UARTEx_DisableStopMode
/tmp/ccEfj1JP.s:768 .text.HAL_UARTEx_EnableFifoMode:00000000 $t
/tmp/ccEfj1JP.s:774 .text.HAL_UARTEx_EnableFifoMode:00000000 HAL_UARTEx_EnableFifoMode
/tmp/ccEfj1JP.s:853 .text.HAL_UARTEx_DisableFifoMode:00000000 $t
/tmp/ccEfj1JP.s:859 .text.HAL_UARTEx_DisableFifoMode:00000000 HAL_UARTEx_DisableFifoMode
/tmp/ccEfj1JP.s:930 .text.HAL_UARTEx_SetTxFifoThreshold:00000000 $t
/tmp/ccEfj1JP.s:936 .text.HAL_UARTEx_SetTxFifoThreshold:00000000 HAL_UARTEx_SetTxFifoThreshold
/tmp/ccEfj1JP.s:1017 .text.HAL_UARTEx_SetRxFifoThreshold:00000000 $t
/tmp/ccEfj1JP.s:1023 .text.HAL_UARTEx_SetRxFifoThreshold:00000000 HAL_UARTEx_SetRxFifoThreshold
/tmp/ccEfj1JP.s:1104 .text.HAL_UARTEx_ReceiveToIdle:00000000 $t
/tmp/ccEfj1JP.s:1110 .text.HAL_UARTEx_ReceiveToIdle:00000000 HAL_UARTEx_ReceiveToIdle
/tmp/ccEfj1JP.s:1443 .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 $t
/tmp/ccEfj1JP.s:1449 .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 HAL_UARTEx_ReceiveToIdle_IT
/tmp/ccEfj1JP.s:1605 .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 $t
/tmp/ccEfj1JP.s:1611 .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 HAL_UARTEx_ReceiveToIdle_DMA
/tmp/ccEfj1JP.s:1767 .rodata.denominator.0:00000000 $d
/tmp/ccEfj1JP.s:1773 .rodata.numerator.1:00000000 $d
UNDEFINED SYMBOLS
UART_SetConfig
UART_CheckIdleState
HAL_UART_MspInit
UART_AdvFeatureConfig
HAL_GetTick
UART_WaitOnFlagUntilTimeout
UART_Start_Receive_IT
UART_Start_Receive_DMA
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