cesco/squeow
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

UI led

Browse Source
This commit is contained in:
nzasch
2025-06-28 00:58:29 +02:00
parent b9232f66b0
commit 28b7af65b6
123 changed files with 105128 additions and 104148 deletions
Download Patch File Download Diff File Expand all files Collapse all files

326
squeow_sw/build/stm32g4xx_hal_cortex.lst
View File

@@ -1,4 +1,4 @@
ARM GAS /tmp/ccDEPnZG.s page 1
ARM GAS /tmp/ccuFAPPx.s page 1
1 .cpu cortex-m4
@@ -58,7 +58,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__)
28:Drivers/CMSIS/Include/core_cm4.h **** #pragma clang system_header /* treat file as system include file */
29:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS /tmp/ccDEPnZG.s page 2
ARM GAS /tmp/ccuFAPPx.s page 2
30:Drivers/CMSIS/Include/core_cm4.h ****
@@ -118,7 +118,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
84:Drivers/CMSIS/Include/core_cm4.h **** #else
85:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
86:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS /tmp/ccDEPnZG.s page 3
ARM GAS /tmp/ccuFAPPx.s page 3
87:Drivers/CMSIS/Include/core_cm4.h ****
@@ -178,7 +178,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
141:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
142:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U
143:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS /tmp/ccDEPnZG.s page 4
ARM GAS /tmp/ccuFAPPx.s page 4
144:Drivers/CMSIS/Include/core_cm4.h **** #else
@@ -238,7 +238,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
198:Drivers/CMSIS/Include/core_cm4.h **** #define __NVIC_PRIO_BITS 3U
199:Drivers/CMSIS/Include/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
200:Drivers/CMSIS/Include/core_cm4.h **** #endif
ARM GAS /tmp/ccDEPnZG.s page 5
ARM GAS /tmp/ccuFAPPx.s page 5
201:Drivers/CMSIS/Include/core_cm4.h ****
@@ -298,7 +298,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
255:Drivers/CMSIS/Include/core_cm4.h ****
256:Drivers/CMSIS/Include/core_cm4.h **** /**
257:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR).
ARM GAS /tmp/ccDEPnZG.s page 6
ARM GAS /tmp/ccuFAPPx.s page 6
258:Drivers/CMSIS/Include/core_cm4.h **** */
@@ -358,7 +358,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
312:Drivers/CMSIS/Include/core_cm4.h ****
313:Drivers/CMSIS/Include/core_cm4.h **** /**
314:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ARM GAS /tmp/ccDEPnZG.s page 7
ARM GAS /tmp/ccuFAPPx.s page 7
315:Drivers/CMSIS/Include/core_cm4.h **** */
@@ -418,7 +418,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
369:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL).
370:Drivers/CMSIS/Include/core_cm4.h **** */
371:Drivers/CMSIS/Include/core_cm4.h **** typedef union
ARM GAS /tmp/ccDEPnZG.s page 8
ARM GAS /tmp/ccuFAPPx.s page 8
372:Drivers/CMSIS/Include/core_cm4.h **** {
@@ -478,7 +478,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
426:Drivers/CMSIS/Include/core_cm4.h ****
427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */
428:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 9
ARM GAS /tmp/ccuFAPPx.s page 9
429:Drivers/CMSIS/Include/core_cm4.h ****
@@ -538,7 +538,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB
484:Drivers/CMSIS/Include/core_cm4.h ****
485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB
ARM GAS /tmp/ccDEPnZG.s page 10
ARM GAS /tmp/ccuFAPPx.s page 10
486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB
@@ -598,7 +598,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB
541:Drivers/CMSIS/Include/core_cm4.h ****
542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB
ARM GAS /tmp/ccDEPnZG.s page 11
ARM GAS /tmp/ccuFAPPx.s page 11
543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB
@@ -658,7 +658,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
597:Drivers/CMSIS/Include/core_cm4.h ****
598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB
599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB
ARM GAS /tmp/ccDEPnZG.s page 12
ARM GAS /tmp/ccuFAPPx.s page 12
600:Drivers/CMSIS/Include/core_cm4.h ****
@@ -718,7 +718,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
654:Drivers/CMSIS/Include/core_cm4.h ****
655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB
656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB
ARM GAS /tmp/ccDEPnZG.s page 13
ARM GAS /tmp/ccuFAPPx.s page 13
657:Drivers/CMSIS/Include/core_cm4.h ****
@@ -778,7 +778,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
711:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
712:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB
713:Drivers/CMSIS/Include/core_cm4.h **** @{
ARM GAS /tmp/ccDEPnZG.s page 14
ARM GAS /tmp/ccuFAPPx.s page 14
714:Drivers/CMSIS/Include/core_cm4.h **** */
@@ -838,7 +838,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT
769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT
770:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 15
ARM GAS /tmp/ccuFAPPx.s page 15
771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT
@@ -898,7 +898,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
825:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[32U];
826:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[43U];
827:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
ARM GAS /tmp/ccDEPnZG.s page 16
ARM GAS /tmp/ccuFAPPx.s page 16
828:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
@@ -958,7 +958,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
882:Drivers/CMSIS/Include/core_cm4.h ****
883:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM
884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM
ARM GAS /tmp/ccDEPnZG.s page 17
ARM GAS /tmp/ccuFAPPx.s page 17
885:Drivers/CMSIS/Include/core_cm4.h ****
@@ -1018,7 +1018,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
939:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR
940:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR
941:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 18
ARM GAS /tmp/ccuFAPPx.s page 18
942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR
@@ -1078,7 +1078,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
996:Drivers/CMSIS/Include/core_cm4.h ****
997:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL
ARM GAS /tmp/ccDEPnZG.s page 19
ARM GAS /tmp/ccuFAPPx.s page 19
999:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL
@@ -1138,7 +1138,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1053:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register *
1054:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[131U];
1055:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis
ARM GAS /tmp/ccDEPnZG.s page 20
ARM GAS /tmp/ccuFAPPx.s page 20
1056:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi
@@ -1198,7 +1198,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1110:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF
1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF
1112:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 21
ARM GAS /tmp/ccuFAPPx.s page 21
1113:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF
@@ -1258,7 +1258,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1167:Drivers/CMSIS/Include/core_cm4.h ****
1168:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */
1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV
ARM GAS /tmp/ccDEPnZG.s page 22
ARM GAS /tmp/ccuFAPPx.s page 22
1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV
@@ -1318,7 +1318,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1224:Drivers/CMSIS/Include/core_cm4.h ****
1225:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */
1226:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU
ARM GAS /tmp/ccDEPnZG.s page 23
ARM GAS /tmp/ccuFAPPx.s page 23
1227:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU
@@ -1378,7 +1378,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU
1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU
1283:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 24
ARM GAS /tmp/ccuFAPPx.s page 24
1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU
@@ -1438,7 +1438,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1338:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC
1339:Drivers/CMSIS/Include/core_cm4.h ****
1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC
ARM GAS /tmp/ccDEPnZG.s page 25
ARM GAS /tmp/ccuFAPPx.s page 25
1341:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC
@@ -1498,7 +1498,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1395:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR
1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR
1397:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 26
ARM GAS /tmp/ccuFAPPx.s page 26
1398:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 2 Definitions */
@@ -1558,7 +1558,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core
1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core
1454:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 27
ARM GAS /tmp/ccuFAPPx.s page 27
1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core
@@ -1618,7 +1618,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1509:Drivers/CMSIS/Include/core_cm4.h ****
1510:Drivers/CMSIS/Include/core_cm4.h ****
1511:Drivers/CMSIS/Include/core_cm4.h **** /**
ARM GAS /tmp/ccDEPnZG.s page 28
ARM GAS /tmp/ccuFAPPx.s page 28
1512:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register
@@ -1678,7 +1678,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1566:Drivers/CMSIS/Include/core_cm4.h **** #endif
1567:Drivers/CMSIS/Include/core_cm4.h ****
1568:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
ARM GAS /tmp/ccDEPnZG.s page 29
ARM GAS /tmp/ccuFAPPx.s page 29
1569:Drivers/CMSIS/Include/core_cm4.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
@@ -1738,7 +1738,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1623:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetVector __NVIC_SetVector
1624:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetVector __NVIC_GetVector
1625:Drivers/CMSIS/Include/core_cm4.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */
ARM GAS /tmp/ccDEPnZG.s page 30
ARM GAS /tmp/ccuFAPPx.s page 30
1626:Drivers/CMSIS/Include/core_cm4.h ****
@@ -1798,7 +1798,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1680:Drivers/CMSIS/Include/core_cm4.h **** {
30 .loc 2 1680 1 view -0
31 .cfi_startproc
ARM GAS /tmp/ccDEPnZG.s page 31
ARM GAS /tmp/ccuFAPPx.s page 31
32 @ args = 0, pretend = 0, frame = 0
@@ -1858,7 +1858,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1696:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative.
1697:Drivers/CMSIS/Include/core_cm4.h **** */
1698:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
ARM GAS /tmp/ccDEPnZG.s page 32
ARM GAS /tmp/ccuFAPPx.s page 32
1699:Drivers/CMSIS/Include/core_cm4.h **** {
@@ -1918,7 +1918,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
ARM GAS /tmp/ccDEPnZG.s page 33
ARM GAS /tmp/ccuFAPPx.s page 33
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
@@ -1978,7 +1978,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/ccDEPnZG.s page 34
ARM GAS /tmp/ccuFAPPx.s page 34
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
@@ -2038,7 +2038,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
119:Drivers/CMSIS/Include/cmsis_gcc.h ****
120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */
ARM GAS /tmp/ccDEPnZG.s page 35
ARM GAS /tmp/ccuFAPPx.s page 35
121:Drivers/CMSIS/Include/cmsis_gcc.h ****
@@ -2098,7 +2098,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
ARM GAS /tmp/ccDEPnZG.s page 36
ARM GAS /tmp/ccuFAPPx.s page 36
178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors
@@ -2158,7 +2158,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/ccDEPnZG.s page 37
ARM GAS /tmp/ccuFAPPx.s page 37
235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
@@ -2218,7 +2218,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
289:Drivers/CMSIS/Include/cmsis_gcc.h ****
290:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
291:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
ARM GAS /tmp/ccDEPnZG.s page 38
ARM GAS /tmp/ccuFAPPx.s page 38
292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@@ -2278,7 +2278,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
346:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccDEPnZG.s page 39
ARM GAS /tmp/ccuFAPPx.s page 39
349:Drivers/CMSIS/Include/cmsis_gcc.h ****
@@ -2338,7 +2338,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
403:Drivers/CMSIS/Include/cmsis_gcc.h ****
404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS /tmp/ccDEPnZG.s page 40
ARM GAS /tmp/ccuFAPPx.s page 40
406:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure)
@@ -2398,7 +2398,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
460:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure)
461:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
462:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
ARM GAS /tmp/ccDEPnZG.s page 41
ARM GAS /tmp/ccuFAPPx.s page 41
463:Drivers/CMSIS/Include/cmsis_gcc.h **** */
@@ -2458,7 +2458,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
519:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
ARM GAS /tmp/ccDEPnZG.s page 42
ARM GAS /tmp/ccuFAPPx.s page 42
520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@@ -2518,7 +2518,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
575:Drivers/CMSIS/Include/cmsis_gcc.h ****
576:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccDEPnZG.s page 43
ARM GAS /tmp/ccuFAPPx.s page 43
577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@@ -2578,7 +2578,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
632:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure)
633:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state.
ARM GAS /tmp/ccDEPnZG.s page 44
ARM GAS /tmp/ccuFAPPx.s page 44
634:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
@@ -2638,7 +2638,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
688:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
689:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/ccDEPnZG.s page 45
ARM GAS /tmp/ccuFAPPx.s page 45
691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
@@ -2698,7 +2698,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/ccDEPnZG.s page 46
ARM GAS /tmp/ccuFAPPx.s page 46
748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
@@ -2758,7 +2758,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
802:Drivers/CMSIS/Include/cmsis_gcc.h ****
803:Drivers/CMSIS/Include/cmsis_gcc.h ****
804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ARM GAS /tmp/ccDEPnZG.s page 47
ARM GAS /tmp/ccuFAPPx.s page 47
805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@@ -2818,7 +2818,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
ARM GAS /tmp/ccDEPnZG.s page 48
ARM GAS /tmp/ccuFAPPx.s page 48
862:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
@@ -2878,7 +2878,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
916:Drivers/CMSIS/Include/cmsis_gcc.h **** */
917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe")
918:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccDEPnZG.s page 49
ARM GAS /tmp/ccuFAPPx.s page 49
919:Drivers/CMSIS/Include/cmsis_gcc.h ****
@@ -2938,7 +2938,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
123 .L5:
124 .LBE39:
125 .LBE38:
ARM GAS /tmp/ccDEPnZG.s page 50
ARM GAS /tmp/ccuFAPPx.s page 50
1724:Drivers/CMSIS/Include/core_cm4.h **** }
@@ -2998,7 +2998,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1762:Drivers/CMSIS/Include/core_cm4.h ****
1763:Drivers/CMSIS/Include/core_cm4.h ****
1764:Drivers/CMSIS/Include/core_cm4.h **** /**
ARM GAS /tmp/ccDEPnZG.s page 51
ARM GAS /tmp/ccuFAPPx.s page 51
1765:Drivers/CMSIS/Include/core_cm4.h **** \brief Clear Pending Interrupt
@@ -3058,7 +3058,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
151 0000 0028 cmp r0, #0
152 .loc 2 1811 6 view .LVU31
153 0002 08DB blt .L10
ARM GAS /tmp/ccDEPnZG.s page 52
ARM GAS /tmp/ccuFAPPx.s page 52
1812:Drivers/CMSIS/Include/core_cm4.h **** {
@@ -3118,7 +3118,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1821:Drivers/CMSIS/Include/core_cm4.h ****
1822:Drivers/CMSIS/Include/core_cm4.h **** /**
1823:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Priority
ARM GAS /tmp/ccDEPnZG.s page 53
ARM GAS /tmp/ccuFAPPx.s page 53
1824:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority of a device specific interrupt or a processor exception.
@@ -3178,7 +3178,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
236 .align 2
237 .L17:
238 0020 14ED00E0 .word -536810220
ARM GAS /tmp/ccDEPnZG.s page 54
ARM GAS /tmp/ccuFAPPx.s page 54
239 .cfi_endproc
@@ -3238,7 +3238,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
274 .loc 2 1863 3 is_stmt 1 view .LVU67
275 .loc 2 1863 44 is_stmt 0 view .LVU68
276 0014 031D adds r3, r0, #4
ARM GAS /tmp/ccDEPnZG.s page 55
ARM GAS /tmp/ccuFAPPx.s page 55
277 .loc 2 1863 109 view .LVU69
@@ -3298,7 +3298,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1878:Drivers/CMSIS/Include/core_cm4.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC
1879:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group.
1880:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0).
ARM GAS /tmp/ccDEPnZG.s page 56
ARM GAS /tmp/ccuFAPPx.s page 56
1881:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pSubPriority Subpriority value (starting from 0).
@@ -3358,7 +3358,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
360 .loc 2 1892 53 view .LVU94
361 0028 24EA0C04 bic r4, r4, ip
362 .loc 2 1892 21 view .LVU95
ARM GAS /tmp/ccDEPnZG.s page 57
ARM GAS /tmp/ccuFAPPx.s page 57
363 002c 1460 str r4, [r2]
@@ -3418,7 +3418,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1919:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number.
1920:Drivers/CMSIS/Include/core_cm4.h **** \return Address of interrupt handler function
1921:Drivers/CMSIS/Include/core_cm4.h **** */
ARM GAS /tmp/ccDEPnZG.s page 58
ARM GAS /tmp/ccuFAPPx.s page 58
1922:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
@@ -3478,7 +3478,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
423 .LBB42:
424 .LBI42:
944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/ccDEPnZG.s page 59
ARM GAS /tmp/ccuFAPPx.s page 59
425 .loc 3 944 27 view .LVU112
@@ -3538,7 +3538,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @attention
13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** *
14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * Copyright (c) 2019 STMicroelectronics.
ARM GAS /tmp/ccDEPnZG.s page 60
ARM GAS /tmp/ccuFAPPx.s page 60
15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * All rights reserved.
@@ -3598,7 +3598,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula:
71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
ARM GAS /tmp/ccDEPnZG.s page 61
ARM GAS /tmp/ccuFAPPx.s page 61
72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
@@ -3658,7 +3658,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group1
ARM GAS /tmp/ccDEPnZG.s page 62
ARM GAS /tmp/ccuFAPPx.s page 62
129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Initialization and Configuration functions
@@ -3718,7 +3718,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
476 .loc 2 1650 3 view .LVU121
1651:Drivers/CMSIS/Include/core_cm4.h ****
477 .loc 2 1651 3 view .LVU122
ARM GAS /tmp/ccDEPnZG.s page 63
ARM GAS /tmp/ccuFAPPx.s page 63
1653:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
@@ -3778,7 +3778,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
518 .LFE329:
520 .section .text.HAL_NVIC_SetPriority,"ax",%progbits
521 .align 1
ARM GAS /tmp/ccDEPnZG.s page 64
ARM GAS /tmp/ccuFAPPx.s page 64
522 .global HAL_NVIC_SetPriority
@@ -3838,7 +3838,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
551 0004 054B ldr r3, .L36
552 0006 D868 ldr r0, [r3, #12]
553 .LVL41:
ARM GAS /tmp/ccDEPnZG.s page 65
ARM GAS /tmp/ccuFAPPx.s page 65
1669:Drivers/CMSIS/Include/core_cm4.h **** }
@@ -3898,7 +3898,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
594 .loc 1 208 1 is_stmt 0 view .LVU154
595 0000 08B5 push {r3, lr}
596 .LCFI3:
ARM GAS /tmp/ccDEPnZG.s page 66
ARM GAS /tmp/ccuFAPPx.s page 66
597 .cfi_def_cfa_offset 8
@@ -3958,7 +3958,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
632 .LVL49:
230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
633 .loc 1 230 1 is_stmt 0 view .LVU162
ARM GAS /tmp/ccDEPnZG.s page 67
ARM GAS /tmp/ccuFAPPx.s page 67
634 0006 08BD pop {r3, pc}
@@ -4018,7 +4018,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** {
673 .loc 1 250 1 view -0
674 .cfi_startproc
ARM GAS /tmp/ccDEPnZG.s page 68
ARM GAS /tmp/ccuFAPPx.s page 68
675 @ args = 0, pretend = 0, frame = 0
@@ -4078,7 +4078,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1992:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */
1993:Drivers/CMSIS/Include/core_cm4.h ****
1994:Drivers/CMSIS/Include/core_cm4.h ****
ARM GAS /tmp/ccDEPnZG.s page 69
ARM GAS /tmp/ccuFAPPx.s page 69
1995:Drivers/CMSIS/Include/core_cm4.h ****
@@ -4138,7 +4138,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
701 .loc 2 1817 5 view .LVU176
1817:Drivers/CMSIS/Include/core_cm4.h **** }
702 .loc 2 1817 46 is_stmt 0 view .LVU177
ARM GAS /tmp/ccDEPnZG.s page 70
ARM GAS /tmp/ccuFAPPx.s page 70
703 000e 054A ldr r2, .L47
@@ -4198,7 +4198,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */
256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group2
ARM GAS /tmp/ccDEPnZG.s page 71
ARM GAS /tmp/ccuFAPPx.s page 71
258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Cortex control functions
@@ -4258,7 +4258,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
776 .global HAL_NVIC_GetPriority
777 .syntax unified
778 .thumb
ARM GAS /tmp/ccDEPnZG.s page 72
ARM GAS /tmp/ccuFAPPx.s page 72
779 .thumb_func
@@ -4318,7 +4318,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
806 0010 2146 mov r1, r4
807 0012 FFF7FEFF bl NVIC_DecodePriority
808 .LVL59:
ARM GAS /tmp/ccDEPnZG.s page 73
ARM GAS /tmp/ccuFAPPx.s page 73
310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** }
@@ -4378,7 +4378,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
843 0004 00F01F02 and r2, r0, #31
1759:Drivers/CMSIS/Include/core_cm4.h **** }
844 .loc 2 1759 34 view .LVU211
ARM GAS /tmp/ccDEPnZG.s page 74
ARM GAS /tmp/ccuFAPPx.s page 74
845 0008 4009 lsrs r0, r0, #5
@@ -4438,7 +4438,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
883 .loc 1 340 3 view .LVU217
341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Return 1 if pending else 0 */
ARM GAS /tmp/ccDEPnZG.s page 75
ARM GAS /tmp/ccuFAPPx.s page 75
343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn);
@@ -4498,7 +4498,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
925 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
926 .align 1
927 .global HAL_NVIC_ClearPendingIRQ
ARM GAS /tmp/ccDEPnZG.s page 76
ARM GAS /tmp/ccuFAPPx.s page 76
928 .syntax unified
@@ -4558,7 +4558,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1774:Drivers/CMSIS/Include/core_cm4.h **** }
960 .loc 2 1774 43 view .LVU243
961 000e 6030 adds r0, r0, #96
ARM GAS /tmp/ccDEPnZG.s page 77
ARM GAS /tmp/ccuFAPPx.s page 77
962 0010 014A ldr r2, .L65
@@ -4618,7 +4618,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1000 0000 0028 cmp r0, #0
1789:Drivers/CMSIS/Include/core_cm4.h **** {
1001 .loc 2 1789 6 view .LVU251
ARM GAS /tmp/ccDEPnZG.s page 78
ARM GAS /tmp/ccuFAPPx.s page 78
1002 0002 0BDB blt .L69
@@ -4678,7 +4678,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock
381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None
ARM GAS /tmp/ccDEPnZG.s page 79
ARM GAS /tmp/ccuFAPPx.s page 79
383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */
@@ -4738,7 +4738,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1083 .LFB343:
397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /**
ARM GAS /tmp/ccDEPnZG.s page 80
ARM GAS /tmp/ccuFAPPx.s page 80
399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Handle SYSTICK interrupt request.
@@ -4798,7 +4798,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1120 .section .text.HAL_MPU_Enable,"ax",%progbits
1121 .align 1
1122 .global HAL_MPU_Enable
ARM GAS /tmp/ccDEPnZG.s page 81
ARM GAS /tmp/ccuFAPPx.s page 81
1123 .syntax unified
@@ -4858,7 +4858,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1156 .loc 1 437 3 view .LVU284
1157 .LBB64:
1158 .LBI64:
ARM GAS /tmp/ccDEPnZG.s page 82
ARM GAS /tmp/ccuFAPPx.s page 82
933:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@@ -4918,7 +4918,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
953:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
954:Drivers/CMSIS/Include/cmsis_gcc.h **** */
955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
ARM GAS /tmp/ccDEPnZG.s page 83
ARM GAS /tmp/ccuFAPPx.s page 83
1196 .loc 3 955 27 view .LVU290
@@ -4978,7 +4978,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ****
463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Set the Region number */
464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RNR = RegionNumber;
ARM GAS /tmp/ccDEPnZG.s page 84
ARM GAS /tmp/ccuFAPPx.s page 84
1237 .loc 1 464 3 view .LVU297
@@ -5038,7 +5038,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1274 .loc 1 483 3 is_stmt 1 view .LVU305
1275 0006 D3F8A020 ldr r2, [r3, #160]
1276 000a 22F00102 bic r2, r2, #1
ARM GAS /tmp/ccDEPnZG.s page 85
ARM GAS /tmp/ccuFAPPx.s page 85
1277 000e C3F8A020 str r2, [r3, #160]
@@ -5098,7 +5098,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Set the Region number */
506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number;
1312 .loc 1 506 3 view .LVU318
ARM GAS /tmp/ccDEPnZG.s page 86
ARM GAS /tmp/ccuFAPPx.s page 86
1313 .loc 1 506 22 is_stmt 0 view .LVU319
@@ -5158,7 +5158,7 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1350 .loc 1 517 82 view .LVU337
1351 0038 43EA0143 orr r3, r3, r1, lsl #16
519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
ARM GAS /tmp/ccDEPnZG.s page 87
ARM GAS /tmp/ccuFAPPx.s page 87
1352 .loc 1 519 34 view .LVU338
@@ -5193,88 +5193,88 @@ ARM GAS /tmp/ccDEPnZG.s page 1
1375 .text
1376 .Letext0:
1377 .file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
1378 .file 5 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach
1379 .file 6 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/
1378 .file 5 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach
1379 .file 6 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/
1380 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
ARM GAS /tmp/ccDEPnZG.s page 88
ARM GAS /tmp/ccuFAPPx.s page 88
DEFINED SYMBOLS
*ABS*:00000000 stm32g4xx_hal_cortex.c
/tmp/ccDEPnZG.s:21 .text.__NVIC_EnableIRQ:00000000 $t
/tmp/ccDEPnZG.s:26 .text.__NVIC_EnableIRQ:00000000 __NVIC_EnableIRQ
/tmp/ccDEPnZG.s:60 .text.__NVIC_EnableIRQ:00000018 $d
/tmp/ccDEPnZG.s:65 .text.__NVIC_DisableIRQ:00000000 $t
/tmp/ccDEPnZG.s:70 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
/tmp/ccDEPnZG.s:131 .text.__NVIC_DisableIRQ:00000020 $d
/tmp/ccDEPnZG.s:136 .text.__NVIC_SetPriority:00000000 $t
/tmp/ccDEPnZG.s:141 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
/tmp/ccDEPnZG.s:188 .text.__NVIC_SetPriority:00000024 $d
/tmp/ccDEPnZG.s:193 .text.__NVIC_GetPriority:00000000 $t
/tmp/ccDEPnZG.s:198 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
/tmp/ccDEPnZG.s:238 .text.__NVIC_GetPriority:00000020 $d
/tmp/ccDEPnZG.s:243 .text.NVIC_EncodePriority:00000000 $t
/tmp/ccDEPnZG.s:248 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
/tmp/ccDEPnZG.s:310 .text.NVIC_DecodePriority:00000000 $t
/tmp/ccDEPnZG.s:315 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
/tmp/ccDEPnZG.s:384 .text.__NVIC_SystemReset:00000000 $t
/tmp/ccDEPnZG.s:389 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
/tmp/ccDEPnZG.s:450 .text.__NVIC_SystemReset:0000001c $d
/tmp/ccDEPnZG.s:456 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
/tmp/ccDEPnZG.s:462 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
/tmp/ccDEPnZG.s:516 .text.HAL_NVIC_SetPriorityGrouping:00000020 $d
/tmp/ccDEPnZG.s:521 .text.HAL_NVIC_SetPriority:00000000 $t
/tmp/ccDEPnZG.s:527 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
/tmp/ccDEPnZG.s:576 .text.HAL_NVIC_SetPriority:0000001c $d
/tmp/ccDEPnZG.s:581 .text.HAL_NVIC_EnableIRQ:00000000 $t
/tmp/ccDEPnZG.s:587 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
/tmp/ccDEPnZG.s:610 .text.HAL_NVIC_DisableIRQ:00000000 $t
/tmp/ccDEPnZG.s:616 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
/tmp/ccDEPnZG.s:639 .text.HAL_NVIC_SystemReset:00000000 $t
/tmp/ccDEPnZG.s:645 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
/tmp/ccDEPnZG.s:664 .text.HAL_SYSTICK_Config:00000000 $t
/tmp/ccDEPnZG.s:670 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
/tmp/ccDEPnZG.s:735 .text.HAL_SYSTICK_Config:00000024 $d
/tmp/ccDEPnZG.s:740 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
/tmp/ccDEPnZG.s:746 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
/tmp/ccDEPnZG.s:770 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
/tmp/ccDEPnZG.s:775 .text.HAL_NVIC_GetPriority:00000000 $t
/tmp/ccDEPnZG.s:781 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
/tmp/ccDEPnZG.s:816 .text.HAL_NVIC_SetPendingIRQ:00000000 $t
/tmp/ccDEPnZG.s:822 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
/tmp/ccDEPnZG.s:864 .text.HAL_NVIC_SetPendingIRQ:00000018 $d
/tmp/ccDEPnZG.s:869 .text.HAL_NVIC_GetPendingIRQ:00000000 $t
/tmp/ccDEPnZG.s:875 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
/tmp/ccDEPnZG.s:921 .text.HAL_NVIC_GetPendingIRQ:00000020 $d
/tmp/ccDEPnZG.s:926 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
/tmp/ccDEPnZG.s:932 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
/tmp/ccDEPnZG.s:974 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
/tmp/ccDEPnZG.s:979 .text.HAL_NVIC_GetActive:00000000 $t
/tmp/ccDEPnZG.s:985 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
/tmp/ccDEPnZG.s:1030 .text.HAL_NVIC_GetActive:00000020 $d
/tmp/ccDEPnZG.s:1035 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
/tmp/ccDEPnZG.s:1041 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
/tmp/ccDEPnZG.s:1076 .text.HAL_SYSTICK_Callback:00000000 $t
/tmp/ccDEPnZG.s:1082 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
ARM GAS /tmp/ccDEPnZG.s page 89
/tmp/ccuFAPPx.s:21 .text.__NVIC_EnableIRQ:00000000 $t
/tmp/ccuFAPPx.s:26 .text.__NVIC_EnableIRQ:00000000 __NVIC_EnableIRQ
/tmp/ccuFAPPx.s:60 .text.__NVIC_EnableIRQ:00000018 $d
/tmp/ccuFAPPx.s:65 .text.__NVIC_DisableIRQ:00000000 $t
/tmp/ccuFAPPx.s:70 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
/tmp/ccuFAPPx.s:131 .text.__NVIC_DisableIRQ:00000020 $d
/tmp/ccuFAPPx.s:136 .text.__NVIC_SetPriority:00000000 $t
/tmp/ccuFAPPx.s:141 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
/tmp/ccuFAPPx.s:188 .text.__NVIC_SetPriority:00000024 $d
/tmp/ccuFAPPx.s:193 .text.__NVIC_GetPriority:00000000 $t
/tmp/ccuFAPPx.s:198 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
/tmp/ccuFAPPx.s:238 .text.__NVIC_GetPriority:00000020 $d
/tmp/ccuFAPPx.s:243 .text.NVIC_EncodePriority:00000000 $t
/tmp/ccuFAPPx.s:248 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
/tmp/ccuFAPPx.s:310 .text.NVIC_DecodePriority:00000000 $t
/tmp/ccuFAPPx.s:315 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
/tmp/ccuFAPPx.s:384 .text.__NVIC_SystemReset:00000000 $t
/tmp/ccuFAPPx.s:389 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
/tmp/ccuFAPPx.s:450 .text.__NVIC_SystemReset:0000001c $d
/tmp/ccuFAPPx.s:456 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
/tmp/ccuFAPPx.s:462 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
/tmp/ccuFAPPx.s:516 .text.HAL_NVIC_SetPriorityGrouping:00000020 $d
/tmp/ccuFAPPx.s:521 .text.HAL_NVIC_SetPriority:00000000 $t
/tmp/ccuFAPPx.s:527 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
/tmp/ccuFAPPx.s:576 .text.HAL_NVIC_SetPriority:0000001c $d
/tmp/ccuFAPPx.s:581 .text.HAL_NVIC_EnableIRQ:00000000 $t
/tmp/ccuFAPPx.s:587 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
/tmp/ccuFAPPx.s:610 .text.HAL_NVIC_DisableIRQ:00000000 $t
/tmp/ccuFAPPx.s:616 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
/tmp/ccuFAPPx.s:639 .text.HAL_NVIC_SystemReset:00000000 $t
/tmp/ccuFAPPx.s:645 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
/tmp/ccuFAPPx.s:664 .text.HAL_SYSTICK_Config:00000000 $t
/tmp/ccuFAPPx.s:670 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
/tmp/ccuFAPPx.s:735 .text.HAL_SYSTICK_Config:00000024 $d
/tmp/ccuFAPPx.s:740 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
/tmp/ccuFAPPx.s:746 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
/tmp/ccuFAPPx.s:770 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
/tmp/ccuFAPPx.s:775 .text.HAL_NVIC_GetPriority:00000000 $t
/tmp/ccuFAPPx.s:781 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
/tmp/ccuFAPPx.s:816 .text.HAL_NVIC_SetPendingIRQ:00000000 $t
/tmp/ccuFAPPx.s:822 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
/tmp/ccuFAPPx.s:864 .text.HAL_NVIC_SetPendingIRQ:00000018 $d
/tmp/ccuFAPPx.s:869 .text.HAL_NVIC_GetPendingIRQ:00000000 $t
/tmp/ccuFAPPx.s:875 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
/tmp/ccuFAPPx.s:921 .text.HAL_NVIC_GetPendingIRQ:00000020 $d
/tmp/ccuFAPPx.s:926 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
/tmp/ccuFAPPx.s:932 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
/tmp/ccuFAPPx.s:974 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
/tmp/ccuFAPPx.s:979 .text.HAL_NVIC_GetActive:00000000 $t
/tmp/ccuFAPPx.s:985 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
/tmp/ccuFAPPx.s:1030 .text.HAL_NVIC_GetActive:00000020 $d
/tmp/ccuFAPPx.s:1035 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
/tmp/ccuFAPPx.s:1041 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
/tmp/ccuFAPPx.s:1076 .text.HAL_SYSTICK_Callback:00000000 $t
/tmp/ccuFAPPx.s:1082 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
ARM GAS /tmp/ccuFAPPx.s page 89
/tmp/ccDEPnZG.s:1095 .text.HAL_SYSTICK_IRQHandler:00000000 $t
/tmp/ccDEPnZG.s:1101 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
/tmp/ccDEPnZG.s:1121 .text.HAL_MPU_Enable:00000000 $t
/tmp/ccDEPnZG.s:1127 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
/tmp/ccDEPnZG.s:1175 .text.HAL_MPU_Enable:00000014 $d
/tmp/ccDEPnZG.s:1180 .text.HAL_MPU_Disable:00000000 $t
/tmp/ccDEPnZG.s:1186 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
/tmp/ccDEPnZG.s:1217 .text.HAL_MPU_Disable:00000010 $d
/tmp/ccDEPnZG.s:1222 .text.HAL_MPU_EnableRegion:00000000 $t
/tmp/ccDEPnZG.s:1228 .text.HAL_MPU_EnableRegion:00000000 HAL_MPU_EnableRegion
/tmp/ccDEPnZG.s:1250 .text.HAL_MPU_EnableRegion:00000014 $d
/tmp/ccDEPnZG.s:1255 .text.HAL_MPU_DisableRegion:00000000 $t
/tmp/ccDEPnZG.s:1261 .text.HAL_MPU_DisableRegion:00000000 HAL_MPU_DisableRegion
/tmp/ccDEPnZG.s:1283 .text.HAL_MPU_DisableRegion:00000014 $d
/tmp/ccDEPnZG.s:1288 .text.HAL_MPU_ConfigRegion:00000000 $t
/tmp/ccDEPnZG.s:1294 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
/tmp/ccDEPnZG.s:1371 .text.HAL_MPU_ConfigRegion:00000054 $d
/tmp/ccuFAPPx.s:1095 .text.HAL_SYSTICK_IRQHandler:00000000 $t
/tmp/ccuFAPPx.s:1101 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
/tmp/ccuFAPPx.s:1121 .text.HAL_MPU_Enable:00000000 $t
/tmp/ccuFAPPx.s:1127 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
/tmp/ccuFAPPx.s:1175 .text.HAL_MPU_Enable:00000014 $d
/tmp/ccuFAPPx.s:1180 .text.HAL_MPU_Disable:00000000 $t
/tmp/ccuFAPPx.s:1186 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
/tmp/ccuFAPPx.s:1217 .text.HAL_MPU_Disable:00000010 $d
/tmp/ccuFAPPx.s:1222 .text.HAL_MPU_EnableRegion:00000000 $t
/tmp/ccuFAPPx.s:1228 .text.HAL_MPU_EnableRegion:00000000 HAL_MPU_EnableRegion
/tmp/ccuFAPPx.s:1250 .text.HAL_MPU_EnableRegion:00000014 $d
/tmp/ccuFAPPx.s:1255 .text.HAL_MPU_DisableRegion:00000000 $t
/tmp/ccuFAPPx.s:1261 .text.HAL_MPU_DisableRegion:00000000 HAL_MPU_DisableRegion
/tmp/ccuFAPPx.s:1283 .text.HAL_MPU_DisableRegion:00000014 $d
/tmp/ccuFAPPx.s:1288 .text.HAL_MPU_ConfigRegion:00000000 $t
/tmp/ccuFAPPx.s:1294 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
/tmp/ccuFAPPx.s:1371 .text.HAL_MPU_ConfigRegion:00000054 $d
NO UNDEFINED SYMBOLS