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v1.2

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This commit is contained in:
nzasch
2025-01-28 19:01:22 +01:00
parent bfd044a2cb
commit b9232f66b0
1160 changed files with 693991 additions and 336287 deletions
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350
squeow_sw/build/system_stm32g4xx.lst
View File

@@ -1,4 +1,4 @@
ARM GAS /tmp/cc1Ld1Ft.s page 1
ARM GAS /tmp/ccV7jtdT.s page 1
1 .cpu cortex-m4
@@ -58,7 +58,7 @@ ARM GAS /tmp/cc1Ld1Ft.s page 1
28:Src/system_stm32g4xx.c **** * System Clock source | HSI
29:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
30:Src/system_stm32g4xx.c **** * SYSCLK(Hz) | 16000000
ARM GAS /tmp/cc1Ld1Ft.s page 2
ARM GAS /tmp/ccV7jtdT.s page 2
31:Src/system_stm32g4xx.c **** *-----------------------------------------------------------------------------
@@ -118,7 +118,7 @@ ARM GAS /tmp/cc1Ld1Ft.s page 1
85:Src/system_stm32g4xx.c **** #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
86:Src/system_stm32g4xx.c **** #endif /* HSI_VALUE */
87:Src/system_stm32g4xx.c ****
ARM GAS /tmp/cc1Ld1Ft.s page 3
ARM GAS /tmp/ccV7jtdT.s page 3
88:Src/system_stm32g4xx.c **** /**
@@ -178,7 +178,7 @@ ARM GAS /tmp/cc1Ld1Ft.s page 1
142:Src/system_stm32g4xx.c **** * @{
143:Src/system_stm32g4xx.c **** */
144:Src/system_stm32g4xx.c **** /* The SystemCoreClock variable is updated in three ways:
ARM GAS /tmp/cc1Ld1Ft.s page 4
ARM GAS /tmp/ccV7jtdT.s page 4
145:Src/system_stm32g4xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
@@ -238,7 +238,7 @@ ARM GAS /tmp/cc1Ld1Ft.s page 1
187:Src/system_stm32g4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
188:Src/system_stm32g4xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
189:Src/system_stm32g4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
ARM GAS /tmp/cc1Ld1Ft.s page 5
ARM GAS /tmp/ccV7jtdT.s page 5
190:Src/system_stm32g4xx.c **** }
@@ -298,7 +298,7 @@ ARM GAS /tmp/cc1Ld1Ft.s page 1
228:Src/system_stm32g4xx.c **** void SystemCoreClockUpdate(void)
229:Src/system_stm32g4xx.c **** {
59 .loc 1 229 1 is_stmt 1 view -0
ARM GAS /tmp/cc1Ld1Ft.s page 6
ARM GAS /tmp/ccV7jtdT.s page 6
60 .cfi_startproc
@@ -312,22 +312,28 @@ ARM GAS /tmp/cc1Ld1Ft.s page 1
233:Src/system_stm32g4xx.c **** switch (RCC->CFGR & RCC_CFGR_SWS)
65 .loc 1 233 3 view .LVU7
66 .loc 1 233 14 is_stmt 0 view .LVU8
67 0000 1E4B ldr r3, .L12
67 0000 1E4B ldr r3, .L11
68 0002 9B68 ldr r3, [r3, #8]
69 .loc 1 233 21 view .LVU9
70 0004 03F00C03 and r3, r3, #12
71 .loc 1 233 3 view .LVU10
72 0008 082B cmp r3, #8
73 000a 12D0 beq .L5
73 000a 11D0 beq .L5
74 000c 0C2B cmp r3, #12
75 000e 14D0 beq .L6
75 000e 13D0 beq .L6
76 0010 042B cmp r3, #4
77 0012 0AD0 beq .L10
78 .L7:
77 0012 02D1 bne .L7
234:Src/system_stm32g4xx.c **** {
235:Src/system_stm32g4xx.c **** case 0x04: /* HSI used as system clock source */
236:Src/system_stm32g4xx.c **** SystemCoreClock = HSI_VALUE;
78 .loc 1 236 7 is_stmt 1 view .LVU11
79 .loc 1 236 23 is_stmt 0 view .LVU12
80 0014 1A4B ldr r3, .L11+4
81 0016 1B4A ldr r2, .L11+8
82 0018 1A60 str r2, [r3]
237:Src/system_stm32g4xx.c **** break;
83 .loc 1 237 7 is_stmt 1 view .LVU13
84 .L7:
238:Src/system_stm32g4xx.c ****
239:Src/system_stm32g4xx.c **** case 0x08: /* HSE used as system clock source */
240:Src/system_stm32g4xx.c **** SystemCoreClock = HSE_VALUE;
@@ -352,219 +358,209 @@ ARM GAS /tmp/cc1Ld1Ft.s page 1
259:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
260:Src/system_stm32g4xx.c **** break;
261:Src/system_stm32g4xx.c ****
ARM GAS /tmp/ccV7jtdT.s page 7
262:Src/system_stm32g4xx.c **** default:
263:Src/system_stm32g4xx.c **** break;
264:Src/system_stm32g4xx.c **** }
265:Src/system_stm32g4xx.c **** /* Compute HCLK clock frequency --------------------------------------------*/
266:Src/system_stm32g4xx.c **** /* Get HCLK prescaler */
267:Src/system_stm32g4xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
ARM GAS /tmp/cc1Ld1Ft.s page 7
79 .loc 1 267 3 is_stmt 1 view .LVU11
80 .loc 1 267 28 is_stmt 0 view .LVU12
81 0014 194B ldr r3, .L12
82 0016 9B68 ldr r3, [r3, #8]
83 .loc 1 267 52 view .LVU13
84 0018 C3F30313 ubfx r3, r3, #4, #4
85 .loc 1 267 22 view .LVU14
86 001c 184A ldr r2, .L12+4
87 001e D15C ldrb r1, [r2, r3] @ zero_extendqisi2
88 .LVL0:
85 .loc 1 267 3 view .LVU14
86 .loc 1 267 28 is_stmt 0 view .LVU15
87 001a 184B ldr r3, .L11
88 001c 9B68 ldr r3, [r3, #8]
89 .loc 1 267 52 view .LVU16
90 001e C3F30313 ubfx r3, r3, #4, #4
91 .loc 1 267 22 view .LVU17
92 0022 194A ldr r2, .L11+12
93 0024 D15C ldrb r1, [r2, r3] @ zero_extendqisi2
94 .LVL0:
268:Src/system_stm32g4xx.c **** /* HCLK clock frequency */
269:Src/system_stm32g4xx.c **** SystemCoreClock >>= tmp;
89 .loc 1 269 3 is_stmt 1 view .LVU15
90 .loc 1 269 19 is_stmt 0 view .LVU16
91 0020 184A ldr r2, .L12+8
92 0022 1368 ldr r3, [r2]
93 0024 CB40 lsrs r3, r3, r1
94 0026 1360 str r3, [r2]
95 .loc 1 269 3 is_stmt 1 view .LVU18
96 .loc 1 269 19 is_stmt 0 view .LVU19
97 0026 164A ldr r2, .L11+4
98 0028 1368 ldr r3, [r2]
99 002a CB40 lsrs r3, r3, r1
100 002c 1360 str r3, [r2]
270:Src/system_stm32g4xx.c **** }
95 .loc 1 270 1 view .LVU17
96 0028 7047 bx lr
97 .LVL1:
98 .L10:
236:Src/system_stm32g4xx.c **** break;
99 .loc 1 236 7 is_stmt 1 view .LVU18
236:Src/system_stm32g4xx.c **** break;
100 .loc 1 236 23 is_stmt 0 view .LVU19
101 002a 164B ldr r3, .L12+8
102 002c 164A ldr r2, .L12+12
103 002e 1A60 str r2, [r3]
237:Src/system_stm32g4xx.c ****
104 .loc 1 237 7 is_stmt 1 view .LVU20
105 0030 F0E7 b .L7
106 .L5:
101 .loc 1 270 1 view .LVU20
102 002e 7047 bx lr
103 .LVL1:
104 .L5:
240:Src/system_stm32g4xx.c **** break;
107 .loc 1 240 7 view .LVU21
105 .loc 1 240 7 is_stmt 1 view .LVU21
240:Src/system_stm32g4xx.c **** break;
108 .loc 1 240 23 is_stmt 0 view .LVU22
109 0032 144B ldr r3, .L12+8
110 0034 154A ldr r2, .L12+16
111 0036 1A60 str r2, [r3]
106 .loc 1 240 23 is_stmt 0 view .LVU22
107 0030 134B ldr r3, .L11+4
108 0032 164A ldr r2, .L11+16
109 0034 1A60 str r2, [r3]
241:Src/system_stm32g4xx.c ****
112 .loc 1 241 7 is_stmt 1 view .LVU23
113 0038 ECE7 b .L7
114 .L6:
110 .loc 1 241 7 is_stmt 1 view .LVU23
111 0036 F0E7 b .L7
112 .L6:
247:Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
115 .loc 1 247 7 view .LVU24
113 .loc 1 247 7 view .LVU24
247:Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
116 .loc 1 247 23 is_stmt 0 view .LVU25
117 003a 104A ldr r2, .L12
118 003c D368 ldr r3, [r2, #12]
114 .loc 1 247 23 is_stmt 0 view .LVU25
115 0038 104A ldr r2, .L11
116 003a D368 ldr r3, [r2, #12]
247:Src/system_stm32g4xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
119 .loc 1 247 17 view .LVU26
120 003e 03F00303 and r3, r3, #3
121 .LVL2:
117 .loc 1 247 17 view .LVU26
118 003c 03F00303 and r3, r3, #3
119 .LVL2:
248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
122 .loc 1 248 7 is_stmt 1 view .LVU27
ARM GAS /tmp/cc1Ld1Ft.s page 8
120 .loc 1 248 7 is_stmt 1 view .LVU27
248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
121 .loc 1 248 19 is_stmt 0 view .LVU28
122 0040 D268 ldr r2, [r2, #12]
248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
123 .loc 1 248 49 view .LVU29
ARM GAS /tmp/ccV7jtdT.s page 8
124 0042 C2F30312 ubfx r2, r2, #4, #4
248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
123 .loc 1 248 19 is_stmt 0 view .LVU28
124 0042 D268 ldr r2, [r2, #12]
248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
125 .loc 1 248 49 view .LVU29
126 0044 C2F30312 ubfx r2, r2, #4, #4
248:Src/system_stm32g4xx.c **** if (pllsource == 0x02UL) /* HSI used as PLL clock source */
127 .loc 1 248 12 view .LVU30
128 0048 0132 adds r2, r2, #1
129 .LVL3:
125 .loc 1 248 12 view .LVU30
126 0046 0132 adds r2, r2, #1
127 .LVL3:
249:Src/system_stm32g4xx.c **** {
130 .loc 1 249 7 is_stmt 1 view .LVU31
128 .loc 1 249 7 is_stmt 1 view .LVU31
249:Src/system_stm32g4xx.c **** {
131 .loc 1 249 10 is_stmt 0 view .LVU32
132 004a 022B cmp r3, #2
133 004c 12D0 beq .L11
129 .loc 1 249 10 is_stmt 0 view .LVU32
130 0048 022B cmp r3, #2
131 004a 12D0 beq .L10
255:Src/system_stm32g4xx.c **** }
134 .loc 1 255 9 is_stmt 1 view .LVU33
132 .loc 1 255 9 is_stmt 1 view .LVU33
255:Src/system_stm32g4xx.c **** }
135 .loc 1 255 16 is_stmt 0 view .LVU34
136 004e 0F4B ldr r3, .L12+16
137 .LVL4:
133 .loc 1 255 16 is_stmt 0 view .LVU34
134 004c 0F4B ldr r3, .L11+16
135 .LVL4:
255:Src/system_stm32g4xx.c **** }
138 .loc 1 255 16 view .LVU35
139 0050 B3FBF2F2 udiv r2, r3, r2
140 .LVL5:
141 .L9:
136 .loc 1 255 16 view .LVU35
137 004e B3FBF2F2 udiv r2, r3, r2
138 .LVL5:
139 .L9:
257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
142 .loc 1 257 7 is_stmt 1 view .LVU36
140 .loc 1 257 7 is_stmt 1 view .LVU36
257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
143 .loc 1 257 30 is_stmt 0 view .LVU37
144 0054 0949 ldr r1, .L12
145 0056 CB68 ldr r3, [r1, #12]
141 .loc 1 257 30 is_stmt 0 view .LVU37
142 0052 0A49 ldr r1, .L11
143 0054 CB68 ldr r3, [r1, #12]
257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
146 .loc 1 257 60 view .LVU38
147 0058 C3F30623 ubfx r3, r3, #8, #7
144 .loc 1 257 60 view .LVU38
145 0056 C3F30623 ubfx r3, r3, #8, #7
257:Src/system_stm32g4xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
148 .loc 1 257 14 view .LVU39
149 005c 02FB03F3 mul r3, r2, r3
150 .LVL6:
146 .loc 1 257 14 view .LVU39
147 005a 02FB03F3 mul r3, r2, r3
148 .LVL6:
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
151 .loc 1 258 7 is_stmt 1 view .LVU40
149 .loc 1 258 7 is_stmt 1 view .LVU40
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
152 .loc 1 258 20 is_stmt 0 view .LVU41
153 0060 CA68 ldr r2, [r1, #12]
150 .loc 1 258 20 is_stmt 0 view .LVU41
151 005e CA68 ldr r2, [r1, #12]
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
154 .loc 1 258 50 view .LVU42
155 0062 C2F34162 ubfx r2, r2, #25, #2
152 .loc 1 258 50 view .LVU42
153 0060 C2F34162 ubfx r2, r2, #25, #2
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
156 .loc 1 258 57 view .LVU43
157 0066 0132 adds r2, r2, #1
154 .loc 1 258 57 view .LVU43
155 0064 0132 adds r2, r2, #1
258:Src/system_stm32g4xx.c **** SystemCoreClock = pllvco/pllr;
158 .loc 1 258 12 view .LVU44
159 0068 5200 lsls r2, r2, #1
160 .LVL7:
156 .loc 1 258 12 view .LVU44
157 0066 5200 lsls r2, r2, #1
158 .LVL7:
259:Src/system_stm32g4xx.c **** break;
161 .loc 1 259 7 is_stmt 1 view .LVU45
ARM GAS /tmp/cc1Ld1Ft.s page 9
159 .loc 1 259 7 is_stmt 1 view .LVU45
259:Src/system_stm32g4xx.c **** break;
160 .loc 1 259 31 is_stmt 0 view .LVU46
161 0068 B3FBF2F3 udiv r3, r3, r2
162 .LVL8:
259:Src/system_stm32g4xx.c **** break;
ARM GAS /tmp/ccV7jtdT.s page 9
163 .loc 1 259 23 view .LVU47
164 006c 044A ldr r2, .L11+4
165 .LVL9:
259:Src/system_stm32g4xx.c **** break;
162 .loc 1 259 31 is_stmt 0 view .LVU46
163 006a B3FBF2F3 udiv r3, r3, r2
164 .LVL8:
259:Src/system_stm32g4xx.c **** break;
165 .loc 1 259 23 view .LVU47
166 006e 054A ldr r2, .L12+8
167 .LVL9:
259:Src/system_stm32g4xx.c **** break;
168 .loc 1 259 23 view .LVU48
169 0070 1360 str r3, [r2]
166 .loc 1 259 23 view .LVU48
167 006e 1360 str r3, [r2]
260:Src/system_stm32g4xx.c ****
170 .loc 1 260 7 is_stmt 1 view .LVU49
171 0072 CFE7 b .L7
172 .LVL10:
173 .L11:
168 .loc 1 260 7 is_stmt 1 view .LVU49
169 0070 D3E7 b .L7
170 .LVL10:
171 .L10:
251:Src/system_stm32g4xx.c **** }
174 .loc 1 251 9 view .LVU50
172 .loc 1 251 9 view .LVU50
251:Src/system_stm32g4xx.c **** }
175 .loc 1 251 16 is_stmt 0 view .LVU51
176 0074 044B ldr r3, .L12+12
177 .LVL11:
173 .loc 1 251 16 is_stmt 0 view .LVU51
174 0072 044B ldr r3, .L11+8
175 .LVL11:
251:Src/system_stm32g4xx.c **** }
178 .loc 1 251 16 view .LVU52
179 0076 B3FBF2F2 udiv r2, r3, r2
180 .LVL12:
176 .loc 1 251 16 view .LVU52
177 0074 B3FBF2F2 udiv r2, r3, r2
178 .LVL12:
251:Src/system_stm32g4xx.c **** }
181 .loc 1 251 16 view .LVU53
182 007a EBE7 b .L9
183 .L13:
184 .align 2
185 .L12:
186 007c 00100240 .word 1073876992
187 0080 00000000 .word AHBPrescTable
188 0084 00000000 .word SystemCoreClock
189 0088 0024F400 .word 16000000
190 008c 0080BB00 .word 12288000
191 .cfi_endproc
192 .LFE330:
194 .global APBPrescTable
195 .section .rodata.APBPrescTable,"a"
196 .align 2
199 APBPrescTable:
200 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
200 01020304
201 .global AHBPrescTable
202 .section .rodata.AHBPrescTable,"a"
203 .align 2
206 AHBPrescTable:
207 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
207 00000000
207 01020304
207 06
208 000d 070809 .ascii "\007\010\011"
209 .global SystemCoreClock
210 .section .data.SystemCoreClock,"aw"
211 .align 2
ARM GAS /tmp/cc1Ld1Ft.s page 10
179 .loc 1 251 16 view .LVU53
180 0078 EBE7 b .L9
181 .L12:
182 007a 00BF .align 2
183 .L11:
184 007c 00100240 .word 1073876992
185 0080 00000000 .word SystemCoreClock
186 0084 0024F400 .word 16000000
187 0088 00000000 .word AHBPrescTable
188 008c 0080BB00 .word 12288000
189 .cfi_endproc
190 .LFE330:
192 .global APBPrescTable
193 .section .rodata.APBPrescTable,"a"
194 .align 2
197 APBPrescTable:
198 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
198 01020304
199 .global AHBPrescTable
200 .section .rodata.AHBPrescTable,"a"
201 .align 2
204 AHBPrescTable:
205 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
205 00000000
205 01020304
205 06
206 000d 070809 .ascii "\007\010\011"
207 .global SystemCoreClock
208 .section .data.SystemCoreClock,"aw"
209 .align 2
212 SystemCoreClock:
213 0000 0024F400 .word 16000000
214 .text
215 .Letext0:
216 .file 2 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach
ARM GAS /tmp/ccV7jtdT.s page 10
214 SystemCoreClock:
215 0000 0024F400 .word 16000000
216 .text
217 .Letext0:
218 .file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h"
219 .file 3 "Drivers/CMSIS/Include/core_cm4.h"
220 .file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
221 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
ARM GAS /tmp/cc1Ld1Ft.s page 11
217 .file 3 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/
218 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
219 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
220 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
ARM GAS /tmp/ccV7jtdT.s page 11
DEFINED SYMBOLS
*ABS*:00000000 system_stm32g4xx.c
/tmp/cc1Ld1Ft.s:21 .text.SystemInit:00000000 $t
/tmp/cc1Ld1Ft.s:27 .text.SystemInit:00000000 SystemInit
/tmp/cc1Ld1Ft.s:46 .text.SystemInit:00000010 $d
/tmp/cc1Ld1Ft.s:51 .text.SystemCoreClockUpdate:00000000 $t
/tmp/cc1Ld1Ft.s:57 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
/tmp/cc1Ld1Ft.s:186 .text.SystemCoreClockUpdate:0000007c $d
/tmp/cc1Ld1Ft.s:206 .rodata.AHBPrescTable:00000000 AHBPrescTable
/tmp/cc1Ld1Ft.s:214 .data.SystemCoreClock:00000000 SystemCoreClock
/tmp/cc1Ld1Ft.s:199 .rodata.APBPrescTable:00000000 APBPrescTable
/tmp/cc1Ld1Ft.s:196 .rodata.APBPrescTable:00000000 $d
/tmp/cc1Ld1Ft.s:203 .rodata.AHBPrescTable:00000000 $d
/tmp/cc1Ld1Ft.s:211 .data.SystemCoreClock:00000000 $d
/tmp/ccV7jtdT.s:21 .text.SystemInit:00000000 $t
/tmp/ccV7jtdT.s:27 .text.SystemInit:00000000 SystemInit
/tmp/ccV7jtdT.s:46 .text.SystemInit:00000010 $d
/tmp/ccV7jtdT.s:51 .text.SystemCoreClockUpdate:00000000 $t
/tmp/ccV7jtdT.s:57 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
/tmp/ccV7jtdT.s:184 .text.SystemCoreClockUpdate:0000007c $d
/tmp/ccV7jtdT.s:212 .data.SystemCoreClock:00000000 SystemCoreClock
/tmp/ccV7jtdT.s:204 .rodata.AHBPrescTable:00000000 AHBPrescTable
/tmp/ccV7jtdT.s:197 .rodata.APBPrescTable:00000000 APBPrescTable
/tmp/ccV7jtdT.s:194 .rodata.APBPrescTable:00000000 $d
/tmp/ccV7jtdT.s:201 .rodata.AHBPrescTable:00000000 $d
/tmp/ccV7jtdT.s:209 .data.SystemCoreClock:00000000 $d
NO UNDEFINED SYMBOLS