ARM GAS /tmp/ccDEPnZG.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32g4xx_hal_cortex.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c" 20 .section .text.__NVIC_EnableIRQ,"ax",%progbits 21 .align 1 22 .syntax unified 23 .thumb 24 .thumb_func 26 __NVIC_EnableIRQ: 27 .LVL0: 28 .LFB106: 29 .file 2 "Drivers/CMSIS/Include/core_cm4.h" 1:Drivers/CMSIS/Include/core_cm4.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/core_cm4.h **** * @file core_cm4.h 3:Drivers/CMSIS/Include/core_cm4.h **** * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 4:Drivers/CMSIS/Include/core_cm4.h **** * @version V5.1.0 5:Drivers/CMSIS/Include/core_cm4.h **** * @date 13. March 2019 6:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/core_cm4.h **** /* 8:Drivers/CMSIS/Include/core_cm4.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/core_cm4.h **** * 10:Drivers/CMSIS/Include/core_cm4.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/core_cm4.h **** * 12:Drivers/CMSIS/Include/core_cm4.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/core_cm4.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/core_cm4.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/core_cm4.h **** * 16:Drivers/CMSIS/Include/core_cm4.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/core_cm4.h **** * 18:Drivers/CMSIS/Include/core_cm4.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/core_cm4.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/core_cm4.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/core_cm4.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/core_cm4.h **** * limitations under the License. 23:Drivers/CMSIS/Include/core_cm4.h **** */ 24:Drivers/CMSIS/Include/core_cm4.h **** 25:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __ICCARM__ ) 26:Drivers/CMSIS/Include/core_cm4.h **** #pragma system_include /* treat file as system include file for MISRA check */ 27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__) 28:Drivers/CMSIS/Include/core_cm4.h **** #pragma clang system_header /* treat file as system include file */ 29:Drivers/CMSIS/Include/core_cm4.h **** #endif ARM GAS /tmp/ccDEPnZG.s page 2 30:Drivers/CMSIS/Include/core_cm4.h **** 31:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC 32:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_GENERIC 33:Drivers/CMSIS/Include/core_cm4.h **** 34:Drivers/CMSIS/Include/core_cm4.h **** #include 35:Drivers/CMSIS/Include/core_cm4.h **** 36:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 37:Drivers/CMSIS/Include/core_cm4.h **** extern "C" { 38:Drivers/CMSIS/Include/core_cm4.h **** #endif 39:Drivers/CMSIS/Include/core_cm4.h **** 40:Drivers/CMSIS/Include/core_cm4.h **** /** 41:Drivers/CMSIS/Include/core_cm4.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42:Drivers/CMSIS/Include/core_cm4.h **** CMSIS violates the following MISRA-C:2004 rules: 43:Drivers/CMSIS/Include/core_cm4.h **** 44:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 8.5, object/function definition in header file.
45:Drivers/CMSIS/Include/core_cm4.h **** Function definitions in header files are used to allow 'inlining'. 46:Drivers/CMSIS/Include/core_cm4.h **** 47:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48:Drivers/CMSIS/Include/core_cm4.h **** Unions are used for effective representation of core registers. 49:Drivers/CMSIS/Include/core_cm4.h **** 50:Drivers/CMSIS/Include/core_cm4.h **** \li Advisory Rule 19.7, Function-like macro defined.
51:Drivers/CMSIS/Include/core_cm4.h **** Function-like macros are used to allow more efficient code. 52:Drivers/CMSIS/Include/core_cm4.h **** */ 53:Drivers/CMSIS/Include/core_cm4.h **** 54:Drivers/CMSIS/Include/core_cm4.h **** 55:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* 56:Drivers/CMSIS/Include/core_cm4.h **** * CMSIS definitions 57:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 58:Drivers/CMSIS/Include/core_cm4.h **** /** 59:Drivers/CMSIS/Include/core_cm4.h **** \ingroup Cortex_M4 60:Drivers/CMSIS/Include/core_cm4.h **** @{ 61:Drivers/CMSIS/Include/core_cm4.h **** */ 62:Drivers/CMSIS/Include/core_cm4.h **** 63:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_version.h" 64:Drivers/CMSIS/Include/core_cm4.h **** 65:Drivers/CMSIS/Include/core_cm4.h **** /* CMSIS CM4 definitions */ 66:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C 67:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C 68:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ 69:Drivers/CMSIS/Include/core_cm4.h **** __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL 70:Drivers/CMSIS/Include/core_cm4.h **** 71:Drivers/CMSIS/Include/core_cm4.h **** #define __CORTEX_M (4U) /*!< Cortex-M Core */ 72:Drivers/CMSIS/Include/core_cm4.h **** 73:Drivers/CMSIS/Include/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not. 74:Drivers/CMSIS/Include/core_cm4.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun 75:Drivers/CMSIS/Include/core_cm4.h **** */ 76:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __CC_ARM ) 77:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TARGET_FPU_VFP 78:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 79:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 80:Drivers/CMSIS/Include/core_cm4.h **** #else 81:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 82:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 83:Drivers/CMSIS/Include/core_cm4.h **** #endif 84:Drivers/CMSIS/Include/core_cm4.h **** #else 85:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 86:Drivers/CMSIS/Include/core_cm4.h **** #endif ARM GAS /tmp/ccDEPnZG.s page 3 87:Drivers/CMSIS/Include/core_cm4.h **** 88:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 89:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARM_FP 90:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 91:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 92:Drivers/CMSIS/Include/core_cm4.h **** #else 93:Drivers/CMSIS/Include/core_cm4.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN 94:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 95:Drivers/CMSIS/Include/core_cm4.h **** #endif 96:Drivers/CMSIS/Include/core_cm4.h **** #else 97:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 98:Drivers/CMSIS/Include/core_cm4.h **** #endif 99:Drivers/CMSIS/Include/core_cm4.h **** 100:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __GNUC__ ) 101:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) 102:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 103:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 104:Drivers/CMSIS/Include/core_cm4.h **** #else 105:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 106:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 107:Drivers/CMSIS/Include/core_cm4.h **** #endif 108:Drivers/CMSIS/Include/core_cm4.h **** #else 109:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 110:Drivers/CMSIS/Include/core_cm4.h **** #endif 111:Drivers/CMSIS/Include/core_cm4.h **** 112:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __ICCARM__ ) 113:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARMVFP__ 114:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 115:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 116:Drivers/CMSIS/Include/core_cm4.h **** #else 117:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 118:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 119:Drivers/CMSIS/Include/core_cm4.h **** #endif 120:Drivers/CMSIS/Include/core_cm4.h **** #else 121:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 122:Drivers/CMSIS/Include/core_cm4.h **** #endif 123:Drivers/CMSIS/Include/core_cm4.h **** 124:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TI_ARM__ ) 125:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TI_VFP_SUPPORT__ 126:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 127:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 128:Drivers/CMSIS/Include/core_cm4.h **** #else 129:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 130:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 131:Drivers/CMSIS/Include/core_cm4.h **** #endif 132:Drivers/CMSIS/Include/core_cm4.h **** #else 133:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 134:Drivers/CMSIS/Include/core_cm4.h **** #endif 135:Drivers/CMSIS/Include/core_cm4.h **** 136:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TASKING__ ) 137:Drivers/CMSIS/Include/core_cm4.h **** #if defined __FPU_VFP__ 138:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 139:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 140:Drivers/CMSIS/Include/core_cm4.h **** #else 141:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 142:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 143:Drivers/CMSIS/Include/core_cm4.h **** #endif ARM GAS /tmp/ccDEPnZG.s page 4 144:Drivers/CMSIS/Include/core_cm4.h **** #else 145:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 146:Drivers/CMSIS/Include/core_cm4.h **** #endif 147:Drivers/CMSIS/Include/core_cm4.h **** 148:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __CSMC__ ) 149:Drivers/CMSIS/Include/core_cm4.h **** #if ( __CSMC__ & 0x400U) 150:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 151:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U 152:Drivers/CMSIS/Include/core_cm4.h **** #else 153:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) 154:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 155:Drivers/CMSIS/Include/core_cm4.h **** #endif 156:Drivers/CMSIS/Include/core_cm4.h **** #else 157:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U 158:Drivers/CMSIS/Include/core_cm4.h **** #endif 159:Drivers/CMSIS/Include/core_cm4.h **** 160:Drivers/CMSIS/Include/core_cm4.h **** #endif 161:Drivers/CMSIS/Include/core_cm4.h **** 162:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 163:Drivers/CMSIS/Include/core_cm4.h **** 164:Drivers/CMSIS/Include/core_cm4.h **** 165:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 166:Drivers/CMSIS/Include/core_cm4.h **** } 167:Drivers/CMSIS/Include/core_cm4.h **** #endif 168:Drivers/CMSIS/Include/core_cm4.h **** 169:Drivers/CMSIS/Include/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */ 170:Drivers/CMSIS/Include/core_cm4.h **** 171:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CMSIS_GENERIC 172:Drivers/CMSIS/Include/core_cm4.h **** 173:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT 174:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT 175:Drivers/CMSIS/Include/core_cm4.h **** 176:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 177:Drivers/CMSIS/Include/core_cm4.h **** extern "C" { 178:Drivers/CMSIS/Include/core_cm4.h **** #endif 179:Drivers/CMSIS/Include/core_cm4.h **** 180:Drivers/CMSIS/Include/core_cm4.h **** /* check device defines and use defaults */ 181:Drivers/CMSIS/Include/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES 182:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CM4_REV 183:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_REV 0x0000U 184:Drivers/CMSIS/Include/core_cm4.h **** #warning "__CM4_REV not defined in device header file; using default!" 185:Drivers/CMSIS/Include/core_cm4.h **** #endif 186:Drivers/CMSIS/Include/core_cm4.h **** 187:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __FPU_PRESENT 188:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_PRESENT 0U 189:Drivers/CMSIS/Include/core_cm4.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" 190:Drivers/CMSIS/Include/core_cm4.h **** #endif 191:Drivers/CMSIS/Include/core_cm4.h **** 192:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __MPU_PRESENT 193:Drivers/CMSIS/Include/core_cm4.h **** #define __MPU_PRESENT 0U 194:Drivers/CMSIS/Include/core_cm4.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" 195:Drivers/CMSIS/Include/core_cm4.h **** #endif 196:Drivers/CMSIS/Include/core_cm4.h **** 197:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __NVIC_PRIO_BITS 198:Drivers/CMSIS/Include/core_cm4.h **** #define __NVIC_PRIO_BITS 3U 199:Drivers/CMSIS/Include/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 200:Drivers/CMSIS/Include/core_cm4.h **** #endif ARM GAS /tmp/ccDEPnZG.s page 5 201:Drivers/CMSIS/Include/core_cm4.h **** 202:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __Vendor_SysTickConfig 203:Drivers/CMSIS/Include/core_cm4.h **** #define __Vendor_SysTickConfig 0U 204:Drivers/CMSIS/Include/core_cm4.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 205:Drivers/CMSIS/Include/core_cm4.h **** #endif 206:Drivers/CMSIS/Include/core_cm4.h **** #endif 207:Drivers/CMSIS/Include/core_cm4.h **** 208:Drivers/CMSIS/Include/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */ 209:Drivers/CMSIS/Include/core_cm4.h **** /** 210:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines 211:Drivers/CMSIS/Include/core_cm4.h **** 212:Drivers/CMSIS/Include/core_cm4.h **** IO Type Qualifiers are used 213:Drivers/CMSIS/Include/core_cm4.h **** \li to specify the access to peripheral variables. 214:Drivers/CMSIS/Include/core_cm4.h **** \li for automatic generation of peripheral register debug information. 215:Drivers/CMSIS/Include/core_cm4.h **** */ 216:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus 217:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile /*!< Defines 'read only' permissions */ 218:Drivers/CMSIS/Include/core_cm4.h **** #else 219:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile const /*!< Defines 'read only' permissions */ 220:Drivers/CMSIS/Include/core_cm4.h **** #endif 221:Drivers/CMSIS/Include/core_cm4.h **** #define __O volatile /*!< Defines 'write only' permissions */ 222:Drivers/CMSIS/Include/core_cm4.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ 223:Drivers/CMSIS/Include/core_cm4.h **** 224:Drivers/CMSIS/Include/core_cm4.h **** /* following defines should be used for structure members */ 225:Drivers/CMSIS/Include/core_cm4.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ 226:Drivers/CMSIS/Include/core_cm4.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ 227:Drivers/CMSIS/Include/core_cm4.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 228:Drivers/CMSIS/Include/core_cm4.h **** 229:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group Cortex_M4 */ 230:Drivers/CMSIS/Include/core_cm4.h **** 231:Drivers/CMSIS/Include/core_cm4.h **** 232:Drivers/CMSIS/Include/core_cm4.h **** 233:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* 234:Drivers/CMSIS/Include/core_cm4.h **** * Register Abstraction 235:Drivers/CMSIS/Include/core_cm4.h **** Core Register contain: 236:Drivers/CMSIS/Include/core_cm4.h **** - Core Register 237:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Register 238:Drivers/CMSIS/Include/core_cm4.h **** - Core SCB Register 239:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Register 240:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Register 241:Drivers/CMSIS/Include/core_cm4.h **** - Core MPU Register 242:Drivers/CMSIS/Include/core_cm4.h **** - Core FPU Register 243:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 244:Drivers/CMSIS/Include/core_cm4.h **** /** 245:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_register Defines and Type Definitions 246:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions and defines for Cortex-M processor based devices. 247:Drivers/CMSIS/Include/core_cm4.h **** */ 248:Drivers/CMSIS/Include/core_cm4.h **** 249:Drivers/CMSIS/Include/core_cm4.h **** /** 250:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 251:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CORE Status and Control Registers 252:Drivers/CMSIS/Include/core_cm4.h **** \brief Core Register type definitions. 253:Drivers/CMSIS/Include/core_cm4.h **** @{ 254:Drivers/CMSIS/Include/core_cm4.h **** */ 255:Drivers/CMSIS/Include/core_cm4.h **** 256:Drivers/CMSIS/Include/core_cm4.h **** /** 257:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR). ARM GAS /tmp/ccDEPnZG.s page 6 258:Drivers/CMSIS/Include/core_cm4.h **** */ 259:Drivers/CMSIS/Include/core_cm4.h **** typedef union 260:Drivers/CMSIS/Include/core_cm4.h **** { 261:Drivers/CMSIS/Include/core_cm4.h **** struct 262:Drivers/CMSIS/Include/core_cm4.h **** { 263:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 264:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 265:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 266:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 267:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 268:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 269:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 270:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 271:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 272:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 273:Drivers/CMSIS/Include/core_cm4.h **** } APSR_Type; 274:Drivers/CMSIS/Include/core_cm4.h **** 275:Drivers/CMSIS/Include/core_cm4.h **** /* APSR Register Definitions */ 276:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Pos 31U /*!< APSR 277:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR 278:Drivers/CMSIS/Include/core_cm4.h **** 279:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Pos 30U /*!< APSR 280:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR 281:Drivers/CMSIS/Include/core_cm4.h **** 282:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Pos 29U /*!< APSR 283:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 284:Drivers/CMSIS/Include/core_cm4.h **** 285:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Pos 28U /*!< APSR 286:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR 287:Drivers/CMSIS/Include/core_cm4.h **** 288:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Pos 27U /*!< APSR 289:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR 290:Drivers/CMSIS/Include/core_cm4.h **** 291:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Pos 16U /*!< APSR 292:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR 293:Drivers/CMSIS/Include/core_cm4.h **** 294:Drivers/CMSIS/Include/core_cm4.h **** 295:Drivers/CMSIS/Include/core_cm4.h **** /** 296:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). 297:Drivers/CMSIS/Include/core_cm4.h **** */ 298:Drivers/CMSIS/Include/core_cm4.h **** typedef union 299:Drivers/CMSIS/Include/core_cm4.h **** { 300:Drivers/CMSIS/Include/core_cm4.h **** struct 301:Drivers/CMSIS/Include/core_cm4.h **** { 302:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 303:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 304:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 305:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 306:Drivers/CMSIS/Include/core_cm4.h **** } IPSR_Type; 307:Drivers/CMSIS/Include/core_cm4.h **** 308:Drivers/CMSIS/Include/core_cm4.h **** /* IPSR Register Definitions */ 309:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Pos 0U /*!< IPSR 310:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR 311:Drivers/CMSIS/Include/core_cm4.h **** 312:Drivers/CMSIS/Include/core_cm4.h **** 313:Drivers/CMSIS/Include/core_cm4.h **** /** 314:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). ARM GAS /tmp/ccDEPnZG.s page 7 315:Drivers/CMSIS/Include/core_cm4.h **** */ 316:Drivers/CMSIS/Include/core_cm4.h **** typedef union 317:Drivers/CMSIS/Include/core_cm4.h **** { 318:Drivers/CMSIS/Include/core_cm4.h **** struct 319:Drivers/CMSIS/Include/core_cm4.h **** { 320:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 322:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 323:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 324:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 325:Drivers/CMSIS/Include/core_cm4.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ 326:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 327:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 328:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 329:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 330:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 331:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 332:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 333:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 334:Drivers/CMSIS/Include/core_cm4.h **** } xPSR_Type; 335:Drivers/CMSIS/Include/core_cm4.h **** 336:Drivers/CMSIS/Include/core_cm4.h **** /* xPSR Register Definitions */ 337:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Pos 31U /*!< xPSR 338:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR 339:Drivers/CMSIS/Include/core_cm4.h **** 340:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Pos 30U /*!< xPSR 341:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR 342:Drivers/CMSIS/Include/core_cm4.h **** 343:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Pos 29U /*!< xPSR 344:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR 345:Drivers/CMSIS/Include/core_cm4.h **** 346:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Pos 28U /*!< xPSR 347:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR 348:Drivers/CMSIS/Include/core_cm4.h **** 349:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Pos 27U /*!< xPSR 350:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR 351:Drivers/CMSIS/Include/core_cm4.h **** 352:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR 353:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR 354:Drivers/CMSIS/Include/core_cm4.h **** 355:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Pos 24U /*!< xPSR 356:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 357:Drivers/CMSIS/Include/core_cm4.h **** 358:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Pos 16U /*!< xPSR 359:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR 360:Drivers/CMSIS/Include/core_cm4.h **** 361:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR 362:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR 363:Drivers/CMSIS/Include/core_cm4.h **** 364:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Pos 0U /*!< xPSR 365:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR 366:Drivers/CMSIS/Include/core_cm4.h **** 367:Drivers/CMSIS/Include/core_cm4.h **** 368:Drivers/CMSIS/Include/core_cm4.h **** /** 369:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL). 370:Drivers/CMSIS/Include/core_cm4.h **** */ 371:Drivers/CMSIS/Include/core_cm4.h **** typedef union ARM GAS /tmp/ccDEPnZG.s page 8 372:Drivers/CMSIS/Include/core_cm4.h **** { 373:Drivers/CMSIS/Include/core_cm4.h **** struct 374:Drivers/CMSIS/Include/core_cm4.h **** { 375:Drivers/CMSIS/Include/core_cm4.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 376:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 377:Drivers/CMSIS/Include/core_cm4.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 378:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 379:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ 380:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ 381:Drivers/CMSIS/Include/core_cm4.h **** } CONTROL_Type; 382:Drivers/CMSIS/Include/core_cm4.h **** 383:Drivers/CMSIS/Include/core_cm4.h **** /* CONTROL Register Definitions */ 384:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT 385:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT 386:Drivers/CMSIS/Include/core_cm4.h **** 387:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT 388:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT 389:Drivers/CMSIS/Include/core_cm4.h **** 390:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT 391:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT 392:Drivers/CMSIS/Include/core_cm4.h **** 393:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CORE */ 394:Drivers/CMSIS/Include/core_cm4.h **** 395:Drivers/CMSIS/Include/core_cm4.h **** 396:Drivers/CMSIS/Include/core_cm4.h **** /** 397:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 398:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 399:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the NVIC Registers 400:Drivers/CMSIS/Include/core_cm4.h **** @{ 401:Drivers/CMSIS/Include/core_cm4.h **** */ 402:Drivers/CMSIS/Include/core_cm4.h **** 403:Drivers/CMSIS/Include/core_cm4.h **** /** 404:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 405:Drivers/CMSIS/Include/core_cm4.h **** */ 406:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 407:Drivers/CMSIS/Include/core_cm4.h **** { 408:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 409:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[24U]; 410:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register 411:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[24U]; 412:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * 413:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[24U]; 414:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register 415:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[24U]; 416:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 417:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[56U]; 418:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi 419:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[644U]; 420:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis 421:Drivers/CMSIS/Include/core_cm4.h **** } NVIC_Type; 422:Drivers/CMSIS/Include/core_cm4.h **** 423:Drivers/CMSIS/Include/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */ 424:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I 425:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I 426:Drivers/CMSIS/Include/core_cm4.h **** 427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */ 428:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 9 429:Drivers/CMSIS/Include/core_cm4.h **** 430:Drivers/CMSIS/Include/core_cm4.h **** /** 431:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 432:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCB System Control Block (SCB) 433:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control Block Registers 434:Drivers/CMSIS/Include/core_cm4.h **** @{ 435:Drivers/CMSIS/Include/core_cm4.h **** */ 436:Drivers/CMSIS/Include/core_cm4.h **** 437:Drivers/CMSIS/Include/core_cm4.h **** /** 438:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control Block (SCB). 439:Drivers/CMSIS/Include/core_cm4.h **** */ 440:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 441:Drivers/CMSIS/Include/core_cm4.h **** { 442:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 443:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi 444:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 445:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset 446:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 447:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * 448:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe 449:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State 450:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist 451:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 452:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 453:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register 454:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 455:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register 456:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 457:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 458:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 459:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 460:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis 461:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[5U]; 462:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis 463:Drivers/CMSIS/Include/core_cm4.h **** } SCB_Type; 464:Drivers/CMSIS/Include/core_cm4.h **** 465:Drivers/CMSIS/Include/core_cm4.h **** /* SCB CPUID Register Definitions */ 466:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB 467:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB 468:Drivers/CMSIS/Include/core_cm4.h **** 469:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB 470:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB 471:Drivers/CMSIS/Include/core_cm4.h **** 472:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB 473:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB 474:Drivers/CMSIS/Include/core_cm4.h **** 475:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB 476:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB 477:Drivers/CMSIS/Include/core_cm4.h **** 478:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB 479:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB 480:Drivers/CMSIS/Include/core_cm4.h **** 481:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */ 482:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB 483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB 484:Drivers/CMSIS/Include/core_cm4.h **** 485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ARM GAS /tmp/ccDEPnZG.s page 10 486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB 487:Drivers/CMSIS/Include/core_cm4.h **** 488:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB 489:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB 490:Drivers/CMSIS/Include/core_cm4.h **** 491:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB 492:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB 493:Drivers/CMSIS/Include/core_cm4.h **** 494:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB 495:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB 496:Drivers/CMSIS/Include/core_cm4.h **** 497:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB 498:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB 499:Drivers/CMSIS/Include/core_cm4.h **** 500:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB 501:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB 502:Drivers/CMSIS/Include/core_cm4.h **** 503:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 504:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB 505:Drivers/CMSIS/Include/core_cm4.h **** 506:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB 507:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB 508:Drivers/CMSIS/Include/core_cm4.h **** 509:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB 510:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB 511:Drivers/CMSIS/Include/core_cm4.h **** 512:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */ 513:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB 514:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB 515:Drivers/CMSIS/Include/core_cm4.h **** 516:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ 517:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB 518:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB 519:Drivers/CMSIS/Include/core_cm4.h **** 520:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB 521:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB 522:Drivers/CMSIS/Include/core_cm4.h **** 523:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB 524:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB 525:Drivers/CMSIS/Include/core_cm4.h **** 526:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB 527:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB 528:Drivers/CMSIS/Include/core_cm4.h **** 529:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB 530:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB 531:Drivers/CMSIS/Include/core_cm4.h **** 532:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB 533:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB 534:Drivers/CMSIS/Include/core_cm4.h **** 535:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB 536:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB 537:Drivers/CMSIS/Include/core_cm4.h **** 538:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Control Register Definitions */ 539:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB 540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB 541:Drivers/CMSIS/Include/core_cm4.h **** 542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB ARM GAS /tmp/ccDEPnZG.s page 11 543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB 544:Drivers/CMSIS/Include/core_cm4.h **** 545:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB 546:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB 547:Drivers/CMSIS/Include/core_cm4.h **** 548:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configuration Control Register Definitions */ 549:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB 550:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB 551:Drivers/CMSIS/Include/core_cm4.h **** 552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB 553:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB 554:Drivers/CMSIS/Include/core_cm4.h **** 555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB 556:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB 557:Drivers/CMSIS/Include/core_cm4.h **** 558:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB 559:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB 560:Drivers/CMSIS/Include/core_cm4.h **** 561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB 562:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB 563:Drivers/CMSIS/Include/core_cm4.h **** 564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB 565:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB 566:Drivers/CMSIS/Include/core_cm4.h **** 567:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */ 568:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB 569:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB 570:Drivers/CMSIS/Include/core_cm4.h **** 571:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB 572:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB 573:Drivers/CMSIS/Include/core_cm4.h **** 574:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB 575:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB 576:Drivers/CMSIS/Include/core_cm4.h **** 577:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB 578:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB 579:Drivers/CMSIS/Include/core_cm4.h **** 580:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB 581:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB 582:Drivers/CMSIS/Include/core_cm4.h **** 583:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB 584:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB 585:Drivers/CMSIS/Include/core_cm4.h **** 586:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB 587:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB 588:Drivers/CMSIS/Include/core_cm4.h **** 589:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB 590:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB 591:Drivers/CMSIS/Include/core_cm4.h **** 592:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB 593:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB 594:Drivers/CMSIS/Include/core_cm4.h **** 595:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB 596:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB 597:Drivers/CMSIS/Include/core_cm4.h **** 598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB 599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB ARM GAS /tmp/ccDEPnZG.s page 12 600:Drivers/CMSIS/Include/core_cm4.h **** 601:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB 602:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB 603:Drivers/CMSIS/Include/core_cm4.h **** 604:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB 605:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB 606:Drivers/CMSIS/Include/core_cm4.h **** 607:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB 608:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB 609:Drivers/CMSIS/Include/core_cm4.h **** 610:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */ 611:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB 612:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB 613:Drivers/CMSIS/Include/core_cm4.h **** 614:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB 615:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB 616:Drivers/CMSIS/Include/core_cm4.h **** 617:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB 618:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB 619:Drivers/CMSIS/Include/core_cm4.h **** 620:Drivers/CMSIS/Include/core_cm4.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 621:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB 622:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB 623:Drivers/CMSIS/Include/core_cm4.h **** 624:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB 625:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB 626:Drivers/CMSIS/Include/core_cm4.h **** 627:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB 628:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB 629:Drivers/CMSIS/Include/core_cm4.h **** 630:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB 631:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB 632:Drivers/CMSIS/Include/core_cm4.h **** 633:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB 634:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB 635:Drivers/CMSIS/Include/core_cm4.h **** 636:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB 637:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB 638:Drivers/CMSIS/Include/core_cm4.h **** 639:Drivers/CMSIS/Include/core_cm4.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 640:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB 641:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB 642:Drivers/CMSIS/Include/core_cm4.h **** 643:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB 644:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB 645:Drivers/CMSIS/Include/core_cm4.h **** 646:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB 647:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB 648:Drivers/CMSIS/Include/core_cm4.h **** 649:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB 650:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB 651:Drivers/CMSIS/Include/core_cm4.h **** 652:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB 653:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB 654:Drivers/CMSIS/Include/core_cm4.h **** 655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB 656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB ARM GAS /tmp/ccDEPnZG.s page 13 657:Drivers/CMSIS/Include/core_cm4.h **** 658:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB 659:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB 660:Drivers/CMSIS/Include/core_cm4.h **** 661:Drivers/CMSIS/Include/core_cm4.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 662:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB 663:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB 664:Drivers/CMSIS/Include/core_cm4.h **** 665:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB 666:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB 667:Drivers/CMSIS/Include/core_cm4.h **** 668:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB 669:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB 670:Drivers/CMSIS/Include/core_cm4.h **** 671:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB 672:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB 673:Drivers/CMSIS/Include/core_cm4.h **** 674:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB 675:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB 676:Drivers/CMSIS/Include/core_cm4.h **** 677:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB 678:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB 679:Drivers/CMSIS/Include/core_cm4.h **** 680:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */ 681:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB 682:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB 683:Drivers/CMSIS/Include/core_cm4.h **** 684:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB 685:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB 686:Drivers/CMSIS/Include/core_cm4.h **** 687:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB 688:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB 689:Drivers/CMSIS/Include/core_cm4.h **** 690:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */ 691:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB 692:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB 693:Drivers/CMSIS/Include/core_cm4.h **** 694:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB 695:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB 696:Drivers/CMSIS/Include/core_cm4.h **** 697:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB 698:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB 699:Drivers/CMSIS/Include/core_cm4.h **** 700:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB 701:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB 702:Drivers/CMSIS/Include/core_cm4.h **** 703:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB 704:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB 705:Drivers/CMSIS/Include/core_cm4.h **** 706:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCB */ 707:Drivers/CMSIS/Include/core_cm4.h **** 708:Drivers/CMSIS/Include/core_cm4.h **** 709:Drivers/CMSIS/Include/core_cm4.h **** /** 710:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 711:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 712:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB 713:Drivers/CMSIS/Include/core_cm4.h **** @{ ARM GAS /tmp/ccDEPnZG.s page 14 714:Drivers/CMSIS/Include/core_cm4.h **** */ 715:Drivers/CMSIS/Include/core_cm4.h **** 716:Drivers/CMSIS/Include/core_cm4.h **** /** 717:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control and ID Register not in the SCB. 718:Drivers/CMSIS/Include/core_cm4.h **** */ 719:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 720:Drivers/CMSIS/Include/core_cm4.h **** { 721:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; 722:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist 723:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 724:Drivers/CMSIS/Include/core_cm4.h **** } SCnSCB_Type; 725:Drivers/CMSIS/Include/core_cm4.h **** 726:Drivers/CMSIS/Include/core_cm4.h **** /* Interrupt Controller Type Register Definitions */ 727:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I 728:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I 729:Drivers/CMSIS/Include/core_cm4.h **** 730:Drivers/CMSIS/Include/core_cm4.h **** /* Auxiliary Control Register Definitions */ 731:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: 732:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: 733:Drivers/CMSIS/Include/core_cm4.h **** 734:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: 735:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: 736:Drivers/CMSIS/Include/core_cm4.h **** 737:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: 738:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: 739:Drivers/CMSIS/Include/core_cm4.h **** 740:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: 741:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: 742:Drivers/CMSIS/Include/core_cm4.h **** 743:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: 744:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: 745:Drivers/CMSIS/Include/core_cm4.h **** 746:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */ 747:Drivers/CMSIS/Include/core_cm4.h **** 748:Drivers/CMSIS/Include/core_cm4.h **** 749:Drivers/CMSIS/Include/core_cm4.h **** /** 750:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 751:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) 752:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Timer Registers. 753:Drivers/CMSIS/Include/core_cm4.h **** @{ 754:Drivers/CMSIS/Include/core_cm4.h **** */ 755:Drivers/CMSIS/Include/core_cm4.h **** 756:Drivers/CMSIS/Include/core_cm4.h **** /** 757:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Timer (SysTick). 758:Drivers/CMSIS/Include/core_cm4.h **** */ 759:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 760:Drivers/CMSIS/Include/core_cm4.h **** { 761:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis 762:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 763:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * 764:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 765:Drivers/CMSIS/Include/core_cm4.h **** } SysTick_Type; 766:Drivers/CMSIS/Include/core_cm4.h **** 767:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Control / Status Register Definitions */ 768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT 769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT 770:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 15 771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT 772:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT 773:Drivers/CMSIS/Include/core_cm4.h **** 774:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT 775:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT 776:Drivers/CMSIS/Include/core_cm4.h **** 777:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT 778:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT 779:Drivers/CMSIS/Include/core_cm4.h **** 780:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Reload Register Definitions */ 781:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT 782:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT 783:Drivers/CMSIS/Include/core_cm4.h **** 784:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Current Register Definitions */ 785:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT 786:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT 787:Drivers/CMSIS/Include/core_cm4.h **** 788:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Calibration Register Definitions */ 789:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT 790:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT 791:Drivers/CMSIS/Include/core_cm4.h **** 792:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT 793:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT 794:Drivers/CMSIS/Include/core_cm4.h **** 795:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT 796:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT 797:Drivers/CMSIS/Include/core_cm4.h **** 798:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SysTick */ 799:Drivers/CMSIS/Include/core_cm4.h **** 800:Drivers/CMSIS/Include/core_cm4.h **** 801:Drivers/CMSIS/Include/core_cm4.h **** /** 802:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 803:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 804:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 805:Drivers/CMSIS/Include/core_cm4.h **** @{ 806:Drivers/CMSIS/Include/core_cm4.h **** */ 807:Drivers/CMSIS/Include/core_cm4.h **** 808:Drivers/CMSIS/Include/core_cm4.h **** /** 809:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 810:Drivers/CMSIS/Include/core_cm4.h **** */ 811:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 812:Drivers/CMSIS/Include/core_cm4.h **** { 813:Drivers/CMSIS/Include/core_cm4.h **** __OM union 814:Drivers/CMSIS/Include/core_cm4.h **** { 815:Drivers/CMSIS/Include/core_cm4.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 816:Drivers/CMSIS/Include/core_cm4.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 817:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 818:Drivers/CMSIS/Include/core_cm4.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 819:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[864U]; 820:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 821:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[15U]; 822:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 823:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[15U]; 824:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 825:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[32U]; 826:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[43U]; 827:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ ARM GAS /tmp/ccDEPnZG.s page 16 828:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 829:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[6U]; 830:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re 831:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re 832:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re 833:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re 834:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re 835:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re 836:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re 837:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re 838:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re 839:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re 840:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re 841:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re 842:Drivers/CMSIS/Include/core_cm4.h **** } ITM_Type; 843:Drivers/CMSIS/Include/core_cm4.h **** 844:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Privilege Register Definitions */ 845:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM 846:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM 847:Drivers/CMSIS/Include/core_cm4.h **** 848:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Control Register Definitions */ 849:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM 850:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM 851:Drivers/CMSIS/Include/core_cm4.h **** 852:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM 853:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM 854:Drivers/CMSIS/Include/core_cm4.h **** 855:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM 856:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM 857:Drivers/CMSIS/Include/core_cm4.h **** 858:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM 859:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM 860:Drivers/CMSIS/Include/core_cm4.h **** 861:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM 862:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM 863:Drivers/CMSIS/Include/core_cm4.h **** 864:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM 865:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM 866:Drivers/CMSIS/Include/core_cm4.h **** 867:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM 868:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM 869:Drivers/CMSIS/Include/core_cm4.h **** 870:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM 871:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM 872:Drivers/CMSIS/Include/core_cm4.h **** 873:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM 874:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM 875:Drivers/CMSIS/Include/core_cm4.h **** 876:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Lock Status Register Definitions */ 877:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM 878:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM 879:Drivers/CMSIS/Include/core_cm4.h **** 880:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM 881:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM 882:Drivers/CMSIS/Include/core_cm4.h **** 883:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM 884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM ARM GAS /tmp/ccDEPnZG.s page 17 885:Drivers/CMSIS/Include/core_cm4.h **** 886:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */ 887:Drivers/CMSIS/Include/core_cm4.h **** 888:Drivers/CMSIS/Include/core_cm4.h **** 889:Drivers/CMSIS/Include/core_cm4.h **** /** 890:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 891:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 892:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) 893:Drivers/CMSIS/Include/core_cm4.h **** @{ 894:Drivers/CMSIS/Include/core_cm4.h **** */ 895:Drivers/CMSIS/Include/core_cm4.h **** 896:Drivers/CMSIS/Include/core_cm4.h **** /** 897:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 898:Drivers/CMSIS/Include/core_cm4.h **** */ 899:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 900:Drivers/CMSIS/Include/core_cm4.h **** { 901:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 902:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 903:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 904:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe 905:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 906:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 907:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe 908:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register 909:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 910:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 911:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 912:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; 913:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 914:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 915:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 916:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[1U]; 917:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 918:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 919:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 920:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[1U]; 921:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 922:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 923:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 924:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type; 925:Drivers/CMSIS/Include/core_cm4.h **** 926:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */ 927:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR 928:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR 929:Drivers/CMSIS/Include/core_cm4.h **** 930:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR 931:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR 932:Drivers/CMSIS/Include/core_cm4.h **** 933:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR 934:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR 935:Drivers/CMSIS/Include/core_cm4.h **** 936:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR 937:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR 938:Drivers/CMSIS/Include/core_cm4.h **** 939:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR 940:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR 941:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 18 942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR 943:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR 944:Drivers/CMSIS/Include/core_cm4.h **** 945:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR 946:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR 947:Drivers/CMSIS/Include/core_cm4.h **** 948:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR 949:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR 950:Drivers/CMSIS/Include/core_cm4.h **** 951:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR 952:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR 953:Drivers/CMSIS/Include/core_cm4.h **** 954:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR 955:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR 956:Drivers/CMSIS/Include/core_cm4.h **** 957:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR 958:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR 959:Drivers/CMSIS/Include/core_cm4.h **** 960:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR 961:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR 962:Drivers/CMSIS/Include/core_cm4.h **** 963:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR 964:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR 965:Drivers/CMSIS/Include/core_cm4.h **** 966:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR 967:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR 968:Drivers/CMSIS/Include/core_cm4.h **** 969:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR 970:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR 971:Drivers/CMSIS/Include/core_cm4.h **** 972:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR 973:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR 974:Drivers/CMSIS/Include/core_cm4.h **** 975:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR 976:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR 977:Drivers/CMSIS/Include/core_cm4.h **** 978:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR 979:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR 980:Drivers/CMSIS/Include/core_cm4.h **** 981:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */ 982:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI 983:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI 984:Drivers/CMSIS/Include/core_cm4.h **** 985:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */ 986:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC 987:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC 988:Drivers/CMSIS/Include/core_cm4.h **** 989:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Sleep Count Register Definitions */ 990:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE 991:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE 992:Drivers/CMSIS/Include/core_cm4.h **** 993:Drivers/CMSIS/Include/core_cm4.h **** /* DWT LSU Count Register Definitions */ 994:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU 995:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU 996:Drivers/CMSIS/Include/core_cm4.h **** 997:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */ 998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL ARM GAS /tmp/ccDEPnZG.s page 19 999:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL 1000:Drivers/CMSIS/Include/core_cm4.h **** 1001:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Mask Register Definitions */ 1002:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS 1003:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS 1004:Drivers/CMSIS/Include/core_cm4.h **** 1005:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Function Register Definitions */ 1006:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN 1007:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN 1008:Drivers/CMSIS/Include/core_cm4.h **** 1009:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN 1010:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN 1011:Drivers/CMSIS/Include/core_cm4.h **** 1012:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN 1013:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN 1014:Drivers/CMSIS/Include/core_cm4.h **** 1015:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN 1016:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN 1017:Drivers/CMSIS/Include/core_cm4.h **** 1018:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN 1019:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN 1020:Drivers/CMSIS/Include/core_cm4.h **** 1021:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN 1022:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN 1023:Drivers/CMSIS/Include/core_cm4.h **** 1024:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN 1025:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN 1026:Drivers/CMSIS/Include/core_cm4.h **** 1027:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN 1028:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN 1029:Drivers/CMSIS/Include/core_cm4.h **** 1030:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN 1031:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN 1032:Drivers/CMSIS/Include/core_cm4.h **** 1033:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */ 1034:Drivers/CMSIS/Include/core_cm4.h **** 1035:Drivers/CMSIS/Include/core_cm4.h **** 1036:Drivers/CMSIS/Include/core_cm4.h **** /** 1037:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1038:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) 1039:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Trace Port Interface (TPI) 1040:Drivers/CMSIS/Include/core_cm4.h **** @{ 1041:Drivers/CMSIS/Include/core_cm4.h **** */ 1042:Drivers/CMSIS/Include/core_cm4.h **** 1043:Drivers/CMSIS/Include/core_cm4.h **** /** 1044:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Trace Port Interface Register (TPI). 1045:Drivers/CMSIS/Include/core_cm4.h **** */ 1046:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1047:Drivers/CMSIS/Include/core_cm4.h **** { 1048:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg 1049:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis 1050:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[2U]; 1051:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg 1052:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[55U]; 1053:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * 1054:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[131U]; 1055:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis ARM GAS /tmp/ccDEPnZG.s page 20 1056:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi 1057:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte 1058:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[759U]; 1059:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1060:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1061:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1062:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[1U]; 1063:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1064:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1065:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1066:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[39U]; 1067:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1068:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1069:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED7[8U]; 1070:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1071:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1072:Drivers/CMSIS/Include/core_cm4.h **** } TPI_Type; 1073:Drivers/CMSIS/Include/core_cm4.h **** 1074:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ 1075:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP 1076:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP 1077:Drivers/CMSIS/Include/core_cm4.h **** 1078:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */ 1079:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP 1080:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP 1081:Drivers/CMSIS/Include/core_cm4.h **** 1082:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */ 1083:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS 1084:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS 1085:Drivers/CMSIS/Include/core_cm4.h **** 1086:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS 1087:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS 1088:Drivers/CMSIS/Include/core_cm4.h **** 1089:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS 1090:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS 1091:Drivers/CMSIS/Include/core_cm4.h **** 1092:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS 1093:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS 1094:Drivers/CMSIS/Include/core_cm4.h **** 1095:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */ 1096:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC 1097:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC 1098:Drivers/CMSIS/Include/core_cm4.h **** 1099:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC 1100:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC 1101:Drivers/CMSIS/Include/core_cm4.h **** 1102:Drivers/CMSIS/Include/core_cm4.h **** /* TPI TRIGGER Register Definitions */ 1103:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI 1104:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI 1105:Drivers/CMSIS/Include/core_cm4.h **** 1106:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1107:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF 1108:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF 1109:Drivers/CMSIS/Include/core_cm4.h **** 1110:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF 1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF 1112:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 21 1113:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF 1114:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF 1115:Drivers/CMSIS/Include/core_cm4.h **** 1116:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF 1117:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF 1118:Drivers/CMSIS/Include/core_cm4.h **** 1119:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF 1120:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF 1121:Drivers/CMSIS/Include/core_cm4.h **** 1122:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF 1123:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF 1124:Drivers/CMSIS/Include/core_cm4.h **** 1125:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF 1126:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF 1127:Drivers/CMSIS/Include/core_cm4.h **** 1128:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */ 1129:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA 1130:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA 1131:Drivers/CMSIS/Include/core_cm4.h **** 1132:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA 1133:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA 1134:Drivers/CMSIS/Include/core_cm4.h **** 1135:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1136:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF 1137:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF 1138:Drivers/CMSIS/Include/core_cm4.h **** 1139:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF 1140:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF 1141:Drivers/CMSIS/Include/core_cm4.h **** 1142:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF 1143:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF 1144:Drivers/CMSIS/Include/core_cm4.h **** 1145:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF 1146:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF 1147:Drivers/CMSIS/Include/core_cm4.h **** 1148:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF 1149:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF 1150:Drivers/CMSIS/Include/core_cm4.h **** 1151:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF 1152:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF 1153:Drivers/CMSIS/Include/core_cm4.h **** 1154:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF 1155:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF 1156:Drivers/CMSIS/Include/core_cm4.h **** 1157:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */ 1158:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA 1159:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA 1160:Drivers/CMSIS/Include/core_cm4.h **** 1161:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA 1162:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA 1163:Drivers/CMSIS/Include/core_cm4.h **** 1164:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */ 1165:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC 1166:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC 1167:Drivers/CMSIS/Include/core_cm4.h **** 1168:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */ 1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV ARM GAS /tmp/ccDEPnZG.s page 22 1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV 1171:Drivers/CMSIS/Include/core_cm4.h **** 1172:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV 1173:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV 1174:Drivers/CMSIS/Include/core_cm4.h **** 1175:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV 1176:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV 1177:Drivers/CMSIS/Include/core_cm4.h **** 1178:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV 1179:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV 1180:Drivers/CMSIS/Include/core_cm4.h **** 1181:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV 1182:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV 1183:Drivers/CMSIS/Include/core_cm4.h **** 1184:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV 1185:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV 1186:Drivers/CMSIS/Include/core_cm4.h **** 1187:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVTYPE Register Definitions */ 1188:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV 1189:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV 1190:Drivers/CMSIS/Include/core_cm4.h **** 1191:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV 1192:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV 1193:Drivers/CMSIS/Include/core_cm4.h **** 1194:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */ 1195:Drivers/CMSIS/Include/core_cm4.h **** 1196:Drivers/CMSIS/Include/core_cm4.h **** 1197:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1198:Drivers/CMSIS/Include/core_cm4.h **** /** 1199:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1200:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1201:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Memory Protection Unit (MPU) 1202:Drivers/CMSIS/Include/core_cm4.h **** @{ 1203:Drivers/CMSIS/Include/core_cm4.h **** */ 1204:Drivers/CMSIS/Include/core_cm4.h **** 1205:Drivers/CMSIS/Include/core_cm4.h **** /** 1206:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Memory Protection Unit (MPU). 1207:Drivers/CMSIS/Include/core_cm4.h **** */ 1208:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1209:Drivers/CMSIS/Include/core_cm4.h **** { 1210:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1211:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1212:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1213:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register 1214:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re 1215:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address 1216:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and 1217:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address 1218:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and 1219:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address 1220:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and 1221:Drivers/CMSIS/Include/core_cm4.h **** } MPU_Type; 1222:Drivers/CMSIS/Include/core_cm4.h **** 1223:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_RALIASES 4U 1224:Drivers/CMSIS/Include/core_cm4.h **** 1225:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */ 1226:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU ARM GAS /tmp/ccDEPnZG.s page 23 1227:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU 1228:Drivers/CMSIS/Include/core_cm4.h **** 1229:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU 1230:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU 1231:Drivers/CMSIS/Include/core_cm4.h **** 1232:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU 1233:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU 1234:Drivers/CMSIS/Include/core_cm4.h **** 1235:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Control Register Definitions */ 1236:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU 1237:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU 1238:Drivers/CMSIS/Include/core_cm4.h **** 1239:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU 1240:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU 1241:Drivers/CMSIS/Include/core_cm4.h **** 1242:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU 1243:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU 1244:Drivers/CMSIS/Include/core_cm4.h **** 1245:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Number Register Definitions */ 1246:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU 1247:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU 1248:Drivers/CMSIS/Include/core_cm4.h **** 1249:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Base Address Register Definitions */ 1250:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU 1251:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU 1252:Drivers/CMSIS/Include/core_cm4.h **** 1253:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU 1254:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU 1255:Drivers/CMSIS/Include/core_cm4.h **** 1256:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU 1257:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU 1258:Drivers/CMSIS/Include/core_cm4.h **** 1259:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */ 1260:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU 1261:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU 1262:Drivers/CMSIS/Include/core_cm4.h **** 1263:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU 1264:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU 1265:Drivers/CMSIS/Include/core_cm4.h **** 1266:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU 1267:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU 1268:Drivers/CMSIS/Include/core_cm4.h **** 1269:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU 1270:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU 1271:Drivers/CMSIS/Include/core_cm4.h **** 1272:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Pos 18U /*!< MPU 1273:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU 1274:Drivers/CMSIS/Include/core_cm4.h **** 1275:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Pos 17U /*!< MPU 1276:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU 1277:Drivers/CMSIS/Include/core_cm4.h **** 1278:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Pos 16U /*!< MPU 1279:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU 1280:Drivers/CMSIS/Include/core_cm4.h **** 1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU 1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU 1283:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 24 1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU 1285:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU 1286:Drivers/CMSIS/Include/core_cm4.h **** 1287:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU 1288:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU 1289:Drivers/CMSIS/Include/core_cm4.h **** 1290:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_MPU */ 1291:Drivers/CMSIS/Include/core_cm4.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1292:Drivers/CMSIS/Include/core_cm4.h **** 1293:Drivers/CMSIS/Include/core_cm4.h **** 1294:Drivers/CMSIS/Include/core_cm4.h **** /** 1295:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1296:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) 1297:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Floating Point Unit (FPU) 1298:Drivers/CMSIS/Include/core_cm4.h **** @{ 1299:Drivers/CMSIS/Include/core_cm4.h **** */ 1300:Drivers/CMSIS/Include/core_cm4.h **** 1301:Drivers/CMSIS/Include/core_cm4.h **** /** 1302:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Floating Point Unit (FPU). 1303:Drivers/CMSIS/Include/core_cm4.h **** */ 1304:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1305:Drivers/CMSIS/Include/core_cm4.h **** { 1306:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; 1307:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R 1308:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R 1309:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co 1310:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 1311:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 1312:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 1313:Drivers/CMSIS/Include/core_cm4.h **** } FPU_Type; 1314:Drivers/CMSIS/Include/core_cm4.h **** 1315:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Control Register Definitions */ 1316:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC 1317:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC 1318:Drivers/CMSIS/Include/core_cm4.h **** 1319:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC 1320:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC 1321:Drivers/CMSIS/Include/core_cm4.h **** 1322:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC 1323:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC 1324:Drivers/CMSIS/Include/core_cm4.h **** 1325:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC 1326:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC 1327:Drivers/CMSIS/Include/core_cm4.h **** 1328:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC 1329:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC 1330:Drivers/CMSIS/Include/core_cm4.h **** 1331:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC 1332:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC 1333:Drivers/CMSIS/Include/core_cm4.h **** 1334:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC 1335:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC 1336:Drivers/CMSIS/Include/core_cm4.h **** 1337:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC 1338:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC 1339:Drivers/CMSIS/Include/core_cm4.h **** 1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC ARM GAS /tmp/ccDEPnZG.s page 25 1341:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC 1342:Drivers/CMSIS/Include/core_cm4.h **** 1343:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Address Register Definitions */ 1344:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA 1345:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA 1346:Drivers/CMSIS/Include/core_cm4.h **** 1347:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */ 1348:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS 1349:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS 1350:Drivers/CMSIS/Include/core_cm4.h **** 1351:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS 1352:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS 1353:Drivers/CMSIS/Include/core_cm4.h **** 1354:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS 1355:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS 1356:Drivers/CMSIS/Include/core_cm4.h **** 1357:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS 1358:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS 1359:Drivers/CMSIS/Include/core_cm4.h **** 1360:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */ 1361:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR 1362:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR 1363:Drivers/CMSIS/Include/core_cm4.h **** 1364:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR 1365:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR 1366:Drivers/CMSIS/Include/core_cm4.h **** 1367:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR 1368:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR 1369:Drivers/CMSIS/Include/core_cm4.h **** 1370:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR 1371:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR 1372:Drivers/CMSIS/Include/core_cm4.h **** 1373:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR 1374:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR 1375:Drivers/CMSIS/Include/core_cm4.h **** 1376:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR 1377:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR 1378:Drivers/CMSIS/Include/core_cm4.h **** 1379:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR 1380:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR 1381:Drivers/CMSIS/Include/core_cm4.h **** 1382:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR 1383:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR 1384:Drivers/CMSIS/Include/core_cm4.h **** 1385:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */ 1386:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR 1387:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR 1388:Drivers/CMSIS/Include/core_cm4.h **** 1389:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR 1390:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR 1391:Drivers/CMSIS/Include/core_cm4.h **** 1392:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR 1393:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR 1394:Drivers/CMSIS/Include/core_cm4.h **** 1395:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR 1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR 1397:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 26 1398:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 2 Definitions */ 1399:Drivers/CMSIS/Include/core_cm4.h **** 1400:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR 1401:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR 1402:Drivers/CMSIS/Include/core_cm4.h **** 1403:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_FPU */ 1404:Drivers/CMSIS/Include/core_cm4.h **** 1405:Drivers/CMSIS/Include/core_cm4.h **** 1406:Drivers/CMSIS/Include/core_cm4.h **** /** 1407:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1408:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1409:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Core Debug Registers 1410:Drivers/CMSIS/Include/core_cm4.h **** @{ 1411:Drivers/CMSIS/Include/core_cm4.h **** */ 1412:Drivers/CMSIS/Include/core_cm4.h **** 1413:Drivers/CMSIS/Include/core_cm4.h **** /** 1414:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Core Debug Register (CoreDebug). 1415:Drivers/CMSIS/Include/core_cm4.h **** */ 1416:Drivers/CMSIS/Include/core_cm4.h **** typedef struct 1417:Drivers/CMSIS/Include/core_cm4.h **** { 1418:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status 1419:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg 1420:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe 1421:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont 1422:Drivers/CMSIS/Include/core_cm4.h **** } CoreDebug_Type; 1423:Drivers/CMSIS/Include/core_cm4.h **** 1424:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */ 1425:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core 1426:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core 1427:Drivers/CMSIS/Include/core_cm4.h **** 1428:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core 1429:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core 1430:Drivers/CMSIS/Include/core_cm4.h **** 1431:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core 1432:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core 1433:Drivers/CMSIS/Include/core_cm4.h **** 1434:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core 1435:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core 1436:Drivers/CMSIS/Include/core_cm4.h **** 1437:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core 1438:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core 1439:Drivers/CMSIS/Include/core_cm4.h **** 1440:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core 1441:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core 1442:Drivers/CMSIS/Include/core_cm4.h **** 1443:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core 1444:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core 1445:Drivers/CMSIS/Include/core_cm4.h **** 1446:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core 1447:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core 1448:Drivers/CMSIS/Include/core_cm4.h **** 1449:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core 1450:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core 1451:Drivers/CMSIS/Include/core_cm4.h **** 1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core 1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core 1454:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 27 1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core 1456:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core 1457:Drivers/CMSIS/Include/core_cm4.h **** 1458:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core 1459:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core 1460:Drivers/CMSIS/Include/core_cm4.h **** 1461:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Core Register Selector Register Definitions */ 1462:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core 1463:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core 1464:Drivers/CMSIS/Include/core_cm4.h **** 1465:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core 1466:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core 1467:Drivers/CMSIS/Include/core_cm4.h **** 1468:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */ 1469:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core 1470:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core 1471:Drivers/CMSIS/Include/core_cm4.h **** 1472:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core 1473:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core 1474:Drivers/CMSIS/Include/core_cm4.h **** 1475:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core 1476:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core 1477:Drivers/CMSIS/Include/core_cm4.h **** 1478:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core 1479:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core 1480:Drivers/CMSIS/Include/core_cm4.h **** 1481:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core 1482:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core 1483:Drivers/CMSIS/Include/core_cm4.h **** 1484:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core 1485:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core 1486:Drivers/CMSIS/Include/core_cm4.h **** 1487:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core 1488:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core 1489:Drivers/CMSIS/Include/core_cm4.h **** 1490:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core 1491:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core 1492:Drivers/CMSIS/Include/core_cm4.h **** 1493:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core 1494:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core 1495:Drivers/CMSIS/Include/core_cm4.h **** 1496:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core 1497:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core 1498:Drivers/CMSIS/Include/core_cm4.h **** 1499:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core 1500:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core 1501:Drivers/CMSIS/Include/core_cm4.h **** 1502:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core 1503:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core 1504:Drivers/CMSIS/Include/core_cm4.h **** 1505:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core 1506:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core 1507:Drivers/CMSIS/Include/core_cm4.h **** 1508:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */ 1509:Drivers/CMSIS/Include/core_cm4.h **** 1510:Drivers/CMSIS/Include/core_cm4.h **** 1511:Drivers/CMSIS/Include/core_cm4.h **** /** ARM GAS /tmp/ccDEPnZG.s page 28 1512:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1513:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_bitfield Core register bit field macros 1514:Drivers/CMSIS/Include/core_cm4.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1515:Drivers/CMSIS/Include/core_cm4.h **** @{ 1516:Drivers/CMSIS/Include/core_cm4.h **** */ 1517:Drivers/CMSIS/Include/core_cm4.h **** 1518:Drivers/CMSIS/Include/core_cm4.h **** /** 1519:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a bit field value for use in a register bit range. 1520:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. 1521:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1522:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted value. 1523:Drivers/CMSIS/Include/core_cm4.h **** */ 1524:Drivers/CMSIS/Include/core_cm4.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1525:Drivers/CMSIS/Include/core_cm4.h **** 1526:Drivers/CMSIS/Include/core_cm4.h **** /** 1527:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a register value to extract a bit filed value. 1528:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. 1529:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1530:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted bit field value. 1531:Drivers/CMSIS/Include/core_cm4.h **** */ 1532:Drivers/CMSIS/Include/core_cm4.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1533:Drivers/CMSIS/Include/core_cm4.h **** 1534:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */ 1535:Drivers/CMSIS/Include/core_cm4.h **** 1536:Drivers/CMSIS/Include/core_cm4.h **** 1537:Drivers/CMSIS/Include/core_cm4.h **** /** 1538:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register 1539:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_base Core Definitions 1540:Drivers/CMSIS/Include/core_cm4.h **** \brief Definitions for base addresses, unions, and structures. 1541:Drivers/CMSIS/Include/core_cm4.h **** @{ 1542:Drivers/CMSIS/Include/core_cm4.h **** */ 1543:Drivers/CMSIS/Include/core_cm4.h **** 1544:Drivers/CMSIS/Include/core_cm4.h **** /* Memory mapping of Core Hardware */ 1545:Drivers/CMSIS/Include/core_cm4.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas 1546:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1547:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1548:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1549:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address 1550:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1551:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas 1553:Drivers/CMSIS/Include/core_cm4.h **** 1554:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register 1555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct 1556:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st 1557:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc 1558:Drivers/CMSIS/Include/core_cm4.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct 1559:Drivers/CMSIS/Include/core_cm4.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct 1560:Drivers/CMSIS/Include/core_cm4.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct 1561:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration 1562:Drivers/CMSIS/Include/core_cm4.h **** 1563:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1564:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * 1565:Drivers/CMSIS/Include/core_cm4.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * 1566:Drivers/CMSIS/Include/core_cm4.h **** #endif 1567:Drivers/CMSIS/Include/core_cm4.h **** 1568:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ ARM GAS /tmp/ccDEPnZG.s page 29 1569:Drivers/CMSIS/Include/core_cm4.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1570:Drivers/CMSIS/Include/core_cm4.h **** 1571:Drivers/CMSIS/Include/core_cm4.h **** /*@} */ 1572:Drivers/CMSIS/Include/core_cm4.h **** 1573:Drivers/CMSIS/Include/core_cm4.h **** 1574:Drivers/CMSIS/Include/core_cm4.h **** 1575:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* 1576:Drivers/CMSIS/Include/core_cm4.h **** * Hardware Abstraction Layer 1577:Drivers/CMSIS/Include/core_cm4.h **** Core Function Interface contains: 1578:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Functions 1579:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Functions 1580:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Functions 1581:Drivers/CMSIS/Include/core_cm4.h **** - Core Register Access Functions 1582:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ 1583:Drivers/CMSIS/Include/core_cm4.h **** /** 1584:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1585:Drivers/CMSIS/Include/core_cm4.h **** */ 1586:Drivers/CMSIS/Include/core_cm4.h **** 1587:Drivers/CMSIS/Include/core_cm4.h **** 1588:Drivers/CMSIS/Include/core_cm4.h **** 1589:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## NVIC functions #################################### */ 1590:Drivers/CMSIS/Include/core_cm4.h **** /** 1591:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface 1592:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1593:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that manage interrupts and exceptions via the NVIC. 1594:Drivers/CMSIS/Include/core_cm4.h **** @{ 1595:Drivers/CMSIS/Include/core_cm4.h **** */ 1596:Drivers/CMSIS/Include/core_cm4.h **** 1597:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_NVIC_VIRTUAL 1598:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1599:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1600:Drivers/CMSIS/Include/core_cm4.h **** #endif 1601:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1602:Drivers/CMSIS/Include/core_cm4.h **** #else 1603:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1604:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1605:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ 1606:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1607:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ 1608:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1609:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1610:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1611:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetActive __NVIC_GetActive 1612:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriority __NVIC_SetPriority 1613:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriority __NVIC_GetPriority 1614:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SystemReset __NVIC_SystemReset 1615:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */ 1616:Drivers/CMSIS/Include/core_cm4.h **** 1617:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL 1618:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1619:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1620:Drivers/CMSIS/Include/core_cm4.h **** #endif 1621:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1622:Drivers/CMSIS/Include/core_cm4.h **** #else 1623:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetVector __NVIC_SetVector 1624:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetVector __NVIC_GetVector 1625:Drivers/CMSIS/Include/core_cm4.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ ARM GAS /tmp/ccDEPnZG.s page 30 1626:Drivers/CMSIS/Include/core_cm4.h **** 1627:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_USER_IRQ_OFFSET 16 1628:Drivers/CMSIS/Include/core_cm4.h **** 1629:Drivers/CMSIS/Include/core_cm4.h **** 1630:Drivers/CMSIS/Include/core_cm4.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ 1631:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret 1632:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu 1633:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu 1634:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret 1635:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu 1636:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu 1637:Drivers/CMSIS/Include/core_cm4.h **** 1638:Drivers/CMSIS/Include/core_cm4.h **** 1639:Drivers/CMSIS/Include/core_cm4.h **** /** 1640:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Priority Grouping 1641:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority grouping field using the required unlock sequence. 1642:Drivers/CMSIS/Include/core_cm4.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1643:Drivers/CMSIS/Include/core_cm4.h **** Only values from 0..7 are used. 1644:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available 1645:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1646:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Priority grouping field. 1647:Drivers/CMSIS/Include/core_cm4.h **** */ 1648:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1649:Drivers/CMSIS/Include/core_cm4.h **** { 1650:Drivers/CMSIS/Include/core_cm4.h **** uint32_t reg_value; 1651:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a 1652:Drivers/CMSIS/Include/core_cm4.h **** 1653:Drivers/CMSIS/Include/core_cm4.h **** reg_value = SCB->AIRCR; /* read old register 1654:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 1655:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | 1656:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1657:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a 1658:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; 1659:Drivers/CMSIS/Include/core_cm4.h **** } 1660:Drivers/CMSIS/Include/core_cm4.h **** 1661:Drivers/CMSIS/Include/core_cm4.h **** 1662:Drivers/CMSIS/Include/core_cm4.h **** /** 1663:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Priority Grouping 1664:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. 1665:Drivers/CMSIS/Include/core_cm4.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1666:Drivers/CMSIS/Include/core_cm4.h **** */ 1667:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1668:Drivers/CMSIS/Include/core_cm4.h **** { 1669:Drivers/CMSIS/Include/core_cm4.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 1670:Drivers/CMSIS/Include/core_cm4.h **** } 1671:Drivers/CMSIS/Include/core_cm4.h **** 1672:Drivers/CMSIS/Include/core_cm4.h **** 1673:Drivers/CMSIS/Include/core_cm4.h **** /** 1674:Drivers/CMSIS/Include/core_cm4.h **** \brief Enable Interrupt 1675:Drivers/CMSIS/Include/core_cm4.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 1676:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1677:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1678:Drivers/CMSIS/Include/core_cm4.h **** */ 1679:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1680:Drivers/CMSIS/Include/core_cm4.h **** { 30 .loc 2 1680 1 view -0 31 .cfi_startproc ARM GAS /tmp/ccDEPnZG.s page 31 32 @ args = 0, pretend = 0, frame = 0 33 @ frame_needed = 0, uses_anonymous_args = 0 34 @ link register save eliminated. 1681:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 35 .loc 2 1681 3 view .LVU1 36 .loc 2 1681 6 is_stmt 0 view .LVU2 37 0000 0028 cmp r0, #0 38 .loc 2 1681 6 view .LVU3 39 0002 07DB blt .L1 1682:Drivers/CMSIS/Include/core_cm4.h **** { 1683:Drivers/CMSIS/Include/core_cm4.h **** __COMPILER_BARRIER(); 40 .loc 2 1683 5 is_stmt 1 view .LVU4 1684:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 41 .loc 2 1684 5 view .LVU5 42 .loc 2 1684 81 is_stmt 0 view .LVU6 43 0004 00F01F02 and r2, r0, #31 44 .loc 2 1684 34 view .LVU7 45 0008 4009 lsrs r0, r0, #5 46 .LVL1: 47 .loc 2 1684 45 view .LVU8 48 000a 0123 movs r3, #1 49 000c 9340 lsls r3, r3, r2 50 .loc 2 1684 43 view .LVU9 51 000e 024A ldr r2, .L3 52 0010 42F82030 str r3, [r2, r0, lsl #2] 1685:Drivers/CMSIS/Include/core_cm4.h **** __COMPILER_BARRIER(); 53 .loc 2 1685 5 is_stmt 1 view .LVU10 54 .L1: 1686:Drivers/CMSIS/Include/core_cm4.h **** } 1687:Drivers/CMSIS/Include/core_cm4.h **** } 55 .loc 2 1687 1 is_stmt 0 view .LVU11 56 0014 7047 bx lr 57 .L4: 58 0016 00BF .align 2 59 .L3: 60 0018 00E100E0 .word -536813312 61 .cfi_endproc 62 .LFE106: 64 .section .text.__NVIC_DisableIRQ,"ax",%progbits 65 .align 1 66 .syntax unified 67 .thumb 68 .thumb_func 70 __NVIC_DisableIRQ: 71 .LVL2: 72 .LFB108: 1688:Drivers/CMSIS/Include/core_cm4.h **** 1689:Drivers/CMSIS/Include/core_cm4.h **** 1690:Drivers/CMSIS/Include/core_cm4.h **** /** 1691:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Enable status 1692:Drivers/CMSIS/Include/core_cm4.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1693:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1694:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt is not enabled. 1695:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt is enabled. 1696:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1697:Drivers/CMSIS/Include/core_cm4.h **** */ 1698:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) ARM GAS /tmp/ccDEPnZG.s page 32 1699:Drivers/CMSIS/Include/core_cm4.h **** { 1700:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1701:Drivers/CMSIS/Include/core_cm4.h **** { 1702:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1703:Drivers/CMSIS/Include/core_cm4.h **** } 1704:Drivers/CMSIS/Include/core_cm4.h **** else 1705:Drivers/CMSIS/Include/core_cm4.h **** { 1706:Drivers/CMSIS/Include/core_cm4.h **** return(0U); 1707:Drivers/CMSIS/Include/core_cm4.h **** } 1708:Drivers/CMSIS/Include/core_cm4.h **** } 1709:Drivers/CMSIS/Include/core_cm4.h **** 1710:Drivers/CMSIS/Include/core_cm4.h **** 1711:Drivers/CMSIS/Include/core_cm4.h **** /** 1712:Drivers/CMSIS/Include/core_cm4.h **** \brief Disable Interrupt 1713:Drivers/CMSIS/Include/core_cm4.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. 1714:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1715:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1716:Drivers/CMSIS/Include/core_cm4.h **** */ 1717:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1718:Drivers/CMSIS/Include/core_cm4.h **** { 73 .loc 2 1718 1 is_stmt 1 view -0 74 .cfi_startproc 75 @ args = 0, pretend = 0, frame = 0 76 @ frame_needed = 0, uses_anonymous_args = 0 77 @ link register save eliminated. 1719:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 78 .loc 2 1719 3 view .LVU13 79 .loc 2 1719 6 is_stmt 0 view .LVU14 80 0000 0028 cmp r0, #0 81 .loc 2 1719 6 view .LVU15 82 0002 0CDB blt .L5 1720:Drivers/CMSIS/Include/core_cm4.h **** { 1721:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 83 .loc 2 1721 5 is_stmt 1 view .LVU16 84 .loc 2 1721 81 is_stmt 0 view .LVU17 85 0004 00F01F02 and r2, r0, #31 86 .loc 2 1721 34 view .LVU18 87 0008 4009 lsrs r0, r0, #5 88 .LVL3: 89 .loc 2 1721 45 view .LVU19 90 000a 0123 movs r3, #1 91 000c 9340 lsls r3, r3, r2 92 .loc 2 1721 43 view .LVU20 93 000e 2030 adds r0, r0, #32 94 0010 034A ldr r2, .L7 95 0012 42F82030 str r3, [r2, r0, lsl #2] 1722:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); 96 .loc 2 1722 5 is_stmt 1 view .LVU21 97 .LBB36: 98 .LBI36: 99 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ ARM GAS /tmp/ccDEPnZG.s page 33 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccDEPnZG.s page 34 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ ARM GAS /tmp/ccDEPnZG.s page 35 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE ARM GAS /tmp/ccDEPnZG.s page 36 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 189:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 195:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 197:Drivers/CMSIS/Include/cmsis_gcc.h **** { 198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 199:Drivers/CMSIS/Include/cmsis_gcc.h **** } 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 206:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 208:Drivers/CMSIS/Include/cmsis_gcc.h **** { 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** } 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 217:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 219:Drivers/CMSIS/Include/cmsis_gcc.h **** { 220:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 222:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 223:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** } 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccDEPnZG.s page 37 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { 250:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 251:Drivers/CMSIS/Include/cmsis_gcc.h **** } 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 259:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 261:Drivers/CMSIS/Include/cmsis_gcc.h **** { 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 263:Drivers/CMSIS/Include/cmsis_gcc.h **** } 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 268:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 271:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 273:Drivers/CMSIS/Include/cmsis_gcc.h **** { 274:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 277:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 278:Drivers/CMSIS/Include/cmsis_gcc.h **** } 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 284:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 285:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 287:Drivers/CMSIS/Include/cmsis_gcc.h **** { 288:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 290:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 291:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); ARM GAS /tmp/ccDEPnZG.s page 38 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 299:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 301:Drivers/CMSIS/Include/cmsis_gcc.h **** { 302:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 304:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 305:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** } 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { 316:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 318:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 319:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 320:Drivers/CMSIS/Include/cmsis_gcc.h **** } 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 326:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 328:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 330:Drivers/CMSIS/Include/cmsis_gcc.h **** { 331:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 335:Drivers/CMSIS/Include/cmsis_gcc.h **** } 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 343:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 345:Drivers/CMSIS/Include/cmsis_gcc.h **** { 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 347:Drivers/CMSIS/Include/cmsis_gcc.h **** } 348:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccDEPnZG.s page 39 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 359:Drivers/CMSIS/Include/cmsis_gcc.h **** } 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 365:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 367:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 369:Drivers/CMSIS/Include/cmsis_gcc.h **** { 370:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 374:Drivers/CMSIS/Include/cmsis_gcc.h **** } 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 381:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 382:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 384:Drivers/CMSIS/Include/cmsis_gcc.h **** { 385:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 387:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 389:Drivers/CMSIS/Include/cmsis_gcc.h **** } 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 396:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 397:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 399:Drivers/CMSIS/Include/cmsis_gcc.h **** { 400:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 401:Drivers/CMSIS/Include/cmsis_gcc.h **** } 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccDEPnZG.s page 40 406:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 407:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 409:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 411:Drivers/CMSIS/Include/cmsis_gcc.h **** { 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 413:Drivers/CMSIS/Include/cmsis_gcc.h **** } 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 419:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 422:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 424:Drivers/CMSIS/Include/cmsis_gcc.h **** { 425:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 427:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 428:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 429:Drivers/CMSIS/Include/cmsis_gcc.h **** } 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 433:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 436:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 438:Drivers/CMSIS/Include/cmsis_gcc.h **** { 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 440:Drivers/CMSIS/Include/cmsis_gcc.h **** } 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 448:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 450:Drivers/CMSIS/Include/cmsis_gcc.h **** { 451:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 453:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 454:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 455:Drivers/CMSIS/Include/cmsis_gcc.h **** } 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 460:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 461:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 462:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value ARM GAS /tmp/ccDEPnZG.s page 41 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 465:Drivers/CMSIS/Include/cmsis_gcc.h **** { 466:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 468:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 469:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 470:Drivers/CMSIS/Include/cmsis_gcc.h **** } 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 475:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 476:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 477:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 478:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 480:Drivers/CMSIS/Include/cmsis_gcc.h **** { 481:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 499:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 500:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 502:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 504:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 505:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 507:Drivers/CMSIS/Include/cmsis_gcc.h **** { 508:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 509:Drivers/CMSIS/Include/cmsis_gcc.h **** } 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 513:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 515:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 516:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 518:Drivers/CMSIS/Include/cmsis_gcc.h **** { 519:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); ARM GAS /tmp/ccDEPnZG.s page 42 520:Drivers/CMSIS/Include/cmsis_gcc.h **** } 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 526:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 527:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 529:Drivers/CMSIS/Include/cmsis_gcc.h **** { 530:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 532:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 534:Drivers/CMSIS/Include/cmsis_gcc.h **** } 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 541:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 542:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 544:Drivers/CMSIS/Include/cmsis_gcc.h **** { 545:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 547:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 549:Drivers/CMSIS/Include/cmsis_gcc.h **** } 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 557:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 559:Drivers/CMSIS/Include/cmsis_gcc.h **** { 560:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 561:Drivers/CMSIS/Include/cmsis_gcc.h **** } 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 568:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 569:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 571:Drivers/CMSIS/Include/cmsis_gcc.h **** { 572:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 573:Drivers/CMSIS/Include/cmsis_gcc.h **** } 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 576:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccDEPnZG.s page 43 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 578:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 579:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 580:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 581:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 582:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 584:Drivers/CMSIS/Include/cmsis_gcc.h **** { 585:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 586:Drivers/CMSIS/Include/cmsis_gcc.h **** } 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 592:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 593:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 595:Drivers/CMSIS/Include/cmsis_gcc.h **** { 596:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 598:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 599:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 600:Drivers/CMSIS/Include/cmsis_gcc.h **** } 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 608:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 610:Drivers/CMSIS/Include/cmsis_gcc.h **** { 611:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 614:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 615:Drivers/CMSIS/Include/cmsis_gcc.h **** } 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 620:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 621:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 622:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 623:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 625:Drivers/CMSIS/Include/cmsis_gcc.h **** { 626:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 627:Drivers/CMSIS/Include/cmsis_gcc.h **** } 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 632:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 633:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. ARM GAS /tmp/ccDEPnZG.s page 44 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 635:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 637:Drivers/CMSIS/Include/cmsis_gcc.h **** { 638:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 639:Drivers/CMSIS/Include/cmsis_gcc.h **** } 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 644:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 654:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 657:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 658:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 660:Drivers/CMSIS/Include/cmsis_gcc.h **** { 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 663:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 664:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 666:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 668:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 675:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 676:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 678:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 679:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 680:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 682:Drivers/CMSIS/Include/cmsis_gcc.h **** { 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 684:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 685:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 687:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 688:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 689:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccDEPnZG.s page 45 691:Drivers/CMSIS/Include/cmsis_gcc.h **** } 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 696:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 698:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 699:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 700:Drivers/CMSIS/Include/cmsis_gcc.h **** 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 703:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** { 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 708:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 709:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 711:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 713:Drivers/CMSIS/Include/cmsis_gcc.h **** } 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 718:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 728:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 729:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 731:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 733:Drivers/CMSIS/Include/cmsis_gcc.h **** } 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 738:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 739:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccDEPnZG.s page 46 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 749:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 750:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 751:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 753:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 754:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 755:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 757:Drivers/CMSIS/Include/cmsis_gcc.h **** } 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 763:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 764:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 766:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 767:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 768:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** { 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 773:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 775:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 776:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 777:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 779:Drivers/CMSIS/Include/cmsis_gcc.h **** } 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 784:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 785:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 786:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 787:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 797:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 799:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 801:Drivers/CMSIS/Include/cmsis_gcc.h **** } 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) ARM GAS /tmp/ccDEPnZG.s page 47 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 806:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 807:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 808:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 811:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 812:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 814:Drivers/CMSIS/Include/cmsis_gcc.h **** { 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 816:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 817:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 821:Drivers/CMSIS/Include/cmsis_gcc.h **** } 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 830:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 831:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 832:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 834:Drivers/CMSIS/Include/cmsis_gcc.h **** { 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 840:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 841:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 843:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 846:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 849:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 851:Drivers/CMSIS/Include/cmsis_gcc.h **** } 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 857:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 858:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 860:Drivers/CMSIS/Include/cmsis_gcc.h **** { 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ ARM GAS /tmp/ccDEPnZG.s page 48 862:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 866:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 869:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 872:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 874:Drivers/CMSIS/Include/cmsis_gcc.h **** } 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 882:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 883:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 888:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 902:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 906:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 907:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 908:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 915:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 916:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 918:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccDEPnZG.s page 49 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 930:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 931:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 932:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 934:Drivers/CMSIS/Include/cmsis_gcc.h **** { 935:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 936:Drivers/CMSIS/Include/cmsis_gcc.h **** } 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 941:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 942:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 943:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 100 .loc 3 944 27 view .LVU22 101 .LBB37: 945:Drivers/CMSIS/Include/cmsis_gcc.h **** { 946:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 102 .loc 3 946 3 view .LVU23 103 .syntax unified 104 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 105 0016 BFF34F8F dsb 0xF 106 @ 0 "" 2 107 .thumb 108 .syntax unified 109 .LBE37: 110 .LBE36: 1723:Drivers/CMSIS/Include/core_cm4.h **** __ISB(); 111 .loc 2 1723 5 view .LVU24 112 .LBB38: 113 .LBI38: 933:Drivers/CMSIS/Include/cmsis_gcc.h **** { 114 .loc 3 933 27 view .LVU25 115 .LBB39: 935:Drivers/CMSIS/Include/cmsis_gcc.h **** } 116 .loc 3 935 3 view .LVU26 117 .syntax unified 118 @ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 119 001a BFF36F8F isb 0xF 120 @ 0 "" 2 121 .thumb 122 .syntax unified 123 .L5: 124 .LBE39: 125 .LBE38: ARM GAS /tmp/ccDEPnZG.s page 50 1724:Drivers/CMSIS/Include/core_cm4.h **** } 1725:Drivers/CMSIS/Include/core_cm4.h **** } 126 .loc 2 1725 1 is_stmt 0 view .LVU27 127 001e 7047 bx lr 128 .L8: 129 .align 2 130 .L7: 131 0020 00E100E0 .word -536813312 132 .cfi_endproc 133 .LFE108: 135 .section .text.__NVIC_SetPriority,"ax",%progbits 136 .align 1 137 .syntax unified 138 .thumb 139 .thumb_func 141 __NVIC_SetPriority: 142 .LVL4: 143 .LFB113: 1726:Drivers/CMSIS/Include/core_cm4.h **** 1727:Drivers/CMSIS/Include/core_cm4.h **** 1728:Drivers/CMSIS/Include/core_cm4.h **** /** 1729:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Pending Interrupt 1730:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe 1731:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1732:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not pending. 1733:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is pending. 1734:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1735:Drivers/CMSIS/Include/core_cm4.h **** */ 1736:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1737:Drivers/CMSIS/Include/core_cm4.h **** { 1738:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1739:Drivers/CMSIS/Include/core_cm4.h **** { 1740:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1741:Drivers/CMSIS/Include/core_cm4.h **** } 1742:Drivers/CMSIS/Include/core_cm4.h **** else 1743:Drivers/CMSIS/Include/core_cm4.h **** { 1744:Drivers/CMSIS/Include/core_cm4.h **** return(0U); 1745:Drivers/CMSIS/Include/core_cm4.h **** } 1746:Drivers/CMSIS/Include/core_cm4.h **** } 1747:Drivers/CMSIS/Include/core_cm4.h **** 1748:Drivers/CMSIS/Include/core_cm4.h **** 1749:Drivers/CMSIS/Include/core_cm4.h **** /** 1750:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Pending Interrupt 1751:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1752:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1753:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1754:Drivers/CMSIS/Include/core_cm4.h **** */ 1755:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1756:Drivers/CMSIS/Include/core_cm4.h **** { 1757:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1758:Drivers/CMSIS/Include/core_cm4.h **** { 1759:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1760:Drivers/CMSIS/Include/core_cm4.h **** } 1761:Drivers/CMSIS/Include/core_cm4.h **** } 1762:Drivers/CMSIS/Include/core_cm4.h **** 1763:Drivers/CMSIS/Include/core_cm4.h **** 1764:Drivers/CMSIS/Include/core_cm4.h **** /** ARM GAS /tmp/ccDEPnZG.s page 51 1765:Drivers/CMSIS/Include/core_cm4.h **** \brief Clear Pending Interrupt 1766:Drivers/CMSIS/Include/core_cm4.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1767:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1768:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1769:Drivers/CMSIS/Include/core_cm4.h **** */ 1770:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1771:Drivers/CMSIS/Include/core_cm4.h **** { 1772:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1773:Drivers/CMSIS/Include/core_cm4.h **** { 1774:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1775:Drivers/CMSIS/Include/core_cm4.h **** } 1776:Drivers/CMSIS/Include/core_cm4.h **** } 1777:Drivers/CMSIS/Include/core_cm4.h **** 1778:Drivers/CMSIS/Include/core_cm4.h **** 1779:Drivers/CMSIS/Include/core_cm4.h **** /** 1780:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Active Interrupt 1781:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific 1782:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. 1783:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not active. 1784:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is active. 1785:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. 1786:Drivers/CMSIS/Include/core_cm4.h **** */ 1787:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1788:Drivers/CMSIS/Include/core_cm4.h **** { 1789:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 1790:Drivers/CMSIS/Include/core_cm4.h **** { 1791:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) 1792:Drivers/CMSIS/Include/core_cm4.h **** } 1793:Drivers/CMSIS/Include/core_cm4.h **** else 1794:Drivers/CMSIS/Include/core_cm4.h **** { 1795:Drivers/CMSIS/Include/core_cm4.h **** return(0U); 1796:Drivers/CMSIS/Include/core_cm4.h **** } 1797:Drivers/CMSIS/Include/core_cm4.h **** } 1798:Drivers/CMSIS/Include/core_cm4.h **** 1799:Drivers/CMSIS/Include/core_cm4.h **** 1800:Drivers/CMSIS/Include/core_cm4.h **** /** 1801:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Priority 1802:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority of a device specific interrupt or a processor exception. 1803:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1804:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1805:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. 1806:Drivers/CMSIS/Include/core_cm4.h **** \param [in] priority Priority to set. 1807:Drivers/CMSIS/Include/core_cm4.h **** \note The priority cannot be set for every processor exception. 1808:Drivers/CMSIS/Include/core_cm4.h **** */ 1809:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1810:Drivers/CMSIS/Include/core_cm4.h **** { 144 .loc 2 1810 1 is_stmt 1 view -0 145 .cfi_startproc 146 @ args = 0, pretend = 0, frame = 0 147 @ frame_needed = 0, uses_anonymous_args = 0 148 @ link register save eliminated. 1811:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 149 .loc 2 1811 3 view .LVU29 150 .loc 2 1811 6 is_stmt 0 view .LVU30 151 0000 0028 cmp r0, #0 152 .loc 2 1811 6 view .LVU31 153 0002 08DB blt .L10 ARM GAS /tmp/ccDEPnZG.s page 52 1812:Drivers/CMSIS/Include/core_cm4.h **** { 1813:Drivers/CMSIS/Include/core_cm4.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u 154 .loc 2 1813 5 is_stmt 1 view .LVU32 155 .loc 2 1813 48 is_stmt 0 view .LVU33 156 0004 0901 lsls r1, r1, #4 157 .LVL5: 158 .loc 2 1813 48 view .LVU34 159 0006 C9B2 uxtb r1, r1 160 .loc 2 1813 46 view .LVU35 161 0008 00F16040 add r0, r0, #-536870912 162 .LVL6: 163 .loc 2 1813 46 view .LVU36 164 000c 00F56140 add r0, r0, #57600 165 .LVL7: 166 .loc 2 1813 46 view .LVU37 167 0010 80F80013 strb r1, [r0, #768] 168 0014 7047 bx lr 169 .LVL8: 170 .L10: 1814:Drivers/CMSIS/Include/core_cm4.h **** } 1815:Drivers/CMSIS/Include/core_cm4.h **** else 1816:Drivers/CMSIS/Include/core_cm4.h **** { 1817:Drivers/CMSIS/Include/core_cm4.h **** SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u 171 .loc 2 1817 5 is_stmt 1 view .LVU38 172 .loc 2 1817 32 is_stmt 0 view .LVU39 173 0016 00F00F00 and r0, r0, #15 174 .LVL9: 175 .loc 2 1817 48 view .LVU40 176 001a 0901 lsls r1, r1, #4 177 .LVL10: 178 .loc 2 1817 48 view .LVU41 179 001c C9B2 uxtb r1, r1 180 .loc 2 1817 46 view .LVU42 181 001e 014B ldr r3, .L12 182 0020 1954 strb r1, [r3, r0] 1818:Drivers/CMSIS/Include/core_cm4.h **** } 1819:Drivers/CMSIS/Include/core_cm4.h **** } 183 .loc 2 1819 1 view .LVU43 184 0022 7047 bx lr 185 .L13: 186 .align 2 187 .L12: 188 0024 14ED00E0 .word -536810220 189 .cfi_endproc 190 .LFE113: 192 .section .text.__NVIC_GetPriority,"ax",%progbits 193 .align 1 194 .syntax unified 195 .thumb 196 .thumb_func 198 __NVIC_GetPriority: 199 .LVL11: 200 .LFB114: 1820:Drivers/CMSIS/Include/core_cm4.h **** 1821:Drivers/CMSIS/Include/core_cm4.h **** 1822:Drivers/CMSIS/Include/core_cm4.h **** /** 1823:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Priority ARM GAS /tmp/ccDEPnZG.s page 53 1824:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority of a device specific interrupt or a processor exception. 1825:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1826:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1827:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. 1828:Drivers/CMSIS/Include/core_cm4.h **** \return Interrupt Priority. 1829:Drivers/CMSIS/Include/core_cm4.h **** Value is aligned automatically to the implemented priority bits of the microc 1830:Drivers/CMSIS/Include/core_cm4.h **** */ 1831:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1832:Drivers/CMSIS/Include/core_cm4.h **** { 201 .loc 2 1832 1 is_stmt 1 view -0 202 .cfi_startproc 203 @ args = 0, pretend = 0, frame = 0 204 @ frame_needed = 0, uses_anonymous_args = 0 205 @ link register save eliminated. 1833:Drivers/CMSIS/Include/core_cm4.h **** 1834:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) 206 .loc 2 1834 3 view .LVU45 207 .loc 2 1834 6 is_stmt 0 view .LVU46 208 0000 0028 cmp r0, #0 209 .loc 2 1834 6 view .LVU47 210 0002 07DB blt .L15 1835:Drivers/CMSIS/Include/core_cm4.h **** { 1836:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 211 .loc 2 1836 5 is_stmt 1 view .LVU48 212 .loc 2 1836 31 is_stmt 0 view .LVU49 213 0004 00F16040 add r0, r0, #-536870912 214 .LVL12: 215 .loc 2 1836 31 view .LVU50 216 0008 00F56140 add r0, r0, #57600 217 .LVL13: 218 .loc 2 1836 31 view .LVU51 219 000c 90F80003 ldrb r0, [r0, #768] @ zero_extendqisi2 220 .LVL14: 221 .loc 2 1836 64 view .LVU52 222 0010 0009 lsrs r0, r0, #4 223 0012 7047 bx lr 224 .L15: 1837:Drivers/CMSIS/Include/core_cm4.h **** } 1838:Drivers/CMSIS/Include/core_cm4.h **** else 1839:Drivers/CMSIS/Include/core_cm4.h **** { 1840:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 225 .loc 2 1840 5 is_stmt 1 view .LVU53 226 .loc 2 1840 50 is_stmt 0 view .LVU54 227 0014 00F00F00 and r0, r0, #15 228 .loc 2 1840 31 view .LVU55 229 0018 014B ldr r3, .L17 230 001a 185C ldrb r0, [r3, r0] @ zero_extendqisi2 231 .loc 2 1840 64 view .LVU56 232 001c 0009 lsrs r0, r0, #4 1841:Drivers/CMSIS/Include/core_cm4.h **** } 1842:Drivers/CMSIS/Include/core_cm4.h **** } 233 .loc 2 1842 1 view .LVU57 234 001e 7047 bx lr 235 .L18: 236 .align 2 237 .L17: 238 0020 14ED00E0 .word -536810220 ARM GAS /tmp/ccDEPnZG.s page 54 239 .cfi_endproc 240 .LFE114: 242 .section .text.NVIC_EncodePriority,"ax",%progbits 243 .align 1 244 .syntax unified 245 .thumb 246 .thumb_func 248 NVIC_EncodePriority: 249 .LVL15: 250 .LFB115: 1843:Drivers/CMSIS/Include/core_cm4.h **** 1844:Drivers/CMSIS/Include/core_cm4.h **** 1845:Drivers/CMSIS/Include/core_cm4.h **** /** 1846:Drivers/CMSIS/Include/core_cm4.h **** \brief Encode Priority 1847:Drivers/CMSIS/Include/core_cm4.h **** \details Encodes the priority for an interrupt with the given priority group, 1848:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value, and subpriority value. 1849:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available 1850:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1851:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. 1852:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). 1853:Drivers/CMSIS/Include/core_cm4.h **** \param [in] SubPriority Subpriority value (starting from 0). 1854:Drivers/CMSIS/Include/core_cm4.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP 1855:Drivers/CMSIS/Include/core_cm4.h **** */ 1856:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin 1857:Drivers/CMSIS/Include/core_cm4.h **** { 251 .loc 2 1857 1 is_stmt 1 view -0 252 .cfi_startproc 253 @ args = 0, pretend = 0, frame = 0 254 @ frame_needed = 0, uses_anonymous_args = 0 255 .loc 2 1857 1 is_stmt 0 view .LVU59 256 0000 00B5 push {lr} 257 .LCFI0: 258 .cfi_def_cfa_offset 4 259 .cfi_offset 14, -4 1858:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 260 .loc 2 1858 3 is_stmt 1 view .LVU60 261 .loc 2 1858 12 is_stmt 0 view .LVU61 262 0002 00F00700 and r0, r0, #7 263 .LVL16: 1859:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; 264 .loc 2 1859 3 is_stmt 1 view .LVU62 1860:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; 265 .loc 2 1860 3 view .LVU63 1861:Drivers/CMSIS/Include/core_cm4.h **** 1862:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 266 .loc 2 1862 3 view .LVU64 267 .loc 2 1862 31 is_stmt 0 view .LVU65 268 0006 C0F1070C rsb ip, r0, #7 269 .loc 2 1862 23 view .LVU66 270 000a BCF1040F cmp ip, #4 271 000e 28BF it cs 272 0010 4FF0040C movcs ip, #4 273 .LVL17: 1863:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 274 .loc 2 1863 3 is_stmt 1 view .LVU67 275 .loc 2 1863 44 is_stmt 0 view .LVU68 276 0014 031D adds r3, r0, #4 ARM GAS /tmp/ccDEPnZG.s page 55 277 .loc 2 1863 109 view .LVU69 278 0016 062B cmp r3, #6 279 0018 0FD9 bls .L21 280 .loc 2 1863 109 discriminator 1 view .LVU70 281 001a C31E subs r3, r0, #3 282 .L20: 283 .LVL18: 1864:Drivers/CMSIS/Include/core_cm4.h **** 1865:Drivers/CMSIS/Include/core_cm4.h **** return ( 284 .loc 2 1865 3 is_stmt 1 view .LVU71 1866:Drivers/CMSIS/Include/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits 285 .loc 2 1866 30 is_stmt 0 view .LVU72 286 001c 4FF0FF3E mov lr, #-1 287 0020 0EFA0CF0 lsl r0, lr, ip 288 .LVL19: 289 .loc 2 1866 30 view .LVU73 290 0024 21EA0001 bic r1, r1, r0 291 .LVL20: 292 .loc 2 1866 82 view .LVU74 293 0028 9940 lsls r1, r1, r3 1867:Drivers/CMSIS/Include/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 294 .loc 2 1867 30 view .LVU75 295 002a 0EFA03FE lsl lr, lr, r3 296 002e 22EA0E02 bic r2, r2, lr 297 .LVL21: 1868:Drivers/CMSIS/Include/core_cm4.h **** ); 1869:Drivers/CMSIS/Include/core_cm4.h **** } 298 .loc 2 1869 1 view .LVU76 299 0032 41EA0200 orr r0, r1, r2 300 0036 5DF804FB ldr pc, [sp], #4 301 .LVL22: 302 .L21: 1863:Drivers/CMSIS/Include/core_cm4.h **** 303 .loc 2 1863 109 discriminator 2 view .LVU77 304 003a 0023 movs r3, #0 305 003c EEE7 b .L20 306 .cfi_endproc 307 .LFE115: 309 .section .text.NVIC_DecodePriority,"ax",%progbits 310 .align 1 311 .syntax unified 312 .thumb 313 .thumb_func 315 NVIC_DecodePriority: 316 .LVL23: 317 .LFB116: 1870:Drivers/CMSIS/Include/core_cm4.h **** 1871:Drivers/CMSIS/Include/core_cm4.h **** 1872:Drivers/CMSIS/Include/core_cm4.h **** /** 1873:Drivers/CMSIS/Include/core_cm4.h **** \brief Decode Priority 1874:Drivers/CMSIS/Include/core_cm4.h **** \details Decodes an interrupt priority value with a given priority group to 1875:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value and subpriority value. 1876:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available 1877:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1878:Drivers/CMSIS/Include/core_cm4.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC 1879:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. 1880:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). ARM GAS /tmp/ccDEPnZG.s page 56 1881:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pSubPriority Subpriority value (starting from 0). 1882:Drivers/CMSIS/Include/core_cm4.h **** */ 1883:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons 1884:Drivers/CMSIS/Include/core_cm4.h **** { 318 .loc 2 1884 1 is_stmt 1 view -0 319 .cfi_startproc 320 @ args = 0, pretend = 0, frame = 0 321 @ frame_needed = 0, uses_anonymous_args = 0 322 .loc 2 1884 1 is_stmt 0 view .LVU79 323 0000 10B5 push {r4, lr} 324 .LCFI1: 325 .cfi_def_cfa_offset 8 326 .cfi_offset 4, -8 327 .cfi_offset 14, -4 1885:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 328 .loc 2 1885 3 is_stmt 1 view .LVU80 329 .loc 2 1885 12 is_stmt 0 view .LVU81 330 0002 01F00701 and r1, r1, #7 331 .LVL24: 1886:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; 332 .loc 2 1886 3 is_stmt 1 view .LVU82 1887:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; 333 .loc 2 1887 3 view .LVU83 1888:Drivers/CMSIS/Include/core_cm4.h **** 1889:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 334 .loc 2 1889 3 view .LVU84 335 .loc 2 1889 31 is_stmt 0 view .LVU85 336 0006 C1F1070C rsb ip, r1, #7 337 .loc 2 1889 23 view .LVU86 338 000a BCF1040F cmp ip, #4 339 000e 28BF it cs 340 0010 4FF0040C movcs ip, #4 341 .LVL25: 1890:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 342 .loc 2 1890 3 is_stmt 1 view .LVU87 343 .loc 2 1890 44 is_stmt 0 view .LVU88 344 0014 0C1D adds r4, r1, #4 345 .loc 2 1890 109 view .LVU89 346 0016 062C cmp r4, #6 347 0018 0FD9 bls .L25 348 .loc 2 1890 109 discriminator 1 view .LVU90 349 001a 0339 subs r1, r1, #3 350 .LVL26: 351 .L24: 1891:Drivers/CMSIS/Include/core_cm4.h **** 1892:Drivers/CMSIS/Include/core_cm4.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 352 .loc 2 1892 3 is_stmt 1 view .LVU91 353 .loc 2 1892 33 is_stmt 0 view .LVU92 354 001c 20FA01F4 lsr r4, r0, r1 355 .LVL27: 356 .loc 2 1892 53 view .LVU93 357 0020 4FF0FF3E mov lr, #-1 358 0024 0EFA0CFC lsl ip, lr, ip 359 .LVL28: 360 .loc 2 1892 53 view .LVU94 361 0028 24EA0C04 bic r4, r4, ip 362 .loc 2 1892 21 view .LVU95 ARM GAS /tmp/ccDEPnZG.s page 57 363 002c 1460 str r4, [r2] 1893:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 364 .loc 2 1893 3 is_stmt 1 view .LVU96 365 .loc 2 1893 53 is_stmt 0 view .LVU97 366 002e 0EFA01FE lsl lr, lr, r1 367 0032 20EA0E00 bic r0, r0, lr 368 .LVL29: 369 .loc 2 1893 21 view .LVU98 370 0036 1860 str r0, [r3] 1894:Drivers/CMSIS/Include/core_cm4.h **** } 371 .loc 2 1894 1 view .LVU99 372 0038 10BD pop {r4, pc} 373 .LVL30: 374 .L25: 1890:Drivers/CMSIS/Include/core_cm4.h **** 375 .loc 2 1890 109 discriminator 2 view .LVU100 376 003a 0021 movs r1, #0 377 .LVL31: 1890:Drivers/CMSIS/Include/core_cm4.h **** 378 .loc 2 1890 109 discriminator 2 view .LVU101 379 003c EEE7 b .L24 380 .cfi_endproc 381 .LFE116: 383 .section .text.__NVIC_SystemReset,"ax",%progbits 384 .align 1 385 .syntax unified 386 .thumb 387 .thumb_func 389 __NVIC_SystemReset: 390 .LFB119: 1895:Drivers/CMSIS/Include/core_cm4.h **** 1896:Drivers/CMSIS/Include/core_cm4.h **** 1897:Drivers/CMSIS/Include/core_cm4.h **** /** 1898:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Vector 1899:Drivers/CMSIS/Include/core_cm4.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. 1900:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1901:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1902:Drivers/CMSIS/Include/core_cm4.h **** VTOR must been relocated to SRAM before. 1903:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number 1904:Drivers/CMSIS/Include/core_cm4.h **** \param [in] vector Address of interrupt handler function 1905:Drivers/CMSIS/Include/core_cm4.h **** */ 1906:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1907:Drivers/CMSIS/Include/core_cm4.h **** { 1908:Drivers/CMSIS/Include/core_cm4.h **** uint32_t vectors = (uint32_t )SCB->VTOR; 1909:Drivers/CMSIS/Include/core_cm4.h **** (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; 1910:Drivers/CMSIS/Include/core_cm4.h **** /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ 1911:Drivers/CMSIS/Include/core_cm4.h **** } 1912:Drivers/CMSIS/Include/core_cm4.h **** 1913:Drivers/CMSIS/Include/core_cm4.h **** 1914:Drivers/CMSIS/Include/core_cm4.h **** /** 1915:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Vector 1916:Drivers/CMSIS/Include/core_cm4.h **** \details Reads an interrupt vector from interrupt vector table. 1917:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, 1918:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. 1919:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. 1920:Drivers/CMSIS/Include/core_cm4.h **** \return Address of interrupt handler function 1921:Drivers/CMSIS/Include/core_cm4.h **** */ ARM GAS /tmp/ccDEPnZG.s page 58 1922:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1923:Drivers/CMSIS/Include/core_cm4.h **** { 1924:Drivers/CMSIS/Include/core_cm4.h **** uint32_t vectors = (uint32_t )SCB->VTOR; 1925:Drivers/CMSIS/Include/core_cm4.h **** return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); 1926:Drivers/CMSIS/Include/core_cm4.h **** } 1927:Drivers/CMSIS/Include/core_cm4.h **** 1928:Drivers/CMSIS/Include/core_cm4.h **** 1929:Drivers/CMSIS/Include/core_cm4.h **** /** 1930:Drivers/CMSIS/Include/core_cm4.h **** \brief System Reset 1931:Drivers/CMSIS/Include/core_cm4.h **** \details Initiates a system reset request to reset the MCU. 1932:Drivers/CMSIS/Include/core_cm4.h **** */ 1933:Drivers/CMSIS/Include/core_cm4.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 1934:Drivers/CMSIS/Include/core_cm4.h **** { 391 .loc 2 1934 1 is_stmt 1 view -0 392 .cfi_startproc 393 @ Volatile: function does not return. 394 @ args = 0, pretend = 0, frame = 0 395 @ frame_needed = 0, uses_anonymous_args = 0 396 @ link register save eliminated. 1935:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure all outstanding memor 397 .loc 2 1935 3 view .LVU103 398 .LBB40: 399 .LBI40: 944:Drivers/CMSIS/Include/cmsis_gcc.h **** { 400 .loc 3 944 27 view .LVU104 401 .LBB41: 402 .loc 3 946 3 view .LVU105 403 .syntax unified 404 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 405 0000 BFF34F8F dsb 0xF 406 @ 0 "" 2 407 .thumb 408 .syntax unified 409 .LBE41: 410 .LBE40: 1936:Drivers/CMSIS/Include/core_cm4.h **** buffered write are completed 1937:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 411 .loc 2 1937 3 view .LVU106 1938:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 412 .loc 2 1938 32 is_stmt 0 view .LVU107 413 0004 0549 ldr r1, .L29 414 0006 CA68 ldr r2, [r1, #12] 415 .loc 2 1938 40 view .LVU108 416 0008 02F4E062 and r2, r2, #1792 1937:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 417 .loc 2 1937 17 view .LVU109 418 000c 044B ldr r3, .L29+4 419 000e 1343 orrs r3, r3, r2 1937:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 420 .loc 2 1937 15 view .LVU110 421 0010 CB60 str r3, [r1, #12] 1939:Drivers/CMSIS/Include/core_cm4.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange 1940:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure completion of memory 422 .loc 2 1940 3 is_stmt 1 view .LVU111 423 .LBB42: 424 .LBI42: 944:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccDEPnZG.s page 59 425 .loc 3 944 27 view .LVU112 426 .LBB43: 427 .loc 3 946 3 view .LVU113 428 .syntax unified 429 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 430 0012 BFF34F8F dsb 0xF 431 @ 0 "" 2 432 .thumb 433 .syntax unified 434 .L28: 435 .LBE43: 436 .LBE42: 1941:Drivers/CMSIS/Include/core_cm4.h **** 1942:Drivers/CMSIS/Include/core_cm4.h **** for(;;) /* wait until reset */ 437 .loc 2 1942 3 view .LVU114 1943:Drivers/CMSIS/Include/core_cm4.h **** { 1944:Drivers/CMSIS/Include/core_cm4.h **** __NOP(); 438 .loc 2 1944 5 discriminator 1 view .LVU115 439 .syntax unified 440 @ 1944 "Drivers/CMSIS/Include/core_cm4.h" 1 441 0016 00BF nop 442 @ 0 "" 2 1942:Drivers/CMSIS/Include/core_cm4.h **** { 443 .loc 2 1942 3 view .LVU116 444 .thumb 445 .syntax unified 446 0018 FDE7 b .L28 447 .L30: 448 001a 00BF .align 2 449 .L29: 450 001c 00ED00E0 .word -536810240 451 0020 0400FA05 .word 100270084 452 .cfi_endproc 453 .LFE119: 455 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits 456 .align 1 457 .global HAL_NVIC_SetPriorityGrouping 458 .syntax unified 459 .thumb 460 .thumb_func 462 HAL_NVIC_SetPriorityGrouping: 463 .LVL32: 464 .LFB329: 1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ****************************************************************************** 3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @file stm32g4xx_hal_cortex.c 4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @author MCD Application Team 5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief CORTEX HAL module driver. 6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * functionalities of the CORTEX: 8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * + Initialization and Configuration functions 9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * + Peripheral Control functions 10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ****************************************************************************** 12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @attention 13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * Copyright (c) 2019 STMicroelectronics. ARM GAS /tmp/ccDEPnZG.s page 60 15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * All rights reserved. 16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This software is licensed under terms that can be found in the LICENSE file 18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * in the root directory of this software component. 19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ****************************************************************************** 22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @verbatim 23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ============================================================================== 24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ##### How to use this driver ##### 25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ============================================================================== 26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** [..] 28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** 29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** =========================================================== 30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** [..] 31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). 32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** The Cortex-M4 exceptions are managed by CMSIS functions. 33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. 35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). 37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. 39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority. 40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority): 42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+@) Lowest pre-emption priority 43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+@) Lowest sub priority 44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number) 45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** [..] 47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** *** How to configure SysTick using CORTEX HAL driver *** 48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ======================================================== 49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** [..] 50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** Setup SysTick Timer for time base. 51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which 53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** is a CMSIS function that: 54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. 55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x0F). 56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Resets the SysTick Counter register. 57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). 58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. 59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Starts the SysTick Counter. 60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro 62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the 63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined 64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** inside the stm32g4xx_hal_cortex.h file. 65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the 67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct 69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: 71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ARM GAS /tmp/ccDEPnZG.s page 61 72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) 73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function 74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF 75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @endverbatim 77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ****************************************************************************** 78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** The table below gives the allowed values of the pre-emption priority and subpriority according 80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. 81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** =============================================================================================== 83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | 84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** =============================================================================================== 85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bi 86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** | | | 4 bi 87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ----------------------------------------------------------------------------------------------- 88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bi 89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** | | | 3 bi 90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ----------------------------------------------------------------------------------------------- 91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bi 92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** | | | 2 bi 93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ----------------------------------------------------------------------------------------------- 94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bi 95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** | | | 1 bi 96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ----------------------------------------------------------------------------------------------- 97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bi 98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** | | | 0 bi 99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** =============================================================================================== 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** #include "stm32g4xx_hal.h" 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup STM32G4xx_HAL_Driver 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @{ 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @{ 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/ 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/ 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/ 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/ 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/ 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @{ 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group1 ARM GAS /tmp/ccDEPnZG.s page 62 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Initialization and Configuration functions 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @verbatim 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ============================================================================== 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ##### Initialization and Configuration functions ##### 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ============================================================================== 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** [..] 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** SysTick functionalities 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @endverbatim 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @{ 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Set the priority grouping field (pre-emption priority and subpriority) 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * using the required unlock sequence. 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param PriorityGroup: The priority grouping bits length. 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be one of the following values: 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 4 bits for subpriority 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 3 bits for subpriority 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 2 bits for subpriority 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 1 bit for subpriority 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 0 bit for subpriority 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority. 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 465 .loc 1 164 1 view -0 466 .cfi_startproc 467 @ args = 0, pretend = 0, frame = 0 468 @ frame_needed = 0, uses_anonymous_args = 0 469 @ link register save eliminated. 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 470 .loc 1 166 3 view .LVU118 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup); 471 .loc 1 169 3 view .LVU119 472 .LBB44: 473 .LBI44: 1648:Drivers/CMSIS/Include/core_cm4.h **** { 474 .loc 2 1648 22 view .LVU120 475 .LBB45: 1650:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a 476 .loc 2 1650 3 view .LVU121 1651:Drivers/CMSIS/Include/core_cm4.h **** 477 .loc 2 1651 3 view .LVU122 ARM GAS /tmp/ccDEPnZG.s page 63 1653:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 478 .loc 2 1653 3 view .LVU123 1653:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan 479 .loc 2 1653 14 is_stmt 0 view .LVU124 480 0000 074A ldr r2, .L32 481 0002 D368 ldr r3, [r2, #12] 482 .LVL33: 1654:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | 483 .loc 2 1654 3 is_stmt 1 view .LVU125 1654:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | 484 .loc 2 1654 13 is_stmt 0 view .LVU126 485 0004 23F4E063 bic r3, r3, #1792 486 .LVL34: 1654:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | 487 .loc 2 1654 13 view .LVU127 488 0008 1B04 lsls r3, r3, #16 489 000a 1B0C lsrs r3, r3, #16 490 .LVL35: 1655:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 491 .loc 2 1655 3 is_stmt 1 view .LVU128 1657:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; 492 .loc 2 1657 35 is_stmt 0 view .LVU129 493 000c 0002 lsls r0, r0, #8 494 .LVL36: 1657:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; 495 .loc 2 1657 35 view .LVU130 496 000e 00F4E060 and r0, r0, #1792 1656:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a 497 .loc 2 1656 62 view .LVU131 498 0012 0343 orrs r3, r3, r0 499 .LVL37: 1655:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 500 .loc 2 1655 14 view .LVU132 501 0014 43F0BF63 orr r3, r3, #100139008 502 0018 43F40033 orr r3, r3, #131072 503 .LVL38: 1658:Drivers/CMSIS/Include/core_cm4.h **** } 504 .loc 2 1658 3 is_stmt 1 view .LVU133 1658:Drivers/CMSIS/Include/core_cm4.h **** } 505 .loc 2 1658 14 is_stmt 0 view .LVU134 506 001c D360 str r3, [r2, #12] 507 .LVL39: 1658:Drivers/CMSIS/Include/core_cm4.h **** } 508 .loc 2 1658 14 view .LVU135 509 .LBE45: 510 .LBE44: 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 511 .loc 1 170 1 view .LVU136 512 001e 7047 bx lr 513 .L33: 514 .align 2 515 .L32: 516 0020 00ED00E0 .word -536810240 517 .cfi_endproc 518 .LFE329: 520 .section .text.HAL_NVIC_SetPriority,"ax",%progbits 521 .align 1 ARM GAS /tmp/ccDEPnZG.s page 64 522 .global HAL_NVIC_SetPriority 523 .syntax unified 524 .thumb 525 .thumb_func 527 HAL_NVIC_SetPriority: 528 .LVL40: 529 .LFB330: 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Set the priority of an interrupt. 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn: External interrupt number. 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param PreemptPriority: The pre-emption priority for the IRQn channel. 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * A lower priority value indicates a higher priority 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param SubPriority: the subpriority level for the IRQ channel. 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * A lower priority value indicates a higher priority. 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 530 .loc 1 186 1 is_stmt 1 view -0 531 .cfi_startproc 532 @ args = 0, pretend = 0, frame = 0 533 @ frame_needed = 0, uses_anonymous_args = 0 534 .loc 1 186 1 is_stmt 0 view .LVU138 535 0000 10B5 push {r4, lr} 536 .LCFI2: 537 .cfi_def_cfa_offset 8 538 .cfi_offset 4, -8 539 .cfi_offset 14, -4 540 0002 0446 mov r4, r0 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t prioritygroup; 541 .loc 1 187 3 is_stmt 1 view .LVU139 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); 542 .loc 1 190 3 view .LVU140 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); 543 .loc 1 191 3 view .LVU141 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping(); 544 .loc 1 193 3 view .LVU142 545 .LBB46: 546 .LBI46: 1667:Drivers/CMSIS/Include/core_cm4.h **** { 547 .loc 2 1667 26 view .LVU143 548 .LBB47: 1669:Drivers/CMSIS/Include/core_cm4.h **** } 549 .loc 2 1669 3 view .LVU144 1669:Drivers/CMSIS/Include/core_cm4.h **** } 550 .loc 2 1669 26 is_stmt 0 view .LVU145 551 0004 054B ldr r3, .L36 552 0006 D868 ldr r0, [r3, #12] 553 .LVL41: ARM GAS /tmp/ccDEPnZG.s page 65 1669:Drivers/CMSIS/Include/core_cm4.h **** } 554 .loc 2 1669 26 view .LVU146 555 .LBE47: 556 .LBE46: 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 557 .loc 1 195 3 is_stmt 1 view .LVU147 558 0008 C0F30220 ubfx r0, r0, #8, #3 559 .LVL42: 560 .loc 1 195 3 is_stmt 0 view .LVU148 561 000c FFF7FEFF bl NVIC_EncodePriority 562 .LVL43: 563 .loc 1 195 3 view .LVU149 564 0010 0146 mov r1, r0 565 .loc 1 195 3 discriminator 1 view .LVU150 566 0012 2046 mov r0, r4 567 0014 FFF7FEFF bl __NVIC_SetPriority 568 .LVL44: 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 569 .loc 1 196 1 view .LVU151 570 0018 10BD pop {r4, pc} 571 .LVL45: 572 .L37: 573 .loc 1 196 1 view .LVU152 574 001a 00BF .align 2 575 .L36: 576 001c 00ED00E0 .word -536810240 577 .cfi_endproc 578 .LFE330: 580 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits 581 .align 1 582 .global HAL_NVIC_EnableIRQ 583 .syntax unified 584 .thumb 585 .thumb_func 587 HAL_NVIC_EnableIRQ: 588 .LVL46: 589 .LFB331: 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Enable a device specific interrupt in the NVIC interrupt controller. 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * function should be called before. 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn External interrupt number. 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 590 .loc 1 208 1 is_stmt 1 view -0 591 .cfi_startproc 592 @ args = 0, pretend = 0, frame = 0 593 @ frame_needed = 0, uses_anonymous_args = 0 594 .loc 1 208 1 is_stmt 0 view .LVU154 595 0000 08B5 push {r3, lr} 596 .LCFI3: ARM GAS /tmp/ccDEPnZG.s page 66 597 .cfi_def_cfa_offset 8 598 .cfi_offset 3, -8 599 .cfi_offset 14, -4 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 600 .loc 1 210 3 is_stmt 1 view .LVU155 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Enable interrupt */ 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); 601 .loc 1 213 3 view .LVU156 602 0002 FFF7FEFF bl __NVIC_EnableIRQ 603 .LVL47: 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 604 .loc 1 214 1 is_stmt 0 view .LVU157 605 0006 08BD pop {r3, pc} 606 .cfi_endproc 607 .LFE331: 609 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits 610 .align 1 611 .global HAL_NVIC_DisableIRQ 612 .syntax unified 613 .thumb 614 .thumb_func 616 HAL_NVIC_DisableIRQ: 617 .LVL48: 618 .LFB332: 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Disable a device specific interrupt in the NVIC interrupt controller. 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn External interrupt number. 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 619 .loc 1 224 1 is_stmt 1 view -0 620 .cfi_startproc 621 @ args = 0, pretend = 0, frame = 0 622 @ frame_needed = 0, uses_anonymous_args = 0 623 .loc 1 224 1 is_stmt 0 view .LVU159 624 0000 08B5 push {r3, lr} 625 .LCFI4: 626 .cfi_def_cfa_offset 8 627 .cfi_offset 3, -8 628 .cfi_offset 14, -4 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 629 .loc 1 226 3 is_stmt 1 view .LVU160 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Disable interrupt */ 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); 630 .loc 1 229 3 view .LVU161 631 0002 FFF7FEFF bl __NVIC_DisableIRQ 632 .LVL49: 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 633 .loc 1 230 1 is_stmt 0 view .LVU162 ARM GAS /tmp/ccDEPnZG.s page 67 634 0006 08BD pop {r3, pc} 635 .cfi_endproc 636 .LFE332: 638 .section .text.HAL_NVIC_SystemReset,"ax",%progbits 639 .align 1 640 .global HAL_NVIC_SystemReset 641 .syntax unified 642 .thumb 643 .thumb_func 645 HAL_NVIC_SystemReset: 646 .LFB333: 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Initiate a system reset request to reset the MCU. 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 647 .loc 1 237 1 is_stmt 1 view -0 648 .cfi_startproc 649 @ Volatile: function does not return. 650 @ args = 0, pretend = 0, frame = 0 651 @ frame_needed = 0, uses_anonymous_args = 0 652 0000 08B5 push {r3, lr} 653 .LCFI5: 654 .cfi_def_cfa_offset 8 655 .cfi_offset 3, -8 656 .cfi_offset 14, -4 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* System Reset */ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_SystemReset(); 657 .loc 1 239 3 view .LVU164 658 0002 FFF7FEFF bl __NVIC_SystemReset 659 .LVL50: 660 .cfi_endproc 661 .LFE333: 663 .section .text.HAL_SYSTICK_Config,"ax",%progbits 664 .align 1 665 .global HAL_SYSTICK_Config 666 .syntax unified 667 .thumb 668 .thumb_func 670 HAL_SYSTICK_Config: 671 .LVL51: 672 .LFB334: 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (Sys 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * - 1 Function failed. 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 673 .loc 1 250 1 view -0 674 .cfi_startproc ARM GAS /tmp/ccDEPnZG.s page 68 675 @ args = 0, pretend = 0, frame = 0 676 @ frame_needed = 0, uses_anonymous_args = 0 677 @ link register save eliminated. 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** return SysTick_Config(TicksNumb); 678 .loc 1 251 4 view .LVU166 679 .LBB48: 680 .LBI48: 1945:Drivers/CMSIS/Include/core_cm4.h **** } 1946:Drivers/CMSIS/Include/core_cm4.h **** } 1947:Drivers/CMSIS/Include/core_cm4.h **** 1948:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_NVICFunctions */ 1949:Drivers/CMSIS/Include/core_cm4.h **** 1950:Drivers/CMSIS/Include/core_cm4.h **** 1951:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## MPU functions #################################### */ 1952:Drivers/CMSIS/Include/core_cm4.h **** 1953:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1954:Drivers/CMSIS/Include/core_cm4.h **** 1955:Drivers/CMSIS/Include/core_cm4.h **** #include "mpu_armv7.h" 1956:Drivers/CMSIS/Include/core_cm4.h **** 1957:Drivers/CMSIS/Include/core_cm4.h **** #endif 1958:Drivers/CMSIS/Include/core_cm4.h **** 1959:Drivers/CMSIS/Include/core_cm4.h **** 1960:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## FPU functions #################################### */ 1961:Drivers/CMSIS/Include/core_cm4.h **** /** 1962:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface 1963:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions 1964:Drivers/CMSIS/Include/core_cm4.h **** \brief Function that provides FPU type. 1965:Drivers/CMSIS/Include/core_cm4.h **** @{ 1966:Drivers/CMSIS/Include/core_cm4.h **** */ 1967:Drivers/CMSIS/Include/core_cm4.h **** 1968:Drivers/CMSIS/Include/core_cm4.h **** /** 1969:Drivers/CMSIS/Include/core_cm4.h **** \brief get FPU type 1970:Drivers/CMSIS/Include/core_cm4.h **** \details returns the FPU type 1971:Drivers/CMSIS/Include/core_cm4.h **** \returns 1972:Drivers/CMSIS/Include/core_cm4.h **** - \b 0: No FPU 1973:Drivers/CMSIS/Include/core_cm4.h **** - \b 1: Single precision FPU 1974:Drivers/CMSIS/Include/core_cm4.h **** - \b 2: Double + Single precision FPU 1975:Drivers/CMSIS/Include/core_cm4.h **** */ 1976:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1977:Drivers/CMSIS/Include/core_cm4.h **** { 1978:Drivers/CMSIS/Include/core_cm4.h **** uint32_t mvfr0; 1979:Drivers/CMSIS/Include/core_cm4.h **** 1980:Drivers/CMSIS/Include/core_cm4.h **** mvfr0 = FPU->MVFR0; 1981:Drivers/CMSIS/Include/core_cm4.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 1982:Drivers/CMSIS/Include/core_cm4.h **** { 1983:Drivers/CMSIS/Include/core_cm4.h **** return 1U; /* Single precision FPU */ 1984:Drivers/CMSIS/Include/core_cm4.h **** } 1985:Drivers/CMSIS/Include/core_cm4.h **** else 1986:Drivers/CMSIS/Include/core_cm4.h **** { 1987:Drivers/CMSIS/Include/core_cm4.h **** return 0U; /* No FPU */ 1988:Drivers/CMSIS/Include/core_cm4.h **** } 1989:Drivers/CMSIS/Include/core_cm4.h **** } 1990:Drivers/CMSIS/Include/core_cm4.h **** 1991:Drivers/CMSIS/Include/core_cm4.h **** 1992:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */ 1993:Drivers/CMSIS/Include/core_cm4.h **** 1994:Drivers/CMSIS/Include/core_cm4.h **** ARM GAS /tmp/ccDEPnZG.s page 69 1995:Drivers/CMSIS/Include/core_cm4.h **** 1996:Drivers/CMSIS/Include/core_cm4.h **** /* ################################## SysTick function ######################################## 1997:Drivers/CMSIS/Include/core_cm4.h **** /** 1998:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface 1999:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 2000:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that configure the System. 2001:Drivers/CMSIS/Include/core_cm4.h **** @{ 2002:Drivers/CMSIS/Include/core_cm4.h **** */ 2003:Drivers/CMSIS/Include/core_cm4.h **** 2004:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 2005:Drivers/CMSIS/Include/core_cm4.h **** 2006:Drivers/CMSIS/Include/core_cm4.h **** /** 2007:Drivers/CMSIS/Include/core_cm4.h **** \brief System Tick Configuration 2008:Drivers/CMSIS/Include/core_cm4.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 2009:Drivers/CMSIS/Include/core_cm4.h **** Counter is in free running mode to generate periodic interrupts. 2010:Drivers/CMSIS/Include/core_cm4.h **** \param [in] ticks Number of ticks between two interrupts. 2011:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Function succeeded. 2012:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Function failed. 2013:Drivers/CMSIS/Include/core_cm4.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the 2014:Drivers/CMSIS/Include/core_cm4.h **** function SysTick_Config is not included. In this case, the file device. 2015:Drivers/CMSIS/Include/core_cm4.h **** must contain a vendor-specific implementation of this function. 2016:Drivers/CMSIS/Include/core_cm4.h **** */ 2017:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 681 .loc 2 2017 26 view .LVU167 682 .LBB49: 2018:Drivers/CMSIS/Include/core_cm4.h **** { 2019:Drivers/CMSIS/Include/core_cm4.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 683 .loc 2 2019 3 view .LVU168 684 .loc 2 2019 14 is_stmt 0 view .LVU169 685 0000 0138 subs r0, r0, #1 686 .LVL52: 687 .loc 2 2019 6 view .LVU170 688 0002 B0F1807F cmp r0, #16777216 689 0006 0BD2 bcs .L46 2020:Drivers/CMSIS/Include/core_cm4.h **** { 2021:Drivers/CMSIS/Include/core_cm4.h **** return (1UL); /* Reload value impossible */ 2022:Drivers/CMSIS/Include/core_cm4.h **** } 2023:Drivers/CMSIS/Include/core_cm4.h **** 2024:Drivers/CMSIS/Include/core_cm4.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 690 .loc 2 2024 3 is_stmt 1 view .LVU171 691 .loc 2 2024 18 is_stmt 0 view .LVU172 692 0008 4FF0E023 mov r3, #-536813568 693 000c 5861 str r0, [r3, #20] 2025:Drivers/CMSIS/Include/core_cm4.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int 694 .loc 2 2025 3 is_stmt 1 view .LVU173 695 .LVL53: 696 .LBB50: 697 .LBI50: 1809:Drivers/CMSIS/Include/core_cm4.h **** { 698 .loc 2 1809 22 view .LVU174 699 .LBB51: 1811:Drivers/CMSIS/Include/core_cm4.h **** { 700 .loc 2 1811 3 view .LVU175 1817:Drivers/CMSIS/Include/core_cm4.h **** } 701 .loc 2 1817 5 view .LVU176 1817:Drivers/CMSIS/Include/core_cm4.h **** } 702 .loc 2 1817 46 is_stmt 0 view .LVU177 ARM GAS /tmp/ccDEPnZG.s page 70 703 000e 054A ldr r2, .L47 704 0010 F021 movs r1, #240 705 0012 82F82310 strb r1, [r2, #35] 706 .LVL54: 1817:Drivers/CMSIS/Include/core_cm4.h **** } 707 .loc 2 1817 46 view .LVU178 708 .LBE51: 709 .LBE50: 2026:Drivers/CMSIS/Include/core_cm4.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val 710 .loc 2 2026 3 is_stmt 1 view .LVU179 711 .loc 2 2026 18 is_stmt 0 view .LVU180 712 0016 0020 movs r0, #0 713 .LVL55: 714 .loc 2 2026 18 view .LVU181 715 0018 9861 str r0, [r3, #24] 2027:Drivers/CMSIS/Include/core_cm4.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 716 .loc 2 2027 3 is_stmt 1 view .LVU182 717 .loc 2 2027 18 is_stmt 0 view .LVU183 718 001a 0722 movs r2, #7 719 001c 1A61 str r2, [r3, #16] 2028:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_TICKINT_Msk | 2029:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi 2030:Drivers/CMSIS/Include/core_cm4.h **** return (0UL); /* Function successful */ 720 .loc 2 2030 3 is_stmt 1 view .LVU184 721 .loc 2 2030 10 is_stmt 0 view .LVU185 722 001e 7047 bx lr 723 .L46: 2021:Drivers/CMSIS/Include/core_cm4.h **** } 724 .loc 2 2021 12 view .LVU186 725 0020 0120 movs r0, #1 726 .LVL56: 2021:Drivers/CMSIS/Include/core_cm4.h **** } 727 .loc 2 2021 12 view .LVU187 728 .LBE49: 729 .LBE48: 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 730 .loc 1 252 1 view .LVU188 731 0022 7047 bx lr 732 .L48: 733 .align 2 734 .L47: 735 0024 00ED00E0 .word -536810240 736 .cfi_endproc 737 .LFE334: 739 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits 740 .align 1 741 .global HAL_NVIC_GetPriorityGrouping 742 .syntax unified 743 .thumb 744 .thumb_func 746 HAL_NVIC_GetPriorityGrouping: 747 .LFB335: 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @} 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group2 ARM GAS /tmp/ccDEPnZG.s page 71 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Cortex control functions 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @verbatim 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ============================================================================== 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ##### Peripheral Control functions ##### 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ============================================================================== 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** [..] 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** @endverbatim 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @{ 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Get the priority grouping field from the NVIC Interrupt Controller. 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void) 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 748 .loc 1 278 1 is_stmt 1 view -0 749 .cfi_startproc 750 @ args = 0, pretend = 0, frame = 0 751 @ frame_needed = 0, uses_anonymous_args = 0 752 @ link register save eliminated. 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */ 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** return NVIC_GetPriorityGrouping(); 753 .loc 1 280 3 view .LVU190 754 .LBB52: 755 .LBI52: 1667:Drivers/CMSIS/Include/core_cm4.h **** { 756 .loc 2 1667 26 view .LVU191 757 .LBB53: 1669:Drivers/CMSIS/Include/core_cm4.h **** } 758 .loc 2 1669 3 view .LVU192 1669:Drivers/CMSIS/Include/core_cm4.h **** } 759 .loc 2 1669 26 is_stmt 0 view .LVU193 760 0000 024B ldr r3, .L50 761 0002 D868 ldr r0, [r3, #12] 762 .LBE53: 763 .LBE52: 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 764 .loc 1 281 1 view .LVU194 765 0004 C0F30220 ubfx r0, r0, #8, #3 766 0008 7047 bx lr 767 .L51: 768 000a 00BF .align 2 769 .L50: 770 000c 00ED00E0 .word -536810240 771 .cfi_endproc 772 .LFE335: 774 .section .text.HAL_NVIC_GetPriority,"ax",%progbits 775 .align 1 776 .global HAL_NVIC_GetPriority 777 .syntax unified 778 .thumb ARM GAS /tmp/ccDEPnZG.s page 72 779 .thumb_func 781 HAL_NVIC_GetPriority: 782 .LVL57: 783 .LFB336: 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Get the priority of an interrupt. 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn: External interrupt number. 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param PriorityGroup: the priority grouping bits length. 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be one of the following values: 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 4 bits for subpriority 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 3 bits for subpriority 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 2 bits for subpriority 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 1 bit for subpriority 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * 0 bit for subpriority 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param pSubPriority: Pointer on the Subpriority value (starting from 0). 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 784 .loc 1 305 1 is_stmt 1 view -0 785 .cfi_startproc 786 @ args = 0, pretend = 0, frame = 0 787 @ frame_needed = 0, uses_anonymous_args = 0 788 .loc 1 305 1 is_stmt 0 view .LVU196 789 0000 70B5 push {r4, r5, r6, lr} 790 .LCFI6: 791 .cfi_def_cfa_offset 16 792 .cfi_offset 4, -16 793 .cfi_offset 5, -12 794 .cfi_offset 6, -8 795 .cfi_offset 14, -4 796 0002 0C46 mov r4, r1 797 0004 1546 mov r5, r2 798 0006 1E46 mov r6, r3 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 799 .loc 1 307 3 is_stmt 1 view .LVU197 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); 800 .loc 1 309 3 view .LVU198 801 0008 FFF7FEFF bl __NVIC_GetPriority 802 .LVL58: 803 .loc 1 309 3 is_stmt 0 discriminator 1 view .LVU199 804 000c 3346 mov r3, r6 805 000e 2A46 mov r2, r5 806 0010 2146 mov r1, r4 807 0012 FFF7FEFF bl NVIC_DecodePriority 808 .LVL59: ARM GAS /tmp/ccDEPnZG.s page 73 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 809 .loc 1 310 1 view .LVU200 810 0016 70BD pop {r4, r5, r6, pc} 811 .loc 1 310 1 view .LVU201 812 .cfi_endproc 813 .LFE336: 815 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits 816 .align 1 817 .global HAL_NVIC_SetPendingIRQ 818 .syntax unified 819 .thumb 820 .thumb_func 822 HAL_NVIC_SetPendingIRQ: 823 .LVL60: 824 .LFB337: 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Set Pending bit of an external interrupt. 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn External interrupt number 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 825 .loc 1 320 1 is_stmt 1 view -0 826 .cfi_startproc 827 @ args = 0, pretend = 0, frame = 0 828 @ frame_needed = 0, uses_anonymous_args = 0 829 @ link register save eliminated. 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 830 .loc 1 322 3 view .LVU203 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Set interrupt pending */ 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); 831 .loc 1 325 3 view .LVU204 832 .LBB54: 833 .LBI54: 1755:Drivers/CMSIS/Include/core_cm4.h **** { 834 .loc 2 1755 22 view .LVU205 835 .LBB55: 1757:Drivers/CMSIS/Include/core_cm4.h **** { 836 .loc 2 1757 3 view .LVU206 1757:Drivers/CMSIS/Include/core_cm4.h **** { 837 .loc 2 1757 6 is_stmt 0 view .LVU207 838 0000 0028 cmp r0, #0 1757:Drivers/CMSIS/Include/core_cm4.h **** { 839 .loc 2 1757 6 view .LVU208 840 0002 08DB blt .L54 1759:Drivers/CMSIS/Include/core_cm4.h **** } 841 .loc 2 1759 5 is_stmt 1 view .LVU209 1759:Drivers/CMSIS/Include/core_cm4.h **** } 842 .loc 2 1759 81 is_stmt 0 view .LVU210 843 0004 00F01F02 and r2, r0, #31 1759:Drivers/CMSIS/Include/core_cm4.h **** } 844 .loc 2 1759 34 view .LVU211 ARM GAS /tmp/ccDEPnZG.s page 74 845 0008 4009 lsrs r0, r0, #5 846 .LVL61: 1759:Drivers/CMSIS/Include/core_cm4.h **** } 847 .loc 2 1759 45 view .LVU212 848 000a 0123 movs r3, #1 849 000c 9340 lsls r3, r3, r2 1759:Drivers/CMSIS/Include/core_cm4.h **** } 850 .loc 2 1759 43 view .LVU213 851 000e 4030 adds r0, r0, #64 852 0010 014A ldr r2, .L56 853 0012 42F82030 str r3, [r2, r0, lsl #2] 854 .LVL62: 855 .L54: 1759:Drivers/CMSIS/Include/core_cm4.h **** } 856 .loc 2 1759 43 view .LVU214 857 .LBE55: 858 .LBE54: 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 859 .loc 1 326 1 view .LVU215 860 0016 7047 bx lr 861 .L57: 862 .align 2 863 .L56: 864 0018 00E100E0 .word -536813312 865 .cfi_endproc 866 .LFE337: 868 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits 869 .align 1 870 .global HAL_NVIC_GetPendingIRQ 871 .syntax unified 872 .thumb 873 .thumb_func 875 HAL_NVIC_GetPendingIRQ: 876 .LVL63: 877 .LFB338: 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Get Pending Interrupt (read the pending register in the NVIC 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * and return the pending bit for the specified interrupt). 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn External interrupt number. 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * - 1 Interrupt status is pending. 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 878 .loc 1 338 1 is_stmt 1 view -0 879 .cfi_startproc 880 @ args = 0, pretend = 0, frame = 0 881 @ frame_needed = 0, uses_anonymous_args = 0 882 @ link register save eliminated. 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 883 .loc 1 340 3 view .LVU217 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Return 1 if pending else 0 */ ARM GAS /tmp/ccDEPnZG.s page 75 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); 884 .loc 1 343 3 view .LVU218 885 .LBB56: 886 .LBI56: 1736:Drivers/CMSIS/Include/core_cm4.h **** { 887 .loc 2 1736 26 view .LVU219 888 .LBB57: 1738:Drivers/CMSIS/Include/core_cm4.h **** { 889 .loc 2 1738 3 view .LVU220 1738:Drivers/CMSIS/Include/core_cm4.h **** { 890 .loc 2 1738 6 is_stmt 0 view .LVU221 891 0000 0028 cmp r0, #0 1738:Drivers/CMSIS/Include/core_cm4.h **** { 892 .loc 2 1738 6 view .LVU222 893 0002 0BDB blt .L60 1740:Drivers/CMSIS/Include/core_cm4.h **** } 894 .loc 2 1740 5 is_stmt 1 view .LVU223 1740:Drivers/CMSIS/Include/core_cm4.h **** } 895 .loc 2 1740 54 is_stmt 0 view .LVU224 896 0004 4309 lsrs r3, r0, #5 1740:Drivers/CMSIS/Include/core_cm4.h **** } 897 .loc 2 1740 35 view .LVU225 898 0006 4033 adds r3, r3, #64 899 0008 054A ldr r2, .L61 900 000a 52F82330 ldr r3, [r2, r3, lsl #2] 1740:Drivers/CMSIS/Include/core_cm4.h **** } 901 .loc 2 1740 91 view .LVU226 902 000e 00F01F00 and r0, r0, #31 903 .LVL64: 1740:Drivers/CMSIS/Include/core_cm4.h **** } 904 .loc 2 1740 103 view .LVU227 905 0012 23FA00F0 lsr r0, r3, r0 1740:Drivers/CMSIS/Include/core_cm4.h **** } 906 .loc 2 1740 12 view .LVU228 907 0016 00F00100 and r0, r0, #1 908 001a 7047 bx lr 909 .L60: 1744:Drivers/CMSIS/Include/core_cm4.h **** } 910 .loc 2 1744 11 view .LVU229 911 001c 0020 movs r0, #0 912 .LVL65: 1744:Drivers/CMSIS/Include/core_cm4.h **** } 913 .loc 2 1744 11 view .LVU230 914 .LBE57: 915 .LBE56: 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 916 .loc 1 344 1 view .LVU231 917 001e 7047 bx lr 918 .L62: 919 .align 2 920 .L61: 921 0020 00E100E0 .word -536813312 922 .cfi_endproc 923 .LFE338: 925 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits 926 .align 1 927 .global HAL_NVIC_ClearPendingIRQ ARM GAS /tmp/ccDEPnZG.s page 76 928 .syntax unified 929 .thumb 930 .thumb_func 932 HAL_NVIC_ClearPendingIRQ: 933 .LVL66: 934 .LFB339: 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Clear the pending bit of an external interrupt. 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn External interrupt number. 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 935 .loc 1 354 1 is_stmt 1 view -0 936 .cfi_startproc 937 @ args = 0, pretend = 0, frame = 0 938 @ frame_needed = 0, uses_anonymous_args = 0 939 @ link register save eliminated. 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 940 .loc 1 356 3 view .LVU233 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Clear pending interrupt */ 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); 941 .loc 1 359 3 view .LVU234 942 .LBB58: 943 .LBI58: 1770:Drivers/CMSIS/Include/core_cm4.h **** { 944 .loc 2 1770 22 view .LVU235 945 .LBB59: 1772:Drivers/CMSIS/Include/core_cm4.h **** { 946 .loc 2 1772 3 view .LVU236 1772:Drivers/CMSIS/Include/core_cm4.h **** { 947 .loc 2 1772 6 is_stmt 0 view .LVU237 948 0000 0028 cmp r0, #0 1772:Drivers/CMSIS/Include/core_cm4.h **** { 949 .loc 2 1772 6 view .LVU238 950 0002 08DB blt .L63 1774:Drivers/CMSIS/Include/core_cm4.h **** } 951 .loc 2 1774 5 is_stmt 1 view .LVU239 1774:Drivers/CMSIS/Include/core_cm4.h **** } 952 .loc 2 1774 81 is_stmt 0 view .LVU240 953 0004 00F01F02 and r2, r0, #31 1774:Drivers/CMSIS/Include/core_cm4.h **** } 954 .loc 2 1774 34 view .LVU241 955 0008 4009 lsrs r0, r0, #5 956 .LVL67: 1774:Drivers/CMSIS/Include/core_cm4.h **** } 957 .loc 2 1774 45 view .LVU242 958 000a 0123 movs r3, #1 959 000c 9340 lsls r3, r3, r2 1774:Drivers/CMSIS/Include/core_cm4.h **** } 960 .loc 2 1774 43 view .LVU243 961 000e 6030 adds r0, r0, #96 ARM GAS /tmp/ccDEPnZG.s page 77 962 0010 014A ldr r2, .L65 963 0012 42F82030 str r3, [r2, r0, lsl #2] 964 .LVL68: 965 .L63: 1774:Drivers/CMSIS/Include/core_cm4.h **** } 966 .loc 2 1774 43 view .LVU244 967 .LBE59: 968 .LBE58: 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 969 .loc 1 360 1 view .LVU245 970 0016 7047 bx lr 971 .L66: 972 .align 2 973 .L65: 974 0018 00E100E0 .word -536813312 975 .cfi_endproc 976 .LFE339: 978 .section .text.HAL_NVIC_GetActive,"ax",%progbits 979 .align 1 980 .global HAL_NVIC_GetActive 981 .syntax unified 982 .thumb 983 .thumb_func 985 HAL_NVIC_GetActive: 986 .LVL69: 987 .LFB340: 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Get active interrupt (read the active register in NVIC and return the active bit). 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param IRQn External interrupt number 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * - 1 Interrupt status is pending. 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 988 .loc 1 371 1 is_stmt 1 view -0 989 .cfi_startproc 990 @ args = 0, pretend = 0, frame = 0 991 @ frame_needed = 0, uses_anonymous_args = 0 992 @ link register save eliminated. 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Return 1 if active else 0 */ 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** return NVIC_GetActive(IRQn); 993 .loc 1 373 3 view .LVU247 994 .LBB60: 995 .LBI60: 1787:Drivers/CMSIS/Include/core_cm4.h **** { 996 .loc 2 1787 26 view .LVU248 997 .LBB61: 1789:Drivers/CMSIS/Include/core_cm4.h **** { 998 .loc 2 1789 3 view .LVU249 1789:Drivers/CMSIS/Include/core_cm4.h **** { 999 .loc 2 1789 6 is_stmt 0 view .LVU250 1000 0000 0028 cmp r0, #0 1789:Drivers/CMSIS/Include/core_cm4.h **** { 1001 .loc 2 1789 6 view .LVU251 ARM GAS /tmp/ccDEPnZG.s page 78 1002 0002 0BDB blt .L69 1791:Drivers/CMSIS/Include/core_cm4.h **** } 1003 .loc 2 1791 5 is_stmt 1 view .LVU252 1791:Drivers/CMSIS/Include/core_cm4.h **** } 1004 .loc 2 1791 54 is_stmt 0 view .LVU253 1005 0004 4309 lsrs r3, r0, #5 1791:Drivers/CMSIS/Include/core_cm4.h **** } 1006 .loc 2 1791 35 view .LVU254 1007 0006 8033 adds r3, r3, #128 1008 0008 054A ldr r2, .L70 1009 000a 52F82330 ldr r3, [r2, r3, lsl #2] 1791:Drivers/CMSIS/Include/core_cm4.h **** } 1010 .loc 2 1791 91 view .LVU255 1011 000e 00F01F00 and r0, r0, #31 1012 .LVL70: 1791:Drivers/CMSIS/Include/core_cm4.h **** } 1013 .loc 2 1791 103 view .LVU256 1014 0012 23FA00F0 lsr r0, r3, r0 1791:Drivers/CMSIS/Include/core_cm4.h **** } 1015 .loc 2 1791 12 view .LVU257 1016 0016 00F00100 and r0, r0, #1 1017 001a 7047 bx lr 1018 .L69: 1795:Drivers/CMSIS/Include/core_cm4.h **** } 1019 .loc 2 1795 11 view .LVU258 1020 001c 0020 movs r0, #0 1021 .LVL71: 1795:Drivers/CMSIS/Include/core_cm4.h **** } 1022 .loc 2 1795 11 view .LVU259 1023 .LBE61: 1024 .LBE60: 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1025 .loc 1 374 1 view .LVU260 1026 001e 7047 bx lr 1027 .L71: 1028 .align 2 1029 .L70: 1030 0020 00E100E0 .word -536813312 1031 .cfi_endproc 1032 .LFE340: 1034 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits 1035 .align 1 1036 .global HAL_SYSTICK_CLKSourceConfig 1037 .syntax unified 1038 .thumb 1039 .thumb_func 1041 HAL_SYSTICK_CLKSourceConfig: 1042 .LVL72: 1043 .LFB341: 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Configure the SysTick clock source. 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param CLKSource: specifies the SysTick clock source. 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be one of the following values: 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None ARM GAS /tmp/ccDEPnZG.s page 79 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 1044 .loc 1 385 1 is_stmt 1 view -0 1045 .cfi_startproc 1046 @ args = 0, pretend = 0, frame = 0 1047 @ frame_needed = 0, uses_anonymous_args = 0 1048 @ link register save eliminated. 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); 1049 .loc 1 387 3 view .LVU262 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) 1050 .loc 1 388 3 view .LVU263 1051 .loc 1 388 6 is_stmt 0 view .LVU264 1052 0000 0428 cmp r0, #4 1053 0002 06D0 beq .L75 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** else 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 1054 .loc 1 394 5 is_stmt 1 view .LVU265 1055 .loc 1 394 12 is_stmt 0 view .LVU266 1056 0004 4FF0E022 mov r2, #-536813568 1057 0008 1369 ldr r3, [r2, #16] 1058 .loc 1 394 19 view .LVU267 1059 000a 23F00403 bic r3, r3, #4 1060 000e 1361 str r3, [r2, #16] 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1061 .loc 1 396 1 view .LVU268 1062 0010 7047 bx lr 1063 .L75: 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1064 .loc 1 390 5 is_stmt 1 view .LVU269 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1065 .loc 1 390 12 is_stmt 0 view .LVU270 1066 0012 4FF0E022 mov r2, #-536813568 1067 0016 1369 ldr r3, [r2, #16] 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1068 .loc 1 390 19 view .LVU271 1069 0018 43F00403 orr r3, r3, #4 1070 001c 1361 str r3, [r2, #16] 1071 001e 7047 bx lr 1072 .cfi_endproc 1073 .LFE341: 1075 .section .text.HAL_SYSTICK_Callback,"ax",%progbits 1076 .align 1 1077 .weak HAL_SYSTICK_Callback 1078 .syntax unified 1079 .thumb 1080 .thumb_func 1082 HAL_SYSTICK_Callback: 1083 .LFB343: 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** ARM GAS /tmp/ccDEPnZG.s page 80 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Handle SYSTICK interrupt request. 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** HAL_SYSTICK_Callback(); 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief SYSTICK callback. 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 1084 .loc 1 412 1 is_stmt 1 view -0 1085 .cfi_startproc 1086 @ args = 0, pretend = 0, frame = 0 1087 @ frame_needed = 0, uses_anonymous_args = 0 1088 @ link register save eliminated. 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* NOTE : This function should not be modified, when the callback is needed, 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1089 .loc 1 416 1 view .LVU273 1090 0000 7047 bx lr 1091 .cfi_endproc 1092 .LFE343: 1094 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits 1095 .align 1 1096 .global HAL_SYSTICK_IRQHandler 1097 .syntax unified 1098 .thumb 1099 .thumb_func 1101 HAL_SYSTICK_IRQHandler: 1102 .LFB342: 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** HAL_SYSTICK_Callback(); 1103 .loc 1 403 1 view -0 1104 .cfi_startproc 1105 @ args = 0, pretend = 0, frame = 0 1106 @ frame_needed = 0, uses_anonymous_args = 0 1107 0000 08B5 push {r3, lr} 1108 .LCFI7: 1109 .cfi_def_cfa_offset 8 1110 .cfi_offset 3, -8 1111 .cfi_offset 14, -4 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1112 .loc 1 404 3 view .LVU275 1113 0002 FFF7FEFF bl HAL_SYSTICK_Callback 1114 .LVL73: 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 1115 .loc 1 405 1 is_stmt 0 view .LVU276 1116 0006 08BD pop {r3, pc} 1117 .cfi_endproc 1118 .LFE342: 1120 .section .text.HAL_MPU_Enable,"ax",%progbits 1121 .align 1 1122 .global HAL_MPU_Enable ARM GAS /tmp/ccDEPnZG.s page 81 1123 .syntax unified 1124 .thumb 1125 .thumb_func 1127 HAL_MPU_Enable: 1128 .LVL74: 1129 .LFB344: 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** #if (__MPU_PRESENT == 1) 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Enable the MPU. 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param MPU_Control: Specifies the control mode of the MPU during hard fault, 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * NMI, FAULTMASK and privileged accessto the default memory 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * This parameter can be one of the following values: 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 1130 .loc 1 431 1 is_stmt 1 view -0 1131 .cfi_startproc 1132 @ args = 0, pretend = 0, frame = 0 1133 @ frame_needed = 0, uses_anonymous_args = 0 1134 @ link register save eliminated. 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Enable the MPU */ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); 1135 .loc 1 433 3 view .LVU278 1136 .loc 1 433 28 is_stmt 0 view .LVU279 1137 0000 40F00100 orr r0, r0, #1 1138 .LVL75: 1139 .loc 1 433 13 view .LVU280 1140 0004 034B ldr r3, .L80 1141 0006 C3F89400 str r0, [r3, #148] 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Ensure MPU setting take effects */ 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** __DSB(); 1142 .loc 1 436 3 is_stmt 1 view .LVU281 1143 .LBB62: 1144 .LBI62: 944:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1145 .loc 3 944 27 view .LVU282 1146 .LBB63: 1147 .loc 3 946 3 view .LVU283 1148 .syntax unified 1149 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1150 000a BFF34F8F dsb 0xF 1151 @ 0 "" 2 1152 .thumb 1153 .syntax unified 1154 .LBE63: 1155 .LBE62: 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** __ISB(); 1156 .loc 1 437 3 view .LVU284 1157 .LBB64: 1158 .LBI64: ARM GAS /tmp/ccDEPnZG.s page 82 933:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1159 .loc 3 933 27 view .LVU285 1160 .LBB65: 935:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1161 .loc 3 935 3 view .LVU286 1162 .syntax unified 1163 @ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1164 000e BFF36F8F isb 0xF 1165 @ 0 "" 2 1166 .thumb 1167 .syntax unified 1168 .LBE65: 1169 .LBE64: 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1170 .loc 1 438 1 is_stmt 0 view .LVU287 1171 0012 7047 bx lr 1172 .L81: 1173 .align 2 1174 .L80: 1175 0014 00ED00E0 .word -536810240 1176 .cfi_endproc 1177 .LFE344: 1179 .section .text.HAL_MPU_Disable,"ax",%progbits 1180 .align 1 1181 .global HAL_MPU_Disable 1182 .syntax unified 1183 .thumb 1184 .thumb_func 1186 HAL_MPU_Disable: 1187 .LFB345: 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Disable the MPU. 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_Disable(void) 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 1188 .loc 1 446 1 is_stmt 1 view -0 1189 .cfi_startproc 1190 @ args = 0, pretend = 0, frame = 0 1191 @ frame_needed = 0, uses_anonymous_args = 0 1192 @ link register save eliminated. 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Make sure outstanding transfers are done */ 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** __DMB(); 1193 .loc 1 448 3 view .LVU289 1194 .LBB66: 1195 .LBI66: 947:Drivers/CMSIS/Include/cmsis_gcc.h **** } 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 953:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 954:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) ARM GAS /tmp/ccDEPnZG.s page 83 1196 .loc 3 955 27 view .LVU290 1197 .LBB67: 956:Drivers/CMSIS/Include/cmsis_gcc.h **** { 957:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 1198 .loc 3 957 3 view .LVU291 1199 .syntax unified 1200 @ 957 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1201 0000 BFF35F8F dmb 0xF 1202 @ 0 "" 2 1203 .thumb 1204 .syntax unified 1205 .LBE67: 1206 .LBE66: 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Disable the MPU and clear the control register*/ 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->CTRL = 0; 1207 .loc 1 451 3 view .LVU292 1208 .loc 1 451 14 is_stmt 0 view .LVU293 1209 0004 024B ldr r3, .L83 1210 0006 0022 movs r2, #0 1211 0008 C3F89420 str r2, [r3, #148] 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1212 .loc 1 452 1 view .LVU294 1213 000c 7047 bx lr 1214 .L84: 1215 000e 00BF .align 2 1216 .L83: 1217 0010 00ED00E0 .word -536810240 1218 .cfi_endproc 1219 .LFE345: 1221 .section .text.HAL_MPU_EnableRegion,"ax",%progbits 1222 .align 1 1223 .global HAL_MPU_EnableRegion 1224 .syntax unified 1225 .thumb 1226 .thumb_func 1228 HAL_MPU_EnableRegion: 1229 .LVL76: 1230 .LFB346: 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Enable the MPU Region. 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_EnableRegion(uint32_t RegionNumber) 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 1231 .loc 1 459 1 is_stmt 1 view -0 1232 .cfi_startproc 1233 @ args = 0, pretend = 0, frame = 0 1234 @ frame_needed = 0, uses_anonymous_args = 0 1235 @ link register save eliminated. 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); 1236 .loc 1 461 3 view .LVU296 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Set the Region number */ 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RNR = RegionNumber; ARM GAS /tmp/ccDEPnZG.s page 84 1237 .loc 1 464 3 view .LVU297 1238 .loc 1 464 12 is_stmt 0 view .LVU298 1239 0000 044B ldr r3, .L86 1240 0002 C3F89800 str r0, [r3, #152] 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Enable the Region */ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 1241 .loc 1 467 3 is_stmt 1 view .LVU299 1242 0006 D3F8A020 ldr r2, [r3, #160] 1243 000a 42F00102 orr r2, r2, #1 1244 000e C3F8A020 str r2, [r3, #160] 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1245 .loc 1 468 1 is_stmt 0 view .LVU300 1246 0012 7047 bx lr 1247 .L87: 1248 .align 2 1249 .L86: 1250 0014 00ED00E0 .word -536810240 1251 .cfi_endproc 1252 .LFE346: 1254 .section .text.HAL_MPU_DisableRegion,"ax",%progbits 1255 .align 1 1256 .global HAL_MPU_DisableRegion 1257 .syntax unified 1258 .thumb 1259 .thumb_func 1261 HAL_MPU_DisableRegion: 1262 .LVL77: 1263 .LFB347: 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Disable the MPU Region. 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_DisableRegion(uint32_t RegionNumber) 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 1264 .loc 1 475 1 is_stmt 1 view -0 1265 .cfi_startproc 1266 @ args = 0, pretend = 0, frame = 0 1267 @ frame_needed = 0, uses_anonymous_args = 0 1268 @ link register save eliminated. 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); 1269 .loc 1 477 3 view .LVU302 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Set the Region number */ 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RNR = RegionNumber; 1270 .loc 1 480 3 view .LVU303 1271 .loc 1 480 12 is_stmt 0 view .LVU304 1272 0000 044B ldr r3, .L89 1273 0002 C3F89800 str r0, [r3, #152] 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Disable the Region */ 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 1274 .loc 1 483 3 is_stmt 1 view .LVU305 1275 0006 D3F8A020 ldr r2, [r3, #160] 1276 000a 22F00102 bic r2, r2, #1 ARM GAS /tmp/ccDEPnZG.s page 85 1277 000e C3F8A020 str r2, [r3, #160] 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1278 .loc 1 484 1 is_stmt 0 view .LVU306 1279 0012 7047 bx lr 1280 .L90: 1281 .align 2 1282 .L89: 1283 0014 00ED00E0 .word -536810240 1284 .cfi_endproc 1285 .LFE347: 1287 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits 1288 .align 1 1289 .global HAL_MPU_ConfigRegion 1290 .syntax unified 1291 .thumb 1292 .thumb_func 1294 HAL_MPU_ConfigRegion: 1295 .LVL78: 1296 .LFB348: 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /** 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @brief Initialize and configure the Region and the memory to be protected. 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * the initialization and configuration information. 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** * @retval None 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** */ 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** { 1297 .loc 1 493 1 is_stmt 1 view -0 1298 .cfi_startproc 1299 @ args = 0, pretend = 0, frame = 0 1300 @ frame_needed = 0, uses_anonymous_args = 0 1301 @ link register save eliminated. 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Check the parameters */ 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); 1302 .loc 1 495 3 view .LVU308 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); 1303 .loc 1 496 3 view .LVU309 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); 1304 .loc 1 497 3 view .LVU310 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); 1305 .loc 1 498 3 view .LVU311 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); 1306 .loc 1 499 3 view .LVU312 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); 1307 .loc 1 500 3 view .LVU313 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); 1308 .loc 1 501 3 view .LVU314 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); 1309 .loc 1 502 3 view .LVU315 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); 1310 .loc 1 503 3 view .LVU316 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); 1311 .loc 1 504 3 view .LVU317 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Set the Region number */ 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; 1312 .loc 1 506 3 view .LVU318 ARM GAS /tmp/ccDEPnZG.s page 86 1313 .loc 1 506 22 is_stmt 0 view .LVU319 1314 0000 4378 ldrb r3, [r0, #1] @ zero_extendqisi2 1315 .loc 1 506 12 view .LVU320 1316 0002 144A ldr r2, .L92 1317 0004 C2F89830 str r3, [r2, #152] 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Disable the Region */ 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 1318 .loc 1 509 3 is_stmt 1 view .LVU321 1319 0008 D2F8A030 ldr r3, [r2, #160] 1320 000c 23F00103 bic r3, r3, #1 1321 0010 C2F8A030 str r3, [r2, #160] 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** /* Apply configuration */ 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; 1322 .loc 1 512 3 view .LVU322 1323 .loc 1 512 23 is_stmt 0 view .LVU323 1324 0014 4368 ldr r3, [r0, #4] 1325 .loc 1 512 13 view .LVU324 1326 0016 C2F89C30 str r3, [r2, #156] 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 1327 .loc 1 513 3 is_stmt 1 view .LVU325 1328 .loc 1 513 34 is_stmt 0 view .LVU326 1329 001a 017B ldrb r1, [r0, #12] @ zero_extendqisi2 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 1330 .loc 1 514 34 view .LVU327 1331 001c C37A ldrb r3, [r0, #11] @ zero_extendqisi2 1332 .loc 1 514 60 view .LVU328 1333 001e 1B06 lsls r3, r3, #24 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 1334 .loc 1 513 82 view .LVU329 1335 0020 43EA0173 orr r3, r3, r1, lsl #28 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 1336 .loc 1 515 34 view .LVU330 1337 0024 817A ldrb r1, [r0, #10] @ zero_extendqisi2 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 1338 .loc 1 514 82 view .LVU331 1339 0026 43EAC143 orr r3, r3, r1, lsl #19 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 1340 .loc 1 516 34 view .LVU332 1341 002a 417B ldrb r1, [r0, #13] @ zero_extendqisi2 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 1342 .loc 1 515 82 view .LVU333 1343 002c 43EA8143 orr r3, r3, r1, lsl #18 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 1344 .loc 1 517 34 view .LVU334 1345 0030 817B ldrb r1, [r0, #14] @ zero_extendqisi2 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 1346 .loc 1 516 82 view .LVU335 1347 0032 43EA4143 orr r3, r3, r1, lsl #17 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 1348 .loc 1 518 34 view .LVU336 1349 0036 C17B ldrb r1, [r0, #15] @ zero_extendqisi2 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 1350 .loc 1 517 82 view .LVU337 1351 0038 43EA0143 orr r3, r3, r1, lsl #16 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ARM GAS /tmp/ccDEPnZG.s page 87 1352 .loc 1 519 34 view .LVU338 1353 003c 417A ldrb r1, [r0, #9] @ zero_extendqisi2 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 1354 .loc 1 518 82 view .LVU339 1355 003e 43EA0123 orr r3, r3, r1, lsl #8 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 1356 .loc 1 520 34 view .LVU340 1357 0042 017A ldrb r1, [r0, #8] @ zero_extendqisi2 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 1358 .loc 1 519 82 view .LVU341 1359 0044 43EA4103 orr r3, r3, r1, lsl #1 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 1360 .loc 1 521 34 view .LVU342 1361 0048 0178 ldrb r1, [r0] @ zero_extendqisi2 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 1362 .loc 1 520 82 view .LVU343 1363 004a 0B43 orrs r3, r3, r1 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 1364 .loc 1 513 13 view .LVU344 1365 004c C2F8A030 str r3, [r2, #160] 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c **** } 1366 .loc 1 522 1 view .LVU345 1367 0050 7047 bx lr 1368 .L93: 1369 0052 00BF .align 2 1370 .L92: 1371 0054 00ED00E0 .word -536810240 1372 .cfi_endproc 1373 .LFE348: 1375 .text 1376 .Letext0: 1377 .file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h" 1378 .file 5 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach 1379 .file 6 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/ 1380 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h" ARM GAS /tmp/ccDEPnZG.s page 88 DEFINED SYMBOLS *ABS*:00000000 stm32g4xx_hal_cortex.c /tmp/ccDEPnZG.s:21 .text.__NVIC_EnableIRQ:00000000 $t /tmp/ccDEPnZG.s:26 .text.__NVIC_EnableIRQ:00000000 __NVIC_EnableIRQ /tmp/ccDEPnZG.s:60 .text.__NVIC_EnableIRQ:00000018 $d /tmp/ccDEPnZG.s:65 .text.__NVIC_DisableIRQ:00000000 $t /tmp/ccDEPnZG.s:70 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ /tmp/ccDEPnZG.s:131 .text.__NVIC_DisableIRQ:00000020 $d /tmp/ccDEPnZG.s:136 .text.__NVIC_SetPriority:00000000 $t /tmp/ccDEPnZG.s:141 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority /tmp/ccDEPnZG.s:188 .text.__NVIC_SetPriority:00000024 $d /tmp/ccDEPnZG.s:193 .text.__NVIC_GetPriority:00000000 $t /tmp/ccDEPnZG.s:198 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority /tmp/ccDEPnZG.s:238 .text.__NVIC_GetPriority:00000020 $d /tmp/ccDEPnZG.s:243 .text.NVIC_EncodePriority:00000000 $t /tmp/ccDEPnZG.s:248 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority /tmp/ccDEPnZG.s:310 .text.NVIC_DecodePriority:00000000 $t /tmp/ccDEPnZG.s:315 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority /tmp/ccDEPnZG.s:384 .text.__NVIC_SystemReset:00000000 $t /tmp/ccDEPnZG.s:389 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset /tmp/ccDEPnZG.s:450 .text.__NVIC_SystemReset:0000001c $d /tmp/ccDEPnZG.s:456 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t /tmp/ccDEPnZG.s:462 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping /tmp/ccDEPnZG.s:516 .text.HAL_NVIC_SetPriorityGrouping:00000020 $d /tmp/ccDEPnZG.s:521 .text.HAL_NVIC_SetPriority:00000000 $t /tmp/ccDEPnZG.s:527 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority /tmp/ccDEPnZG.s:576 .text.HAL_NVIC_SetPriority:0000001c $d /tmp/ccDEPnZG.s:581 .text.HAL_NVIC_EnableIRQ:00000000 $t /tmp/ccDEPnZG.s:587 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ /tmp/ccDEPnZG.s:610 .text.HAL_NVIC_DisableIRQ:00000000 $t /tmp/ccDEPnZG.s:616 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ /tmp/ccDEPnZG.s:639 .text.HAL_NVIC_SystemReset:00000000 $t /tmp/ccDEPnZG.s:645 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset /tmp/ccDEPnZG.s:664 .text.HAL_SYSTICK_Config:00000000 $t /tmp/ccDEPnZG.s:670 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config /tmp/ccDEPnZG.s:735 .text.HAL_SYSTICK_Config:00000024 $d /tmp/ccDEPnZG.s:740 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t /tmp/ccDEPnZG.s:746 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping /tmp/ccDEPnZG.s:770 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d /tmp/ccDEPnZG.s:775 .text.HAL_NVIC_GetPriority:00000000 $t /tmp/ccDEPnZG.s:781 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority /tmp/ccDEPnZG.s:816 .text.HAL_NVIC_SetPendingIRQ:00000000 $t /tmp/ccDEPnZG.s:822 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ /tmp/ccDEPnZG.s:864 .text.HAL_NVIC_SetPendingIRQ:00000018 $d /tmp/ccDEPnZG.s:869 .text.HAL_NVIC_GetPendingIRQ:00000000 $t /tmp/ccDEPnZG.s:875 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ /tmp/ccDEPnZG.s:921 .text.HAL_NVIC_GetPendingIRQ:00000020 $d /tmp/ccDEPnZG.s:926 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t /tmp/ccDEPnZG.s:932 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ /tmp/ccDEPnZG.s:974 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d /tmp/ccDEPnZG.s:979 .text.HAL_NVIC_GetActive:00000000 $t /tmp/ccDEPnZG.s:985 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive /tmp/ccDEPnZG.s:1030 .text.HAL_NVIC_GetActive:00000020 $d /tmp/ccDEPnZG.s:1035 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t /tmp/ccDEPnZG.s:1041 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig /tmp/ccDEPnZG.s:1076 .text.HAL_SYSTICK_Callback:00000000 $t /tmp/ccDEPnZG.s:1082 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback ARM GAS /tmp/ccDEPnZG.s page 89 /tmp/ccDEPnZG.s:1095 .text.HAL_SYSTICK_IRQHandler:00000000 $t /tmp/ccDEPnZG.s:1101 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler /tmp/ccDEPnZG.s:1121 .text.HAL_MPU_Enable:00000000 $t /tmp/ccDEPnZG.s:1127 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable /tmp/ccDEPnZG.s:1175 .text.HAL_MPU_Enable:00000014 $d /tmp/ccDEPnZG.s:1180 .text.HAL_MPU_Disable:00000000 $t /tmp/ccDEPnZG.s:1186 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable /tmp/ccDEPnZG.s:1217 .text.HAL_MPU_Disable:00000010 $d /tmp/ccDEPnZG.s:1222 .text.HAL_MPU_EnableRegion:00000000 $t /tmp/ccDEPnZG.s:1228 .text.HAL_MPU_EnableRegion:00000000 HAL_MPU_EnableRegion /tmp/ccDEPnZG.s:1250 .text.HAL_MPU_EnableRegion:00000014 $d /tmp/ccDEPnZG.s:1255 .text.HAL_MPU_DisableRegion:00000000 $t /tmp/ccDEPnZG.s:1261 .text.HAL_MPU_DisableRegion:00000000 HAL_MPU_DisableRegion /tmp/ccDEPnZG.s:1283 .text.HAL_MPU_DisableRegion:00000014 $d /tmp/ccDEPnZG.s:1288 .text.HAL_MPU_ConfigRegion:00000000 $t /tmp/ccDEPnZG.s:1294 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion /tmp/ccDEPnZG.s:1371 .text.HAL_MPU_ConfigRegion:00000054 $d NO UNDEFINED SYMBOLS