ARM GAS /tmp/ccnQFf6s.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "stm32g4xx_hal_uart_ex.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c" 20 .section .text.UARTEx_Wakeup_AddressConfig,"ax",%progbits 21 .align 1 22 .syntax unified 23 .thumb 24 .thumb_func 26 UARTEx_Wakeup_AddressConfig: 27 .LVL0: 28 .LFB345: 1:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 2:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ****************************************************************************** 3:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @file stm32g4xx_hal_uart_ex.c 4:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @author MCD Application Team 5:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended UART HAL module driver. 6:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This file provides firmware functions to manage the following extended 7:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). 8:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * + Initialization and de-initialization functions 9:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * + Peripheral Control functions 10:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 11:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 12:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ****************************************************************************** 13:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @attention 14:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 15:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * Copyright (c) 2019 STMicroelectronics. 16:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * All rights reserved. 17:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 18:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This software is licensed under terms that can be found in the LICENSE file 19:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * in the root directory of this software component. 20:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 21:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 22:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ****************************************************************************** 23:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim 24:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ============================================================================== 25:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### UART peripheral extended features ##### 26:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ============================================================================== 27:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 28:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Declare a UART_HandleTypeDef handle structure. 29:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 30:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) For the UART RS485 Driver Enable mode, initialize the UART registers ARM GAS /tmp/ccnQFf6s.s page 2 31:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** by calling the HAL_RS485Ex_Init() API. 32:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 33:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. 34:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 35:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** -@- When UART operates in FIFO mode, FIFO mode must be enabled prior 36:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** starting RX/TX transfers. Also RX/TX FIFO thresholds must be 37:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** configured prior starting RX/TX transfers. 38:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 39:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim 40:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ****************************************************************************** 41:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 42:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 43:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Includes ------------------------------------------------------------------*/ 44:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #include "stm32g4xx_hal.h" 45:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 46:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @addtogroup STM32G4xx_HAL_Driver 47:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 48:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 49:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 50:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx UARTEx 51:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART Extended HAL module driver 52:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 53:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 54:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 55:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #ifdef HAL_UART_MODULE_ENABLED 56:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 57:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private typedef -----------------------------------------------------------*/ 58:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private define ------------------------------------------------------------*/ 59:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEX_Private_Constants UARTEx Private Constants 60:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 61:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 62:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* UART RX FIFO depth */ 63:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #define RX_FIFO_DEPTH 8U 64:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 65:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* UART TX FIFO depth */ 66:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #define TX_FIFO_DEPTH 8U 67:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 68:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @} 69:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 70:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 71:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private macros ------------------------------------------------------------*/ 72:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private variables ---------------------------------------------------------*/ 73:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Private function prototypes -----------------------------------------------*/ 74:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Private_Functions UARTEx Private Functions 75:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 76:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 77:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti 78:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); 79:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 80:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @} 81:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 82:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 83:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Exported functions --------------------------------------------------------*/ 84:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 85:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions 86:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 87:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ ARM GAS /tmp/ccnQFf6s.s page 3 88:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 89:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions 90:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended Initialization and Configuration Functions 91:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 92:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim 93:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** =============================================================================== 94:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### Initialization and Configuration functions ##### 95:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** =============================================================================== 96:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..] 97:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 98:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** in asynchronous mode. 99:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) For the asynchronous mode the parameters below can be configured: 100:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Baud Rate 101:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Word Length 102:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Stop Bit 103:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Parity: If the parity is enabled, then the MSB bit of the data written 104:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** in the data register is transmitted but is changed by the parity bit. 105:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Hardware flow control 106:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Receiver/transmitter modes 107:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) Over Sampling Method 108:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) One-Bit Sampling Method 109:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) For the asynchronous mode, the following advanced features can be configured as well: 110:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) TX and/or RX pin level inversion 111:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) data logical level inversion 112:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX and TX pins swap 113:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX overrun detection disabling 114:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) DMA disabling on RX error 115:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) MSB first on communication line 116:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) auto Baud rate detection 117:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..] 118:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration 119:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** procedures (details for the procedures are available in reference manual). 120:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 121:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim 122:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 123:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Depending on the frame length defined by the M1 and M0 bits (7-bit, 124:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 8-bit or 9-bit), the possible UART formats are listed in the 125:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** following table. 126:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 127:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Table 1. UART frame format. 128:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ 129:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | M1 bit | M0 bit | PCE bit | UART frame | 130:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| 131:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 0 | 0 | | SB | 8 bit data | STB | | 132:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| 133:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | 134:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| 135:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 1 | 0 | | SB | 9 bit data | STB | | 136:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| 137:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | 138:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| 139:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 1 | 0 | 0 | | SB | 7 bit data | STB | | 140:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| 141:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | 142:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ 143:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 144:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ ARM GAS /tmp/ccnQFf6s.s page 4 145:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 146:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 147:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 148:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Initialize the RS485 Driver enable feature according to the specified 149:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * parameters in the UART_InitTypeDef and creates the associated handle. 150:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 151:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Polarity Select the driver enable polarity. 152:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values: 153:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high 154:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_LOW DE signal is active low 155:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param AssertionTime Driver Enable assertion time: 156:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 5-bit value defining the time between the activation of the DE (Driver Enable) 157:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * signal and the beginning of the start bit. It is expressed in sample time 158:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * units (1/8 or 1/16 bit time, depending on the oversampling rate) 159:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param DeassertionTime Driver Enable deassertion time: 160:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 5-bit value defining the time between the end of the last stop bit, in a 161:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * transmitted message, and the de-activation of the DE (Driver Enable) signal. 162:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the 163:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * oversampling rate). 164:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 165:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 166:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t Assertion 167:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t DeassertionTime) 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t temp; 170:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 171:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */ 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart == NULL) 173:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR; 175:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 176:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable UART instance */ 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); 178:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 179:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable polarity */ 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_DE_POLARITY(Polarity)); 181:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 182:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable assertion time */ 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); 184:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 185:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the Driver Enable deassertion time */ 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); 187:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->gState == HAL_UART_STATE_RESET) 189:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 190:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Allocate lock resource and initialize it */ 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->Lock = HAL_UNLOCKED; 192:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 193:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) 194:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UART_InitCallbacksToDefault(huart); 195:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 196:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->MspInitCallback == NULL) 197:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 198:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->MspInitCallback = HAL_UART_MspInit; 199:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 200:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 201:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init the low level hardware */ ARM GAS /tmp/ccnQFf6s.s page 5 202:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->MspInitCallback(huart); 203:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #else 204:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX */ 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_UART_MspInit(huart); 206:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ 207:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 208:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; 210:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 211:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable the Peripheral */ 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); 213:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 214:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Perform advanced settings configuration */ 215:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* For some items, configuration requires to be done prior TE and RE bits are set */ 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 217:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UART_AdvFeatureConfig(huart); 219:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 220:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 221:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the UART Communication parameters */ 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (UART_SetConfig(huart) == HAL_ERROR) 223:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 224:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR; 225:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 226:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 227:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DEM); 229:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 230:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the Driver Enable polarity */ 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); 232:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 233:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the Driver Enable assertion and deassertion times */ 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); 237:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 238:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Peripheral */ 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); 240:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 241:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 244:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 245:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 246:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @} 247:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 248:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 249:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions 250:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended functions 251:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 252:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim 253:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** =============================================================================== 254:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### IO operation functions ##### 255:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** =============================================================================== 256:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** This subsection provides a set of Wakeup and FIFO mode related callback functions. 257:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 258:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Wakeup from Stop mode Callback: ARM GAS /tmp/ccnQFf6s.s page 6 259:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_WakeupCallback() 260:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 261:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) TX/RX Fifos Callbacks: 262:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_RxFifoFullCallback() 263:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_TxFifoEmptyCallback() 264:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 265:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim 266:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 267:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 268:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 269:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 270:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART wakeup from Stop mode callback. 271:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 272:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None 273:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 274:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 276:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UNUSED(huart); 278:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 279:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, 280:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** the HAL_UARTEx_WakeupCallback can be implemented in the user file. 281:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 283:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 284:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 285:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART RX Fifo full callback. 286:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 287:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None 288:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 289:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 291:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UNUSED(huart); 293:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 294:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, 295:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. 296:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 298:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 299:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 300:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief UART TX Fifo empty callback. 301:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 302:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None 303:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 304:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 306:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UNUSED(huart); 308:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 309:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, 310:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. 311:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 313:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 314:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 315:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @} ARM GAS /tmp/ccnQFf6s.s page 7 316:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 317:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 318:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions 319:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Extended Peripheral Control functions 320:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 321:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @verbatim 322:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** =============================================================================== 323:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ##### Peripheral Control functions ##### 324:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** =============================================================================== 325:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..] This section provides the following functions: 326:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address 327:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** detection length to more than 4 bits for multiprocessor address mark wake up. 328:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode 329:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** trigger: address match, Start Bit detection or RXNE bit status. 330:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode 331:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableStopMode() API disables the above functionality 332:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode 333:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode 334:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold 335:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold 336:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 337:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** [..] This subsection also provides a set of additional functions providing enhanced reception 338:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** services to user. (For example, these functions allow application to handle use cases 339:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** where number of data to be received is unknown). 340:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 341:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Compared to standard reception services which only consider number of received 342:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** data elements as reception completion criteria, these functions also consider additional ev 343:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** as triggers for updating reception status to caller : 344:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Detection of inactivity period (RX line has not been active for a given period). 345:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally 346:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** for 1 frame time, after last received byte. 347:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (++) RX inactivity detected by RTO, i.e. line has been in idle state 348:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** for a programmable time, after last received byte. 349:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Detection that a specific character has been received. 350:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 351:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) There are two mode of transfer: 352:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Blocking mode: The reception is performed in polling mode, until either expected number 353:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** or till IDLE event occurs. Reception is handled only during function execution. 354:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** When function exits, no data reception could occur. HAL status and number of actually re 355:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** are returned by function after finishing transfer. 356:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. 357:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** These API's return the HAL status. 358:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The end of the data processing will be indicated through the 359:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. 360:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process 361:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** The HAL_UART_ErrorCallback()user callback will be executed when a reception error is det 362:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 363:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Blocking mode API: 364:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle() 365:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 366:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Non-Blocking mode API with Interrupt: 367:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle_IT() 368:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 369:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (#) Non-Blocking mode API with DMA: 370:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle_DMA() 371:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 372:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** @endverbatim ARM GAS /tmp/ccnQFf6s.s page 8 373:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 374:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 375:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 376:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 377:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief By default in multiprocessor mode, when the wake up method is set 378:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * to address mark, the UART handles only 4-bit long addresses detection; 379:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * this API allows to enable longer addresses detection (6-, 7- or 8-bit 380:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * long). 381:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 382:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. 383:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 384:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param AddressLength This parameter can be one of the following values: 385:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address 386:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address 387:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 388:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 389:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t Addres 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 391:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */ 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart == NULL) 393:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR; 395:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 396:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 397:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the address length parameter */ 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); 399:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; 401:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 402:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable the Peripheral */ 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); 404:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 405:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the address length */ 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); 407:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 408:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Peripheral */ 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); 410:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 411:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState to Ready */ 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 414:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 415:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 416:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Set Wakeup from Stop mode interrupt flag selection. 417:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note It is the application responsibility to enable the interrupt used as 418:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * usart_wkup interrupt source before entering low-power mode. 419:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 420:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. 421:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values: 422:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_ADDRESS 423:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_STARTBIT 424:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY 425:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 426:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 427:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeD 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; ARM GAS /tmp/ccnQFf6s.s page 9 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart; 431:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 432:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* check the wake-up from stop mode UART instance */ 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); 434:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* check the wake-up selection parameter */ 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); 436:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 437:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart); 439:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; 441:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 442:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable the Peripheral */ 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); 444:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 445:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the wake-up selection scheme */ 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); 447:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) 449:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); 451:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 452:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 453:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable the Peripheral */ 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); 455:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 456:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init tickstart for timeout management */ 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tickstart = HAL_GetTick(); 458:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 459:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Wait until REACK flag is set */ 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) 461:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = HAL_TIMEOUT; 463:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 464:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 465:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 466:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Initialize the UART State */ 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; 468:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 469:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 470:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */ 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); 472:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return status; 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 475:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 476:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 477:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Enable UART Stop Mode. 478:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. 479:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 480:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 481:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 482:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 484:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart); 486:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ARM GAS /tmp/ccnQFf6s.s page 10 487:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set UESM bit */ 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); 489:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 490:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */ 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); 492:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 495:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 496:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 497:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Disable UART Stop Mode. 498:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 499:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 500:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 501:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 503:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart); 505:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 506:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Clear UESM bit */ 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); 508:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 509:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */ 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); 511:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 514:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 515:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 516:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Enable the FIFO mode. 517:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 518:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 519:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 520:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 523:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 524:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check parameters */ 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); 526:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 527:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart); 529:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; 531:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 532:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */ 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); 534:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 535:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */ 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); 537:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 538:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Enable FIFO mode */ 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** SET_BIT(tmpcr1, USART_CR1_FIFOEN); 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_ENABLE; 541:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 542:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */ 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); ARM GAS /tmp/ccnQFf6s.s page 11 544:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 545:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */ 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart); 547:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; 549:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 550:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */ 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); 552:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 555:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 556:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 557:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Disable the FIFO mode. 558:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 559:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 560:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 561:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 564:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 565:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check parameters */ 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); 567:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 568:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart); 570:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; 572:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 573:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */ 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); 575:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 576:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */ 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); 578:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 579:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable FIFO mode */ 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_DISABLE; 582:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 583:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */ 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); 585:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; 587:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 588:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */ 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); 590:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 593:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 594:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 595:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Set the TXFIFO threshold. 596:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 597:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Threshold TX FIFO threshold value 598:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values: 599:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_8 600:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_4 ARM GAS /tmp/ccnQFf6s.s page 12 601:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_2 602:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_3_4 603:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_7_8 604:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_8_8 605:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 606:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 607:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 610:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 611:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check parameters */ 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); 614:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 615:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart); 617:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; 619:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 620:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */ 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); 622:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 623:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */ 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); 625:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 626:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Update TX threshold configuration */ 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 628:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 629:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */ 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart); 631:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 632:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */ 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); 634:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; 636:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 637:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */ 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); 639:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 642:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 643:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 644:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Set the RXFIFO threshold. 645:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 646:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Threshold RX FIFO threshold value 647:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * This parameter can be one of the following values: 648:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_8 649:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_4 650:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_2 651:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_3_4 652:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_7_8 653:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_8_8 654:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 655:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 656:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { ARM GAS /tmp/ccnQFf6s.s page 13 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 659:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 660:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the parameters */ 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); 663:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 664:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_LOCK(huart); 666:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; 668:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 669:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Save actual UART configuration */ 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); 671:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 672:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Disable UART */ 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); 674:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 675:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Update RX threshold configuration */ 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 677:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 678:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */ 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart); 680:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 681:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Restore UART configuration */ 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); 683:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; 685:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 686:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Unlocked */ 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); 688:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 691:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 692:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 693:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Receive an amount of data in blocking mode till either the expected number of data 694:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * is received or an IDLE event occurs. 695:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note HAL_OK is returned if reception is completed (expected number of data has been received) 696:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * or if reception is stopped after IDLE event (less than the expected number of data has b 697:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * In this case, RxLen output parameter indicates number of data available in reception buf 698:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M 699:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the 700:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of uint16_t available through pData. 701:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO 702:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * is not empty. Read operations from the RDR register are performed when 703:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * RXFNE flag is set. From hardware perspective, RXFNE flag and 704:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * RXNE are mapped on the same bit-field. 705:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 706:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). 707:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received. 708:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param RxLen Number of data elements finally received 709:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * (could be lower than Size, in case reception ends on IDLE event) 710:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). 711:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 712:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 713:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size 714:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t Timeout) ARM GAS /tmp/ccnQFf6s.s page 14 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t *pdata8bits; 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t *pdata16bits; 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t uhMask; 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart; 720:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 721:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */ 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY) 723:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U)) 725:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR; 727:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 728:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 733:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 734:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Init tickstart for timeout management */ 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tickstart = HAL_GetTick(); 736:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferSize = Size; 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount = Size; 739:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 740:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Computation of UART mask to apply to RDR register */ 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** UART_MASK_COMPUTATION(huart); 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 743:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 744:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 746:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits = NULL; 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData; 749:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 750:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 751:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 752:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits = pData; 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = NULL; 754:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 755:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 756:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Initialize output number of received elements */ 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *RxLen = 0U; 758:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 759:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* as long as data have to be received */ 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** while (huart->RxXferCount > 0U) 761:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 762:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check if IDLE flag is set */ 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) 764:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 765:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Clear IDLE flag in ISR */ 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 767:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 768:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* If Set, but no data ever received, clear flag without exiting loop */ 769:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* If Set, and data has already been received, this means Idle Event is valid : End recepti 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (*RxLen > 0U) 771:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { ARM GAS /tmp/ccnQFf6s.s page 15 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_IDLE; 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; 774:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 776:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 777:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 778:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 779:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check if RXNE flag is set */ 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) 781:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (pdata8bits == NULL) 783:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++; 786:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 787:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 788:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++; 791:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 792:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Increment number of received elements */ 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *RxLen += 1U; 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount--; 795:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 796:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 797:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check for the Timeout */ 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (Timeout != HAL_MAX_DELAY) 799:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 801:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; 803:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_TIMEOUT; 805:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 806:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 807:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 808:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 809:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set number of received elements in output parameter : RxLen */ 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** *RxLen = huart->RxXferSize - huart->RxXferCount; 811:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; 813:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_OK; 815:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 816:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 817:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_BUSY; 819:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 821:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 822:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 823:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Receive an amount of data in interrupt mode till either the expected number of data 824:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * is received or an IDLE event occurs. 825:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note Reception is initiated by this function call. Further progress of reception is achieved 826:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of receptio 827:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * number of received data elements. 828:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M ARM GAS /tmp/ccnQFf6s.s page 16 829:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the 830:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of uint16_t available through pData. 831:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 832:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). 833:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received. 834:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 835:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 836:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t S 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; 839:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 840:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */ 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY) 842:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U)) 844:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR; 846:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 847:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 848:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set Reception type to reception till IDLE Event*/ 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 851:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (void)UART_Start_Receive_IT(huart, pData, Size); 853:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 855:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 858:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 859:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 860:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 861:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* In case of errors already pending when reception is started, 862:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Interrupts may have already been raised and lead to reception abortion. 863:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (Overrun error for instance). 864:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = HAL_ERROR; 866:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 867:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return status; 869:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 870:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 871:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_BUSY; 873:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 875:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 876:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 877:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Receive an amount of data in DMA mode till either the expected number 878:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of data is received or an IDLE event occurs. 879:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note Reception is initiated by this function call. Further progress of reception is achieved 880:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * to DMA services, transferring automatically received data elements in user reception buf 881:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * calling registered callbacks at half/end of reception. UART IDLE events are also used to 882:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * reception phase as ended. In all cases, callback execution will indicate number of recei 883:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When the UART parity is enabled (PCE = 1), the received data contain 884:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the parity bit (MSB position). 885:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M ARM GAS /tmp/ccnQFf6s.s page 17 886:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the 887:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of uint16_t available through pData. 888:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 889:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). 890:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received. 891:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval HAL status 892:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 893:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status; 896:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 897:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */ 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY) 899:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U)) 901:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_ERROR; 903:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 904:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 905:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set Reception type to reception till IDLE Event*/ 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 908:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = UART_Start_Receive_DMA(huart, pData, Size); 910:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 911:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check Rx process has been successfully started */ 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (status == HAL_OK) 913:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 915:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 918:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 919:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 920:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 921:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* In case of errors already pending when reception is started, 922:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** Interrupts may have already been raised and lead to reception abortion. 923:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (Overrun error for instance). 924:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** status = HAL_ERROR; 926:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 927:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 928:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return status; 930:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 931:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 932:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return HAL_BUSY; 934:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 936:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 937:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 938:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Provide Rx Event type that has lead to RxEvent callback execution. 939:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, pro 940:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * of reception process is provided to application through calls of Rx Event callback (eith 941:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could o 942:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type ARM GAS /tmp/ccnQFf6s.s page 18 943:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * to Rx Event callback execution. 944:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note This function is expected to be called within the user implementation of Rx Event Callba 945:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * in order to provide the accurate value : 946:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * In Interrupt Mode : 947:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has be 948:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed 949:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * received data is lower than expected one) 950:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * In DMA Mode : 951:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has be 952:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received 953:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed 954:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * received data is lower than expected one). 955:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * In DMA mode, RxEvent callback could be called several times; 956:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * When DMA is configured in Normal Mode, HT event does not stop Reception process; 957:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception proc 958:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 959:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) 960:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 961:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 963:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Return Rx Event type value, as stored in UART handle */ 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** return (huart->RxEventType); 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 966:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 967:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 968:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @} 969:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 970:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 971:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 972:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @} 973:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 974:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 975:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** @addtogroup UARTEx_Private_Functions 976:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @{ 977:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 978:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 979:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 980:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detectio 981:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 982:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param WakeUpSelection UART wake up from stop mode parameters. 983:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None 984:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 985:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti 986:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 29 .loc 1 986 1 view -0 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 8 32 @ frame_needed = 0, uses_anonymous_args = 0 33 @ link register save eliminated. 34 .loc 1 986 1 is_stmt 0 view .LVU1 35 0000 82B0 sub sp, sp, #8 36 .LCFI0: 37 .cfi_def_cfa_offset 8 38 0002 02AB add r3, sp, #8 39 0004 03E90600 stmdb r3, {r1, r2} 987:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); 40 .loc 1 987 3 is_stmt 1 view .LVU2 ARM GAS /tmp/ccnQFf6s.s page 19 988:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 989:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the USART address length */ 990:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); 41 .loc 1 990 3 view .LVU3 42 0008 0268 ldr r2, [r0] 43 000a 5368 ldr r3, [r2, #4] 44 000c 23F01003 bic r3, r3, #16 45 0010 BDF80410 ldrh r1, [sp, #4] 46 0014 0B43 orrs r3, r3, r1 47 0016 5360 str r3, [r2, #4] 991:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 992:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Set the USART address node */ 993:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_AD 48 .loc 1 993 3 view .LVU4 49 0018 0268 ldr r2, [r0] 50 001a 5368 ldr r3, [r2, #4] 51 001c 23F07F43 bic r3, r3, #-16777216 52 0020 9DF80610 ldrb r1, [sp, #6] @ zero_extendqisi2 53 0024 43EA0163 orr r3, r3, r1, lsl #24 54 0028 5360 str r3, [r2, #4] 994:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 55 .loc 1 994 1 is_stmt 0 view .LVU5 56 002a 02B0 add sp, sp, #8 57 .LCFI1: 58 .cfi_def_cfa_offset 0 59 @ sp needed 60 002c 7047 bx lr 61 .cfi_endproc 62 .LFE345: 64 .section .text.UARTEx_SetNbDataToProcess,"ax",%progbits 65 .align 1 66 .syntax unified 67 .thumb 68 .thumb_func 70 UARTEx_SetNbDataToProcess: 71 .LVL1: 72 .LFB346: 995:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 996:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /** 997:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @brief Calculate the number of data to process in RX/TX ISR. 998:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @note The RX FIFO depth and the TX FIFO depth is extracted from 999:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * the UART configuration registers. 1000:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @param huart UART handle. 1001:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** * @retval None 1002:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** */ 1003:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) 1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 73 .loc 1 1004 1 is_stmt 1 view -0 74 .cfi_startproc 75 @ args = 0, pretend = 0, frame = 0 76 @ frame_needed = 0, uses_anonymous_args = 0 77 @ link register save eliminated. 1005:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t rx_fifo_depth; 78 .loc 1 1005 3 view .LVU7 1006:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t tx_fifo_depth; 79 .loc 1 1006 3 view .LVU8 1007:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t rx_fifo_threshold; ARM GAS /tmp/ccnQFf6s.s page 20 80 .loc 1 1007 3 view .LVU9 1008:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t tx_fifo_threshold; 81 .loc 1 1008 3 view .LVU10 1009:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; 82 .loc 1 1009 3 view .LVU11 1010:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; 83 .loc 1 1010 3 view .LVU12 1011:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1012:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** if (huart->FifoMode == UART_FIFOMODE_DISABLE) 84 .loc 1 1012 3 view .LVU13 85 .loc 1 1012 12 is_stmt 0 view .LVU14 86 0000 436E ldr r3, [r0, #100] 87 .loc 1 1012 6 view .LVU15 88 0002 2BB9 cbnz r3, .L4 1013:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1014:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = 1U; 89 .loc 1 1014 5 is_stmt 1 view .LVU16 90 .loc 1 1014 30 is_stmt 0 view .LVU17 91 0004 0123 movs r3, #1 92 0006 A0F86A30 strh r3, [r0, #106] @ movhi 1015:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = 1U; 93 .loc 1 1015 5 is_stmt 1 view .LVU18 94 .loc 1 1015 30 is_stmt 0 view .LVU19 95 000a A0F86830 strh r3, [r0, #104] @ movhi 96 000e 7047 bx lr 97 .L4: 1004:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t rx_fifo_depth; 98 .loc 1 1004 1 view .LVU20 99 0010 30B4 push {r4, r5} 100 .LCFI2: 101 .cfi_def_cfa_offset 8 102 .cfi_offset 4, -8 103 .cfi_offset 5, -4 1016:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1017:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** else 1018:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1019:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** rx_fifo_depth = RX_FIFO_DEPTH; 104 .loc 1 1019 5 is_stmt 1 view .LVU21 105 .LVL2: 1020:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tx_fifo_depth = TX_FIFO_DEPTH; 106 .loc 1 1020 5 view .LVU22 1021:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RX 107 .loc 1 1021 5 view .LVU23 108 .loc 1 1021 35 is_stmt 0 view .LVU24 109 0012 0368 ldr r3, [r0] 110 0014 9A68 ldr r2, [r3, #8] 111 .loc 1 1021 23 view .LVU25 112 0016 C2F34262 ubfx r2, r2, #25, #3 113 .LVL3: 1022:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TX 114 .loc 1 1022 5 is_stmt 1 view .LVU26 115 .loc 1 1022 35 is_stmt 0 view .LVU27 116 001a 9968 ldr r1, [r3, #8] 117 .loc 1 1022 23 view .LVU28 118 001c 490F lsrs r1, r1, #29 119 .LVL4: 1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / ARM GAS /tmp/ccnQFf6s.s page 21 120 .loc 1 1023 5 is_stmt 1 view .LVU29 121 .loc 1 1023 68 is_stmt 0 view .LVU30 122 001e 094D ldr r5, .L9 123 0020 6B5C ldrb r3, [r5, r1] @ zero_extendqisi2 124 .loc 1 1023 57 view .LVU31 125 0022 DB00 lsls r3, r3, #3 1024:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (uint16_t)denominator[tx_fifo_threshold]; 126 .loc 1 1024 53 view .LVU32 127 0024 084C ldr r4, .L9+4 128 0026 615C ldrb r1, [r4, r1] @ zero_extendqisi2 129 .LVL5: 1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 130 .loc 1 1023 89 view .LVU33 131 0028 93FBF1F3 sdiv r3, r3, r1 1023:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 132 .loc 1 1023 30 view .LVU34 133 002c A0F86A30 strh r3, [r0, #106] @ movhi 1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 134 .loc 1 1025 5 is_stmt 1 view .LVU35 135 .loc 1 1025 68 is_stmt 0 view .LVU36 136 0030 AB5C ldrb r3, [r5, r2] @ zero_extendqisi2 137 .loc 1 1025 57 view .LVU37 138 0032 DB00 lsls r3, r3, #3 1026:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** (uint16_t)denominator[rx_fifo_threshold]; 139 .loc 1 1026 53 view .LVU38 140 0034 A25C ldrb r2, [r4, r2] @ zero_extendqisi2 141 .LVL6: 1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 142 .loc 1 1025 89 view .LVU39 143 0036 93FBF2F3 sdiv r3, r3, r2 1025:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 144 .loc 1 1025 30 view .LVU40 145 003a A0F86830 strh r3, [r0, #104] @ movhi 1027:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1028:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 146 .loc 1 1028 1 view .LVU41 147 003e 30BC pop {r4, r5} 148 .LCFI3: 149 .cfi_restore 5 150 .cfi_restore 4 151 .cfi_def_cfa_offset 0 152 0040 7047 bx lr 153 .L10: 154 0042 00BF .align 2 155 .L9: 156 0044 00000000 .word numerator.1 157 0048 00000000 .word denominator.0 158 .cfi_endproc 159 .LFE346: 161 .section .text.HAL_RS485Ex_Init,"ax",%progbits 162 .align 1 163 .global HAL_RS485Ex_Init 164 .syntax unified 165 .thumb 166 .thumb_func 168 HAL_RS485Ex_Init: 169 .LVL7: ARM GAS /tmp/ccnQFf6s.s page 22 170 .LFB329: 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t temp; 171 .loc 1 168 1 is_stmt 1 view -0 172 .cfi_startproc 173 @ args = 0, pretend = 0, frame = 0 174 @ frame_needed = 0, uses_anonymous_args = 0 169:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 175 .loc 1 169 3 view .LVU43 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 176 .loc 1 172 3 view .LVU44 172:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 177 .loc 1 172 6 is_stmt 0 view .LVU45 178 0000 0028 cmp r0, #0 179 0002 3CD0 beq .L15 168:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t temp; 180 .loc 1 168 1 view .LVU46 181 0004 F8B5 push {r3, r4, r5, r6, r7, lr} 182 .LCFI4: 183 .cfi_def_cfa_offset 24 184 .cfi_offset 3, -24 185 .cfi_offset 4, -20 186 .cfi_offset 5, -16 187 .cfi_offset 6, -12 188 .cfi_offset 7, -8 189 .cfi_offset 14, -4 190 0006 0F46 mov r7, r1 191 0008 1646 mov r6, r2 192 000a 1D46 mov r5, r3 193 000c 0446 mov r4, r0 177:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 194 .loc 1 177 3 is_stmt 1 view .LVU47 180:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 195 .loc 1 180 3 view .LVU48 183:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 196 .loc 1 183 3 view .LVU49 186:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 197 .loc 1 186 3 view .LVU50 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 198 .loc 1 188 3 view .LVU51 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 199 .loc 1 188 12 is_stmt 0 view .LVU52 200 000e D0F88830 ldr r3, [r0, #136] 201 .LVL8: 188:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 202 .loc 1 188 6 view .LVU53 203 0012 5BB3 cbz r3, .L20 204 .LVL9: 205 .L13: 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 206 .loc 1 209 3 is_stmt 1 view .LVU54 209:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 207 .loc 1 209 17 is_stmt 0 view .LVU55 208 0014 2423 movs r3, #36 209 0016 C4F88830 str r3, [r4, #136] 212:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 210 .loc 1 212 3 is_stmt 1 view .LVU56 211 001a 2268 ldr r2, [r4] ARM GAS /tmp/ccnQFf6s.s page 23 212 001c 1368 ldr r3, [r2] 213 001e 23F00103 bic r3, r3, #1 214 0022 1360 str r3, [r2] 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 215 .loc 1 216 3 view .LVU57 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 216 .loc 1 216 26 is_stmt 0 view .LVU58 217 0024 A36A ldr r3, [r4, #40] 216:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 218 .loc 1 216 6 view .LVU59 219 0026 33BB cbnz r3, .L21 220 .L14: 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 221 .loc 1 222 3 is_stmt 1 view .LVU60 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 222 .loc 1 222 7 is_stmt 0 view .LVU61 223 0028 2046 mov r0, r4 224 002a FFF7FEFF bl UART_SetConfig 225 .LVL10: 222:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 226 .loc 1 222 6 discriminator 1 view .LVU62 227 002e 0128 cmp r0, #1 228 0030 1BD0 beq .L12 228:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 229 .loc 1 228 3 is_stmt 1 view .LVU63 230 0032 2268 ldr r2, [r4] 231 0034 9368 ldr r3, [r2, #8] 232 0036 43F48043 orr r3, r3, #16384 233 003a 9360 str r3, [r2, #8] 231:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 234 .loc 1 231 3 view .LVU64 235 003c 2268 ldr r2, [r4] 236 003e 9368 ldr r3, [r2, #8] 237 0040 23F40043 bic r3, r3, #32768 238 0044 3B43 orrs r3, r3, r7 239 0046 9360 str r3, [r2, #8] 234:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); 240 .loc 1 234 3 view .LVU65 241 .LVL11: 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); 242 .loc 1 235 3 view .LVU66 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); 243 .loc 1 235 28 is_stmt 0 view .LVU67 244 0048 2D04 lsls r5, r5, #16 245 .LVL12: 235:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); 246 .loc 1 235 8 view .LVU68 247 004a 45EA4652 orr r2, r5, r6, lsl #21 248 .LVL13: 236:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 249 .loc 1 236 3 is_stmt 1 view .LVU69 250 004e 2168 ldr r1, [r4] 251 0050 0B68 ldr r3, [r1] 252 0052 6FF31943 bfc r3, #16, #10 253 0056 1343 orrs r3, r3, r2 254 0058 0B60 str r3, [r1] 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ARM GAS /tmp/ccnQFf6s.s page 24 255 .loc 1 239 3 view .LVU70 256 005a 2268 ldr r2, [r4] 257 .LVL14: 239:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 258 .loc 1 239 3 is_stmt 0 view .LVU71 259 005c 1368 ldr r3, [r2] 260 005e 43F00103 orr r3, r3, #1 261 0062 1360 str r3, [r2] 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 262 .loc 1 242 3 is_stmt 1 view .LVU72 242:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 263 .loc 1 242 11 is_stmt 0 view .LVU73 264 0064 2046 mov r0, r4 265 0066 FFF7FEFF bl UART_CheckIdleState 266 .LVL15: 267 .L12: 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 268 .loc 1 243 1 view .LVU74 269 006a F8BD pop {r3, r4, r5, r6, r7, pc} 270 .LVL16: 271 .L20: 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 272 .loc 1 191 5 is_stmt 1 view .LVU75 191:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 273 .loc 1 191 17 is_stmt 0 view .LVU76 274 006c 80F88430 strb r3, [r0, #132] 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ 275 .loc 1 205 5 is_stmt 1 view .LVU77 276 0070 FFF7FEFF bl HAL_UART_MspInit 277 .LVL17: 205:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ 278 .loc 1 205 5 is_stmt 0 view .LVU78 279 0074 CEE7 b .L13 280 .L21: 218:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 281 .loc 1 218 5 is_stmt 1 view .LVU79 282 0076 2046 mov r0, r4 283 0078 FFF7FEFF bl UART_AdvFeatureConfig 284 .LVL18: 285 007c D4E7 b .L14 286 .LVL19: 287 .L15: 288 .LCFI5: 289 .cfi_def_cfa_offset 0 290 .cfi_restore 3 291 .cfi_restore 4 292 .cfi_restore 5 293 .cfi_restore 6 294 .cfi_restore 7 295 .cfi_restore 14 174:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 296 .loc 1 174 12 is_stmt 0 view .LVU80 297 007e 0120 movs r0, #1 298 .LVL20: 243:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 299 .loc 1 243 1 view .LVU81 300 0080 7047 bx lr ARM GAS /tmp/ccnQFf6s.s page 25 301 .cfi_endproc 302 .LFE329: 304 .section .text.HAL_UARTEx_WakeupCallback,"ax",%progbits 305 .align 1 306 .weak HAL_UARTEx_WakeupCallback 307 .syntax unified 308 .thumb 309 .thumb_func 311 HAL_UARTEx_WakeupCallback: 312 .LVL21: 313 .LFB330: 275:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ 314 .loc 1 275 1 is_stmt 1 view -0 315 .cfi_startproc 316 @ args = 0, pretend = 0, frame = 0 317 @ frame_needed = 0, uses_anonymous_args = 0 318 @ link register save eliminated. 277:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 319 .loc 1 277 3 view .LVU83 282:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 320 .loc 1 282 1 is_stmt 0 view .LVU84 321 0000 7047 bx lr 322 .cfi_endproc 323 .LFE330: 325 .section .text.HAL_UARTEx_RxFifoFullCallback,"ax",%progbits 326 .align 1 327 .weak HAL_UARTEx_RxFifoFullCallback 328 .syntax unified 329 .thumb 330 .thumb_func 332 HAL_UARTEx_RxFifoFullCallback: 333 .LVL22: 334 .LFB331: 290:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ 335 .loc 1 290 1 is_stmt 1 view -0 336 .cfi_startproc 337 @ args = 0, pretend = 0, frame = 0 338 @ frame_needed = 0, uses_anonymous_args = 0 339 @ link register save eliminated. 292:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 340 .loc 1 292 3 view .LVU86 297:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 341 .loc 1 297 1 is_stmt 0 view .LVU87 342 0000 7047 bx lr 343 .cfi_endproc 344 .LFE331: 346 .section .text.HAL_UARTEx_TxFifoEmptyCallback,"ax",%progbits 347 .align 1 348 .weak HAL_UARTEx_TxFifoEmptyCallback 349 .syntax unified 350 .thumb 351 .thumb_func 353 HAL_UARTEx_TxFifoEmptyCallback: 354 .LVL23: 355 .LFB332: 305:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ 356 .loc 1 305 1 is_stmt 1 view -0 ARM GAS /tmp/ccnQFf6s.s page 26 357 .cfi_startproc 358 @ args = 0, pretend = 0, frame = 0 359 @ frame_needed = 0, uses_anonymous_args = 0 360 @ link register save eliminated. 307:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 361 .loc 1 307 3 view .LVU89 312:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 362 .loc 1 312 1 is_stmt 0 view .LVU90 363 0000 7047 bx lr 364 .cfi_endproc 365 .LFE332: 367 .section .text.HAL_MultiProcessorEx_AddressLength_Set,"ax",%progbits 368 .align 1 369 .global HAL_MultiProcessorEx_AddressLength_Set 370 .syntax unified 371 .thumb 372 .thumb_func 374 HAL_MultiProcessorEx_AddressLength_Set: 375 .LVL24: 376 .LFB333: 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */ 377 .loc 1 390 1 is_stmt 1 view -0 378 .cfi_startproc 379 @ args = 0, pretend = 0, frame = 0 380 @ frame_needed = 0, uses_anonymous_args = 0 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 381 .loc 1 392 3 view .LVU92 392:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 382 .loc 1 392 6 is_stmt 0 view .LVU93 383 0000 C0B1 cbz r0, .L27 390:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Check the UART handle allocation */ 384 .loc 1 390 1 view .LVU94 385 0002 08B5 push {r3, lr} 386 .LCFI6: 387 .cfi_def_cfa_offset 8 388 .cfi_offset 3, -8 389 .cfi_offset 14, -4 390 0004 0346 mov r3, r0 398:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 391 .loc 1 398 3 is_stmt 1 view .LVU95 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 392 .loc 1 400 3 view .LVU96 400:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 393 .loc 1 400 17 is_stmt 0 view .LVU97 394 0006 2422 movs r2, #36 395 0008 C0F88820 str r2, [r0, #136] 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 396 .loc 1 403 3 is_stmt 1 view .LVU98 397 000c 0068 ldr r0, [r0] 398 .LVL25: 403:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 399 .loc 1 403 3 is_stmt 0 view .LVU99 400 000e 0268 ldr r2, [r0] 401 0010 22F00102 bic r2, r2, #1 402 0014 0260 str r2, [r0] 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 403 .loc 1 406 3 is_stmt 1 view .LVU100 ARM GAS /tmp/ccnQFf6s.s page 27 404 0016 1868 ldr r0, [r3] 405 0018 4268 ldr r2, [r0, #4] 406 001a 22F01002 bic r2, r2, #16 407 001e 1143 orrs r1, r1, r2 408 .LVL26: 406:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 409 .loc 1 406 3 is_stmt 0 view .LVU101 410 0020 4160 str r1, [r0, #4] 409:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 411 .loc 1 409 3 is_stmt 1 view .LVU102 412 0022 1968 ldr r1, [r3] 413 0024 0A68 ldr r2, [r1] 414 0026 42F00102 orr r2, r2, #1 415 002a 0A60 str r2, [r1] 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 416 .loc 1 412 3 view .LVU103 412:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 417 .loc 1 412 11 is_stmt 0 view .LVU104 418 002c 1846 mov r0, r3 419 002e FFF7FEFF bl UART_CheckIdleState 420 .LVL27: 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 421 .loc 1 413 1 view .LVU105 422 0032 08BD pop {r3, pc} 423 .LVL28: 424 .L27: 425 .LCFI7: 426 .cfi_def_cfa_offset 0 427 .cfi_restore 3 428 .cfi_restore 14 394:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 429 .loc 1 394 12 view .LVU106 430 0034 0120 movs r0, #1 431 .LVL29: 413:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 432 .loc 1 413 1 view .LVU107 433 0036 7047 bx lr 434 .cfi_endproc 435 .LFE333: 437 .section .text.HAL_UARTEx_StopModeWakeUpSourceConfig,"ax",%progbits 438 .align 1 439 .global HAL_UARTEx_StopModeWakeUpSourceConfig 440 .syntax unified 441 .thumb 442 .thumb_func 444 HAL_UARTEx_StopModeWakeUpSourceConfig: 445 .LVL30: 446 .LFB334: 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; 447 .loc 1 428 1 is_stmt 1 view -0 448 .cfi_startproc 449 @ args = 0, pretend = 0, frame = 8 450 @ frame_needed = 0, uses_anonymous_args = 0 428:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; 451 .loc 1 428 1 is_stmt 0 view .LVU109 452 0000 10B5 push {r4, lr} 453 .LCFI8: ARM GAS /tmp/ccnQFf6s.s page 28 454 .cfi_def_cfa_offset 8 455 .cfi_offset 4, -8 456 .cfi_offset 14, -4 457 0002 84B0 sub sp, sp, #16 458 .LCFI9: 459 .cfi_def_cfa_offset 24 460 0004 04AB add r3, sp, #16 461 0006 03E90600 stmdb r3, {r1, r2} 429:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart; 462 .loc 1 429 3 is_stmt 1 view .LVU110 463 .LVL31: 430:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 464 .loc 1 430 3 view .LVU111 433:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* check the wake-up selection parameter */ 465 .loc 1 433 3 view .LVU112 435:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 466 .loc 1 435 3 view .LVU113 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 467 .loc 1 438 3 view .LVU114 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 468 .loc 1 438 3 view .LVU115 469 000a 90F88430 ldrb r3, [r0, #132] @ zero_extendqisi2 470 000e 012B cmp r3, #1 471 0010 35D0 beq .L36 472 0012 0446 mov r4, r0 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 473 .loc 1 438 3 discriminator 2 view .LVU116 474 0014 0123 movs r3, #1 475 0016 80F88430 strb r3, [r0, #132] 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 476 .loc 1 438 3 discriminator 2 view .LVU117 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 477 .loc 1 440 3 view .LVU118 440:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 478 .loc 1 440 17 is_stmt 0 view .LVU119 479 001a 2423 movs r3, #36 480 001c C0F88830 str r3, [r0, #136] 443:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 481 .loc 1 443 3 is_stmt 1 view .LVU120 482 0020 0268 ldr r2, [r0] 483 0022 1368 ldr r3, [r2] 484 0024 23F00103 bic r3, r3, #1 485 0028 1360 str r3, [r2] 446:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 486 .loc 1 446 3 view .LVU121 487 002a 0168 ldr r1, [r0] 488 002c 8B68 ldr r3, [r1, #8] 489 002e 23F44013 bic r3, r3, #3145728 490 0032 029A ldr r2, [sp, #8] 491 0034 1343 orrs r3, r3, r2 492 0036 8B60 str r3, [r1, #8] 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 493 .loc 1 448 3 view .LVU122 448:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 494 .loc 1 448 6 is_stmt 0 view .LVU123 495 0038 AAB1 cbz r2, .L39 496 .LVL32: ARM GAS /tmp/ccnQFf6s.s page 29 497 .L34: 454:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 498 .loc 1 454 3 is_stmt 1 view .LVU124 499 003a 2268 ldr r2, [r4] 500 003c 1368 ldr r3, [r2] 501 003e 43F00103 orr r3, r3, #1 502 0042 1360 str r3, [r2] 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 503 .loc 1 457 3 view .LVU125 457:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 504 .loc 1 457 15 is_stmt 0 view .LVU126 505 0044 FFF7FEFF bl HAL_GetTick 506 .LVL33: 507 0048 0346 mov r3, r0 508 .LVL34: 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 509 .loc 1 460 3 is_stmt 1 view .LVU127 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 510 .loc 1 460 7 is_stmt 0 view .LVU128 511 004a 6FF07E42 mvn r2, #-33554432 512 004e 0092 str r2, [sp] 513 0050 0022 movs r2, #0 514 0052 4FF48001 mov r1, #4194304 515 0056 2046 mov r0, r4 516 .LVL35: 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 517 .loc 1 460 7 view .LVU129 518 0058 FFF7FEFF bl UART_WaitOnFlagUntilTimeout 519 .LVL36: 460:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 520 .loc 1 460 6 discriminator 1 view .LVU130 521 005c 48B9 cbnz r0, .L37 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 522 .loc 1 467 5 is_stmt 1 view .LVU131 467:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 523 .loc 1 467 19 is_stmt 0 view .LVU132 524 005e 2023 movs r3, #32 525 0060 C4F88830 str r3, [r4, #136] 526 0064 06E0 b .L35 527 .LVL37: 528 .L39: 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 529 .loc 1 450 5 is_stmt 1 view .LVU133 530 0066 04AB add r3, sp, #16 531 0068 13E90600 ldmdb r3, {r1, r2} 532 006c FFF7FEFF bl UARTEx_Wakeup_AddressConfig 533 .LVL38: 450:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 534 .loc 1 450 5 is_stmt 0 view .LVU134 535 0070 E3E7 b .L34 536 .LVL39: 537 .L37: 462:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 538 .loc 1 462 12 view .LVU135 539 0072 0320 movs r0, #3 540 .L35: 541 .LVL40: ARM GAS /tmp/ccnQFf6s.s page 30 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 542 .loc 1 471 3 is_stmt 1 view .LVU136 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 543 .loc 1 471 3 view .LVU137 544 0074 0023 movs r3, #0 545 0076 84F88430 strb r3, [r4, #132] 471:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 546 .loc 1 471 3 view .LVU138 473:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 547 .loc 1 473 3 view .LVU139 548 .LVL41: 549 .L33: 474:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 550 .loc 1 474 1 is_stmt 0 view .LVU140 551 007a 04B0 add sp, sp, #16 552 .LCFI10: 553 .cfi_remember_state 554 .cfi_def_cfa_offset 8 555 @ sp needed 556 007c 10BD pop {r4, pc} 557 .LVL42: 558 .L36: 559 .LCFI11: 560 .cfi_restore_state 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 561 .loc 1 438 3 discriminator 1 view .LVU141 562 007e 0220 movs r0, #2 563 .LVL43: 438:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 564 .loc 1 438 3 discriminator 1 view .LVU142 565 0080 FBE7 b .L33 566 .cfi_endproc 567 .LFE334: 569 .section .text.HAL_UARTEx_EnableStopMode,"ax",%progbits 570 .align 1 571 .global HAL_UARTEx_EnableStopMode 572 .syntax unified 573 .thumb 574 .thumb_func 576 HAL_UARTEx_EnableStopMode: 577 .LVL44: 578 .LFB335: 483:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 579 .loc 1 483 1 is_stmt 1 view -0 580 .cfi_startproc 581 @ args = 0, pretend = 0, frame = 0 582 @ frame_needed = 0, uses_anonymous_args = 0 583 @ link register save eliminated. 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 584 .loc 1 485 3 view .LVU144 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 585 .loc 1 485 3 view .LVU145 586 0000 90F88430 ldrb r3, [r0, #132] @ zero_extendqisi2 587 0004 012B cmp r3, #1 588 0006 10D0 beq .L43 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 589 .loc 1 485 3 discriminator 2 view .LVU146 ARM GAS /tmp/ccnQFf6s.s page 31 590 0008 0123 movs r3, #1 591 000a 80F88430 strb r3, [r0, #132] 592 .L42: 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 593 .loc 1 485 3 discriminator 3 view .LVU147 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 594 .loc 1 488 3 discriminator 1 view .LVU148 595 .LBB22: 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 596 .loc 1 488 3 discriminator 1 view .LVU149 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 597 .loc 1 488 3 discriminator 1 view .LVU150 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 598 .loc 1 488 3 discriminator 1 view .LVU151 599 000e 0268 ldr r2, [r0] 600 .LVL45: 601 .LBB23: 602 .LBI23: 603 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccnQFf6s.s page 32 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push ARM GAS /tmp/ccnQFf6s.s page 33 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { ARM GAS /tmp/ccnQFf6s.s page 34 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 189:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 195:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 197:Drivers/CMSIS/Include/cmsis_gcc.h **** { 198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 199:Drivers/CMSIS/Include/cmsis_gcc.h **** } 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 206:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 208:Drivers/CMSIS/Include/cmsis_gcc.h **** { 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); ARM GAS /tmp/ccnQFf6s.s page 35 210:Drivers/CMSIS/Include/cmsis_gcc.h **** } 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 217:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 219:Drivers/CMSIS/Include/cmsis_gcc.h **** { 220:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 222:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 223:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** } 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { 250:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 251:Drivers/CMSIS/Include/cmsis_gcc.h **** } 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 259:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 261:Drivers/CMSIS/Include/cmsis_gcc.h **** { 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 263:Drivers/CMSIS/Include/cmsis_gcc.h **** } 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccnQFf6s.s page 36 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 268:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 271:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 273:Drivers/CMSIS/Include/cmsis_gcc.h **** { 274:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 277:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 278:Drivers/CMSIS/Include/cmsis_gcc.h **** } 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 284:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 285:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 287:Drivers/CMSIS/Include/cmsis_gcc.h **** { 288:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 290:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 291:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 299:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 301:Drivers/CMSIS/Include/cmsis_gcc.h **** { 302:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 304:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 305:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** } 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { 316:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 318:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 319:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 320:Drivers/CMSIS/Include/cmsis_gcc.h **** } 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) ARM GAS /tmp/ccnQFf6s.s page 37 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 326:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 328:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 330:Drivers/CMSIS/Include/cmsis_gcc.h **** { 331:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 335:Drivers/CMSIS/Include/cmsis_gcc.h **** } 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 343:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 345:Drivers/CMSIS/Include/cmsis_gcc.h **** { 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 347:Drivers/CMSIS/Include/cmsis_gcc.h **** } 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 359:Drivers/CMSIS/Include/cmsis_gcc.h **** } 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 365:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 367:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 369:Drivers/CMSIS/Include/cmsis_gcc.h **** { 370:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 374:Drivers/CMSIS/Include/cmsis_gcc.h **** } 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat ARM GAS /tmp/ccnQFf6s.s page 38 381:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 382:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 384:Drivers/CMSIS/Include/cmsis_gcc.h **** { 385:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 387:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 389:Drivers/CMSIS/Include/cmsis_gcc.h **** } 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 396:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 397:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 399:Drivers/CMSIS/Include/cmsis_gcc.h **** { 400:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 401:Drivers/CMSIS/Include/cmsis_gcc.h **** } 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 407:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 409:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 411:Drivers/CMSIS/Include/cmsis_gcc.h **** { 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 413:Drivers/CMSIS/Include/cmsis_gcc.h **** } 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 419:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 422:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 424:Drivers/CMSIS/Include/cmsis_gcc.h **** { 425:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 427:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 428:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 429:Drivers/CMSIS/Include/cmsis_gcc.h **** } 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 433:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 434:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 436:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) ARM GAS /tmp/ccnQFf6s.s page 39 438:Drivers/CMSIS/Include/cmsis_gcc.h **** { 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 440:Drivers/CMSIS/Include/cmsis_gcc.h **** } 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 448:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 450:Drivers/CMSIS/Include/cmsis_gcc.h **** { 451:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 453:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 454:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 455:Drivers/CMSIS/Include/cmsis_gcc.h **** } 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 460:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 461:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 462:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 465:Drivers/CMSIS/Include/cmsis_gcc.h **** { 466:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 468:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 469:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 470:Drivers/CMSIS/Include/cmsis_gcc.h **** } 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 475:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 476:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 477:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 478:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 480:Drivers/CMSIS/Include/cmsis_gcc.h **** { 481:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccnQFf6s.s page 40 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 499:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 500:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 502:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 504:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 505:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 507:Drivers/CMSIS/Include/cmsis_gcc.h **** { 508:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 509:Drivers/CMSIS/Include/cmsis_gcc.h **** } 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 513:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 515:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 516:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 518:Drivers/CMSIS/Include/cmsis_gcc.h **** { 519:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 520:Drivers/CMSIS/Include/cmsis_gcc.h **** } 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 526:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 527:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 529:Drivers/CMSIS/Include/cmsis_gcc.h **** { 530:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 532:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 534:Drivers/CMSIS/Include/cmsis_gcc.h **** } 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 541:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 542:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 544:Drivers/CMSIS/Include/cmsis_gcc.h **** { 545:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 547:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 548:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 549:Drivers/CMSIS/Include/cmsis_gcc.h **** } 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 551:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccnQFf6s.s page 41 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 557:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 559:Drivers/CMSIS/Include/cmsis_gcc.h **** { 560:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 561:Drivers/CMSIS/Include/cmsis_gcc.h **** } 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 568:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 569:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 571:Drivers/CMSIS/Include/cmsis_gcc.h **** { 572:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 573:Drivers/CMSIS/Include/cmsis_gcc.h **** } 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 578:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 579:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 580:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 581:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 582:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 584:Drivers/CMSIS/Include/cmsis_gcc.h **** { 585:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 586:Drivers/CMSIS/Include/cmsis_gcc.h **** } 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 592:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 593:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 595:Drivers/CMSIS/Include/cmsis_gcc.h **** { 596:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 598:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 599:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 600:Drivers/CMSIS/Include/cmsis_gcc.h **** } 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 608:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccnQFf6s.s page 42 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 610:Drivers/CMSIS/Include/cmsis_gcc.h **** { 611:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 614:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 615:Drivers/CMSIS/Include/cmsis_gcc.h **** } 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 620:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 621:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 622:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 623:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 625:Drivers/CMSIS/Include/cmsis_gcc.h **** { 626:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 627:Drivers/CMSIS/Include/cmsis_gcc.h **** } 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 632:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 633:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 635:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 637:Drivers/CMSIS/Include/cmsis_gcc.h **** { 638:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 639:Drivers/CMSIS/Include/cmsis_gcc.h **** } 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 644:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 648:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 654:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 657:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 658:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 660:Drivers/CMSIS/Include/cmsis_gcc.h **** { 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 663:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 664:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else ARM GAS /tmp/ccnQFf6s.s page 43 666:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 668:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 675:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 676:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 678:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 679:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 680:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 682:Drivers/CMSIS/Include/cmsis_gcc.h **** { 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 684:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 685:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 687:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 688:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 689:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 691:Drivers/CMSIS/Include/cmsis_gcc.h **** } 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 696:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 698:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 699:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 700:Drivers/CMSIS/Include/cmsis_gcc.h **** 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 703:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** { 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 708:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 709:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 711:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 713:Drivers/CMSIS/Include/cmsis_gcc.h **** } 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 718:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s ARM GAS /tmp/ccnQFf6s.s page 44 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 728:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 729:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 731:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 733:Drivers/CMSIS/Include/cmsis_gcc.h **** } 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 738:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 739:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 749:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 750:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 751:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 753:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 754:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 755:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 757:Drivers/CMSIS/Include/cmsis_gcc.h **** } 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 763:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 764:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 766:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 767:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 768:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** { 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 773:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 775:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 776:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 777:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 779:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccnQFf6s.s page 45 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 784:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 785:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 786:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 787:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 797:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 799:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 801:Drivers/CMSIS/Include/cmsis_gcc.h **** } 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 806:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 807:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 808:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 811:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 812:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 814:Drivers/CMSIS/Include/cmsis_gcc.h **** { 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 816:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 817:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 821:Drivers/CMSIS/Include/cmsis_gcc.h **** } 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 825:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 830:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 831:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 832:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 834:Drivers/CMSIS/Include/cmsis_gcc.h **** { 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) ARM GAS /tmp/ccnQFf6s.s page 46 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 840:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 841:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 843:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 846:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 849:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 851:Drivers/CMSIS/Include/cmsis_gcc.h **** } 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 857:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 858:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 860:Drivers/CMSIS/Include/cmsis_gcc.h **** { 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 862:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 866:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 867:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 869:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 872:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 874:Drivers/CMSIS/Include/cmsis_gcc.h **** } 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 882:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 883:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 887:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 888:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else ARM GAS /tmp/ccnQFf6s.s page 47 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 902:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 906:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 907:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 908:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 913:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 915:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 916:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 930:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 931:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 932:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 934:Drivers/CMSIS/Include/cmsis_gcc.h **** { 935:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 936:Drivers/CMSIS/Include/cmsis_gcc.h **** } 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 941:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 942:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 943:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 945:Drivers/CMSIS/Include/cmsis_gcc.h **** { 946:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 947:Drivers/CMSIS/Include/cmsis_gcc.h **** } 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccnQFf6s.s page 48 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 953:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 954:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 956:Drivers/CMSIS/Include/cmsis_gcc.h **** { 957:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 958:Drivers/CMSIS/Include/cmsis_gcc.h **** } 959:Drivers/CMSIS/Include/cmsis_gcc.h **** 960:Drivers/CMSIS/Include/cmsis_gcc.h **** 961:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 962:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 963:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 964:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 965:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 966:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 968:Drivers/CMSIS/Include/cmsis_gcc.h **** { 969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 970:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 972:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 974:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 975:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 977:Drivers/CMSIS/Include/cmsis_gcc.h **** } 978:Drivers/CMSIS/Include/cmsis_gcc.h **** 979:Drivers/CMSIS/Include/cmsis_gcc.h **** 980:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 981:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 982:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 983:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 984:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 985:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 987:Drivers/CMSIS/Include/cmsis_gcc.h **** { 988:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 989:Drivers/CMSIS/Include/cmsis_gcc.h **** 990:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 991:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 992:Drivers/CMSIS/Include/cmsis_gcc.h **** } 993:Drivers/CMSIS/Include/cmsis_gcc.h **** 994:Drivers/CMSIS/Include/cmsis_gcc.h **** 995:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 996:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 997:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 998:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 999:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 1002:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1004:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1006:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 1007:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccnQFf6s.s page 49 1008:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 1009:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1011:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1015:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 1016:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 1017:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 1018:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 1020:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 1022:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1023:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 1024:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1026:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 1027:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1028:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 1029:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1030:Drivers/CMSIS/Include/cmsis_gcc.h **** 1031:Drivers/CMSIS/Include/cmsis_gcc.h **** 1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1033:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 1034:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 1035:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 1036:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 1037:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 1038:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 1040:Drivers/CMSIS/Include/cmsis_gcc.h **** 1041:Drivers/CMSIS/Include/cmsis_gcc.h **** 1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 1045:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 1046:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 1047:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 1049:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1050:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1051:Drivers/CMSIS/Include/cmsis_gcc.h **** 1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1053:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1054:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 1055:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1057:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 1058:Drivers/CMSIS/Include/cmsis_gcc.h **** 1059:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 1060:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 1061:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1062:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 1063:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 1064:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; ARM GAS /tmp/ccnQFf6s.s page 50 1065:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1066:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1068:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 1069:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1073:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 1074:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 1075:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 1076:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 1077:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 1079:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1080:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Even though __builtin_clz produces a CLZ instruction on ARM, formally 1081:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_clz(0) is undefined behaviour, so handle this case specially. 1082:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM 1083:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any 1084:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it 1085:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero". 1086:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a 1087:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction. 1088:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1089:Drivers/CMSIS/Include/cmsis_gcc.h **** if (value == 0U) 1090:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1091:Drivers/CMSIS/Include/cmsis_gcc.h **** return 32U; 1092:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1093:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_clz(value); 1094:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1095:Drivers/CMSIS/Include/cmsis_gcc.h **** 1096:Drivers/CMSIS/Include/cmsis_gcc.h **** 1097:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1098:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1099:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1100:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1101:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1102:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 1103:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 1104:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1105:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 1106:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1107:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 1108:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1109:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1110:Drivers/CMSIS/Include/cmsis_gcc.h **** 1111:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1112:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 1113:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1114:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1115:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1116:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1117:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1119:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 1120:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1121:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccnQFf6s.s page 51 1122:Drivers/CMSIS/Include/cmsis_gcc.h **** 1123:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1124:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 1125:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 1126:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1127:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 1128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 1130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1131:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1132:Drivers/CMSIS/Include/cmsis_gcc.h **** 1133:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 1134:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 1135:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 1136:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 1137:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 1138:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1139:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 1140:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 1141:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 1142:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1143:Drivers/CMSIS/Include/cmsis_gcc.h **** 1144:Drivers/CMSIS/Include/cmsis_gcc.h **** 1145:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1146:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 1147:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 1148:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 1149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 1150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 604 .loc 2 1151 31 view .LVU152 605 .LBB24: 1152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 606 .loc 2 1153 5 view .LVU153 1154:Drivers/CMSIS/Include/cmsis_gcc.h **** 1155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 607 .loc 2 1155 4 view .LVU154 608 .syntax unified 609 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 610 0010 52E8003F ldrex r3, [r2] 611 @ 0 "" 2 612 .LVL46: 1156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 613 .loc 2 1156 4 view .LVU155 614 .loc 2 1156 4 is_stmt 0 view .LVU156 615 .thumb 616 .syntax unified 617 .LBE24: 618 .LBE23: 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 619 .loc 1 488 3 discriminator 1 view .LVU157 620 0014 43F00203 orr r3, r3, #2 621 .LVL47: 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 622 .loc 1 488 3 is_stmt 1 discriminator 1 view .LVU158 623 .LBB25: ARM GAS /tmp/ccnQFf6s.s page 52 624 .LBI25: 1157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1158:Drivers/CMSIS/Include/cmsis_gcc.h **** 1159:Drivers/CMSIS/Include/cmsis_gcc.h **** 1160:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1161:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 1162:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 1163:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1164:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1165:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1166:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1167:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1168:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 1169:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1170:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1171:Drivers/CMSIS/Include/cmsis_gcc.h **** 1172:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1173:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1174:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1175:Drivers/CMSIS/Include/cmsis_gcc.h **** 1176:Drivers/CMSIS/Include/cmsis_gcc.h **** 1177:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1178:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 1179:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 1180:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1181:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1182:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1183:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1184:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1185:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 1186:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1187:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 1188:Drivers/CMSIS/Include/cmsis_gcc.h **** 1189:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 1190:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1191:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1192:Drivers/CMSIS/Include/cmsis_gcc.h **** 1193:Drivers/CMSIS/Include/cmsis_gcc.h **** 1194:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 1195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 1196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 1197:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 1198:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 1199:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 1200:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 1201:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 1202:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 625 .loc 2 1202 31 view .LVU159 626 .LBB26: 1203:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1204:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 627 .loc 2 1204 4 view .LVU160 1205:Drivers/CMSIS/Include/cmsis_gcc.h **** 1206:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 628 .loc 2 1206 4 view .LVU161 629 .syntax unified 630 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 ARM GAS /tmp/ccnQFf6s.s page 53 631 0018 42E80031 strex r1, r3, [r2] 632 @ 0 "" 2 633 .LVL48: 1207:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 634 .loc 2 1207 4 view .LVU162 635 .loc 2 1207 4 is_stmt 0 view .LVU163 636 .thumb 637 .syntax unified 638 .LBE26: 639 .LBE25: 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 640 .loc 1 488 3 discriminator 1 view .LVU164 641 001c 0029 cmp r1, #0 642 001e F6D1 bne .L42 643 .LBE22: 488:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 644 .loc 1 488 3 is_stmt 1 discriminator 2 view .LVU165 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 645 .loc 1 491 3 view .LVU166 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 646 .loc 1 491 3 view .LVU167 647 0020 0023 movs r3, #0 648 .LVL49: 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 649 .loc 1 491 3 is_stmt 0 view .LVU168 650 0022 80F88430 strb r3, [r0, #132] 491:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 651 .loc 1 491 3 is_stmt 1 view .LVU169 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 652 .loc 1 493 3 view .LVU170 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 653 .loc 1 493 10 is_stmt 0 view .LVU171 654 0026 1846 mov r0, r3 655 .LVL50: 493:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 656 .loc 1 493 10 view .LVU172 657 0028 7047 bx lr 658 .LVL51: 659 .L43: 485:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 660 .loc 1 485 3 discriminator 1 view .LVU173 661 002a 0220 movs r0, #2 662 .LVL52: 494:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 663 .loc 1 494 1 view .LVU174 664 002c 7047 bx lr 665 .cfi_endproc 666 .LFE335: 668 .section .text.HAL_UARTEx_DisableStopMode,"ax",%progbits 669 .align 1 670 .global HAL_UARTEx_DisableStopMode 671 .syntax unified 672 .thumb 673 .thumb_func 675 HAL_UARTEx_DisableStopMode: 676 .LVL53: 677 .LFB336: ARM GAS /tmp/ccnQFf6s.s page 54 502:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Process Locked */ 678 .loc 1 502 1 is_stmt 1 view -0 679 .cfi_startproc 680 @ args = 0, pretend = 0, frame = 0 681 @ frame_needed = 0, uses_anonymous_args = 0 682 @ link register save eliminated. 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 683 .loc 1 504 3 view .LVU176 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 684 .loc 1 504 3 view .LVU177 685 0000 90F88430 ldrb r3, [r0, #132] @ zero_extendqisi2 686 0004 012B cmp r3, #1 687 0006 10D0 beq .L47 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 688 .loc 1 504 3 discriminator 2 view .LVU178 689 0008 0123 movs r3, #1 690 000a 80F88430 strb r3, [r0, #132] 691 .L46: 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 692 .loc 1 504 3 discriminator 3 view .LVU179 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 693 .loc 1 507 3 discriminator 1 view .LVU180 694 .LBB27: 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 695 .loc 1 507 3 discriminator 1 view .LVU181 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 696 .loc 1 507 3 discriminator 1 view .LVU182 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 697 .loc 1 507 3 discriminator 1 view .LVU183 698 000e 0268 ldr r2, [r0] 699 .LVL54: 700 .LBB28: 701 .LBI28: 1151:Drivers/CMSIS/Include/cmsis_gcc.h **** { 702 .loc 2 1151 31 view .LVU184 703 .LBB29: 1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 704 .loc 2 1153 5 view .LVU185 1155:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 705 .loc 2 1155 4 view .LVU186 706 .syntax unified 707 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 708 0010 52E8003F ldrex r3, [r2] 709 @ 0 "" 2 710 .LVL55: 1156:Drivers/CMSIS/Include/cmsis_gcc.h **** } 711 .loc 2 1156 4 view .LVU187 1156:Drivers/CMSIS/Include/cmsis_gcc.h **** } 712 .loc 2 1156 4 is_stmt 0 view .LVU188 713 .thumb 714 .syntax unified 715 .LBE29: 716 .LBE28: 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 717 .loc 1 507 3 discriminator 1 view .LVU189 718 0014 23F00203 bic r3, r3, #2 719 .LVL56: ARM GAS /tmp/ccnQFf6s.s page 55 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 720 .loc 1 507 3 is_stmt 1 discriminator 1 view .LVU190 721 .LBB30: 722 .LBI30: 1202:Drivers/CMSIS/Include/cmsis_gcc.h **** { 723 .loc 2 1202 31 view .LVU191 724 .LBB31: 1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 725 .loc 2 1204 4 view .LVU192 1206:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 726 .loc 2 1206 4 view .LVU193 727 .syntax unified 728 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 729 0018 42E80031 strex r1, r3, [r2] 730 @ 0 "" 2 731 .LVL57: 732 .loc 2 1207 4 view .LVU194 733 .loc 2 1207 4 is_stmt 0 view .LVU195 734 .thumb 735 .syntax unified 736 .LBE31: 737 .LBE30: 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 738 .loc 1 507 3 discriminator 1 view .LVU196 739 001c 0029 cmp r1, #0 740 001e F6D1 bne .L46 741 .LBE27: 507:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 742 .loc 1 507 3 is_stmt 1 discriminator 2 view .LVU197 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 743 .loc 1 510 3 view .LVU198 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 744 .loc 1 510 3 view .LVU199 745 0020 0023 movs r3, #0 746 .LVL58: 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 747 .loc 1 510 3 is_stmt 0 view .LVU200 748 0022 80F88430 strb r3, [r0, #132] 510:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 749 .loc 1 510 3 is_stmt 1 view .LVU201 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 750 .loc 1 512 3 view .LVU202 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 751 .loc 1 512 10 is_stmt 0 view .LVU203 752 0026 1846 mov r0, r3 753 .LVL59: 512:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 754 .loc 1 512 10 view .LVU204 755 0028 7047 bx lr 756 .LVL60: 757 .L47: 504:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 758 .loc 1 504 3 discriminator 1 view .LVU205 759 002a 0220 movs r0, #2 760 .LVL61: 513:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 761 .loc 1 513 1 view .LVU206 ARM GAS /tmp/ccnQFf6s.s page 56 762 002c 7047 bx lr 763 .cfi_endproc 764 .LFE336: 766 .section .text.HAL_UARTEx_EnableFifoMode,"ax",%progbits 767 .align 1 768 .global HAL_UARTEx_EnableFifoMode 769 .syntax unified 770 .thumb 771 .thumb_func 773 HAL_UARTEx_EnableFifoMode: 774 .LVL62: 775 .LFB337: 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 776 .loc 1 521 1 is_stmt 1 view -0 777 .cfi_startproc 778 @ args = 0, pretend = 0, frame = 0 779 @ frame_needed = 0, uses_anonymous_args = 0 522:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 780 .loc 1 522 3 view .LVU208 525:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 781 .loc 1 525 3 view .LVU209 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 782 .loc 1 528 3 view .LVU210 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 783 .loc 1 528 3 view .LVU211 784 0000 90F88430 ldrb r3, [r0, #132] @ zero_extendqisi2 785 0004 012B cmp r3, #1 786 0006 1DD0 beq .L50 521:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 787 .loc 1 521 1 is_stmt 0 view .LVU212 788 0008 10B5 push {r4, lr} 789 .LCFI12: 790 .cfi_def_cfa_offset 8 791 .cfi_offset 4, -8 792 .cfi_offset 14, -4 793 000a 0446 mov r4, r0 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 794 .loc 1 528 3 is_stmt 1 discriminator 2 view .LVU213 795 000c 0123 movs r3, #1 796 000e 80F88430 strb r3, [r0, #132] 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 797 .loc 1 528 3 discriminator 2 view .LVU214 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 798 .loc 1 530 3 view .LVU215 530:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 799 .loc 1 530 17 is_stmt 0 view .LVU216 800 0012 2423 movs r3, #36 801 0014 C0F88830 str r3, [r0, #136] 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 802 .loc 1 533 3 is_stmt 1 view .LVU217 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 803 .loc 1 533 12 is_stmt 0 view .LVU218 804 0018 0268 ldr r2, [r0] 533:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 805 .loc 1 533 10 view .LVU219 806 001a 1368 ldr r3, [r2] 807 .LVL63: ARM GAS /tmp/ccnQFf6s.s page 57 536:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 808 .loc 1 536 3 is_stmt 1 view .LVU220 809 001c 1168 ldr r1, [r2] 810 001e 21F00101 bic r1, r1, #1 811 0022 1160 str r1, [r2] 539:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_ENABLE; 812 .loc 1 539 3 view .LVU221 813 0024 43F00053 orr r3, r3, #536870912 814 .LVL64: 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 815 .loc 1 540 3 view .LVU222 540:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 816 .loc 1 540 19 is_stmt 0 view .LVU223 817 0028 4FF00052 mov r2, #536870912 818 002c 4266 str r2, [r0, #100] 543:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 819 .loc 1 543 3 is_stmt 1 view .LVU224 820 002e 0268 ldr r2, [r0] 821 0030 1360 str r3, [r2] 546:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 822 .loc 1 546 3 view .LVU225 823 0032 FFF7FEFF bl UARTEx_SetNbDataToProcess 824 .LVL65: 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 825 .loc 1 548 3 view .LVU226 548:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 826 .loc 1 548 17 is_stmt 0 view .LVU227 827 0036 2023 movs r3, #32 828 0038 C4F88830 str r3, [r4, #136] 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 829 .loc 1 551 3 is_stmt 1 view .LVU228 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 830 .loc 1 551 3 view .LVU229 831 003c 0020 movs r0, #0 832 003e 84F88400 strb r0, [r4, #132] 551:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 833 .loc 1 551 3 view .LVU230 553:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 834 .loc 1 553 3 view .LVU231 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 835 .loc 1 554 1 is_stmt 0 view .LVU232 836 0042 10BD pop {r4, pc} 837 .LVL66: 838 .L50: 839 .LCFI13: 840 .cfi_def_cfa_offset 0 841 .cfi_restore 4 842 .cfi_restore 14 528:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 843 .loc 1 528 3 discriminator 1 view .LVU233 844 0044 0220 movs r0, #2 845 .LVL67: 554:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 846 .loc 1 554 1 view .LVU234 847 0046 7047 bx lr 848 .cfi_endproc 849 .LFE337: ARM GAS /tmp/ccnQFf6s.s page 58 851 .section .text.HAL_UARTEx_DisableFifoMode,"ax",%progbits 852 .align 1 853 .global HAL_UARTEx_DisableFifoMode 854 .syntax unified 855 .thumb 856 .thumb_func 858 HAL_UARTEx_DisableFifoMode: 859 .LVL68: 860 .LFB338: 562:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 861 .loc 1 562 1 is_stmt 1 view -0 862 .cfi_startproc 863 @ args = 0, pretend = 0, frame = 0 864 @ frame_needed = 0, uses_anonymous_args = 0 865 @ link register save eliminated. 563:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 866 .loc 1 563 3 view .LVU236 566:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 867 .loc 1 566 3 view .LVU237 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 868 .loc 1 569 3 view .LVU238 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 869 .loc 1 569 3 view .LVU239 870 0000 90F88430 ldrb r3, [r0, #132] @ zero_extendqisi2 871 0004 012B cmp r3, #1 872 0006 18D0 beq .L57 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 873 .loc 1 569 3 discriminator 2 view .LVU240 874 0008 0123 movs r3, #1 875 000a 80F88430 strb r3, [r0, #132] 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 876 .loc 1 569 3 discriminator 2 view .LVU241 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 877 .loc 1 571 3 view .LVU242 571:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 878 .loc 1 571 17 is_stmt 0 view .LVU243 879 000e 2423 movs r3, #36 880 0010 C0F88830 str r3, [r0, #136] 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 881 .loc 1 574 3 is_stmt 1 view .LVU244 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 882 .loc 1 574 12 is_stmt 0 view .LVU245 883 0014 0368 ldr r3, [r0] 574:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 884 .loc 1 574 10 view .LVU246 885 0016 1A68 ldr r2, [r3] 886 .LVL69: 577:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 887 .loc 1 577 3 is_stmt 1 view .LVU247 888 0018 1968 ldr r1, [r3] 889 001a 21F00101 bic r1, r1, #1 890 001e 1960 str r1, [r3] 580:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_DISABLE; 891 .loc 1 580 3 view .LVU248 892 0020 22F00052 bic r2, r2, #536870912 893 .LVL70: 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ARM GAS /tmp/ccnQFf6s.s page 59 894 .loc 1 581 3 view .LVU249 581:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 895 .loc 1 581 19 is_stmt 0 view .LVU250 896 0024 0023 movs r3, #0 897 0026 4366 str r3, [r0, #100] 584:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 898 .loc 1 584 3 is_stmt 1 view .LVU251 899 0028 0168 ldr r1, [r0] 900 002a 0A60 str r2, [r1] 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 901 .loc 1 586 3 view .LVU252 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 902 .loc 1 586 17 is_stmt 0 view .LVU253 903 002c 2022 movs r2, #32 904 .LVL71: 586:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 905 .loc 1 586 17 view .LVU254 906 002e C0F88820 str r2, [r0, #136] 907 .LVL72: 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 908 .loc 1 589 3 is_stmt 1 view .LVU255 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 909 .loc 1 589 3 view .LVU256 910 0032 80F88430 strb r3, [r0, #132] 589:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 911 .loc 1 589 3 view .LVU257 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 912 .loc 1 591 3 view .LVU258 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 913 .loc 1 591 10 is_stmt 0 view .LVU259 914 0036 1846 mov r0, r3 915 .LVL73: 591:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 916 .loc 1 591 10 view .LVU260 917 0038 7047 bx lr 918 .LVL74: 919 .L57: 569:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 920 .loc 1 569 3 discriminator 1 view .LVU261 921 003a 0220 movs r0, #2 922 .LVL75: 592:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 923 .loc 1 592 1 view .LVU262 924 003c 7047 bx lr 925 .cfi_endproc 926 .LFE338: 928 .section .text.HAL_UARTEx_SetTxFifoThreshold,"ax",%progbits 929 .align 1 930 .global HAL_UARTEx_SetTxFifoThreshold 931 .syntax unified 932 .thumb 933 .thumb_func 935 HAL_UARTEx_SetTxFifoThreshold: 936 .LVL76: 937 .LFB339: 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 938 .loc 1 608 1 is_stmt 1 view -0 ARM GAS /tmp/ccnQFf6s.s page 60 939 .cfi_startproc 940 @ args = 0, pretend = 0, frame = 0 941 @ frame_needed = 0, uses_anonymous_args = 0 608:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 942 .loc 1 608 1 is_stmt 0 view .LVU264 943 0000 38B5 push {r3, r4, r5, lr} 944 .LCFI14: 945 .cfi_def_cfa_offset 16 946 .cfi_offset 3, -16 947 .cfi_offset 4, -12 948 .cfi_offset 5, -8 949 .cfi_offset 14, -4 609:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 950 .loc 1 609 3 is_stmt 1 view .LVU265 612:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); 951 .loc 1 612 3 view .LVU266 613:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 952 .loc 1 613 3 view .LVU267 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 953 .loc 1 616 3 view .LVU268 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 954 .loc 1 616 3 view .LVU269 955 0002 90F88430 ldrb r3, [r0, #132] @ zero_extendqisi2 956 0006 012B cmp r3, #1 957 0008 1DD0 beq .L60 958 000a 0446 mov r4, r0 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 959 .loc 1 616 3 discriminator 2 view .LVU270 960 000c 0123 movs r3, #1 961 000e 80F88430 strb r3, [r0, #132] 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 962 .loc 1 616 3 discriminator 2 view .LVU271 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 963 .loc 1 618 3 view .LVU272 618:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 964 .loc 1 618 17 is_stmt 0 view .LVU273 965 0012 2423 movs r3, #36 966 0014 C0F88830 str r3, [r0, #136] 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 967 .loc 1 621 3 is_stmt 1 view .LVU274 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 968 .loc 1 621 12 is_stmt 0 view .LVU275 969 0018 0368 ldr r3, [r0] 621:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 970 .loc 1 621 10 view .LVU276 971 001a 1D68 ldr r5, [r3] 972 .LVL77: 624:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 973 .loc 1 624 3 is_stmt 1 view .LVU277 974 001c 1A68 ldr r2, [r3] 975 001e 22F00102 bic r2, r2, #1 976 0022 1A60 str r2, [r3] 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 977 .loc 1 627 3 view .LVU278 978 0024 0268 ldr r2, [r0] 979 0026 9368 ldr r3, [r2, #8] 980 0028 23F06043 bic r3, r3, #-536870912 ARM GAS /tmp/ccnQFf6s.s page 61 981 002c 1943 orrs r1, r1, r3 982 .LVL78: 627:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 983 .loc 1 627 3 is_stmt 0 view .LVU279 984 002e 9160 str r1, [r2, #8] 630:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 985 .loc 1 630 3 is_stmt 1 view .LVU280 986 0030 FFF7FEFF bl UARTEx_SetNbDataToProcess 987 .LVL79: 633:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 988 .loc 1 633 3 view .LVU281 989 0034 2368 ldr r3, [r4] 990 0036 1D60 str r5, [r3] 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 991 .loc 1 635 3 view .LVU282 635:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 992 .loc 1 635 17 is_stmt 0 view .LVU283 993 0038 2023 movs r3, #32 994 003a C4F88830 str r3, [r4, #136] 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 995 .loc 1 638 3 is_stmt 1 view .LVU284 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 996 .loc 1 638 3 view .LVU285 997 003e 0020 movs r0, #0 998 0040 84F88400 strb r0, [r4, #132] 638:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 999 .loc 1 638 3 view .LVU286 640:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1000 .loc 1 640 3 view .LVU287 1001 .LVL80: 1002 .L59: 641:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1003 .loc 1 641 1 is_stmt 0 view .LVU288 1004 0044 38BD pop {r3, r4, r5, pc} 1005 .LVL81: 1006 .L60: 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1007 .loc 1 616 3 discriminator 1 view .LVU289 1008 0046 0220 movs r0, #2 1009 .LVL82: 616:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1010 .loc 1 616 3 discriminator 1 view .LVU290 1011 0048 FCE7 b .L59 1012 .cfi_endproc 1013 .LFE339: 1015 .section .text.HAL_UARTEx_SetRxFifoThreshold,"ax",%progbits 1016 .align 1 1017 .global HAL_UARTEx_SetRxFifoThreshold 1018 .syntax unified 1019 .thumb 1020 .thumb_func 1022 HAL_UARTEx_SetRxFifoThreshold: 1023 .LVL83: 1024 .LFB340: 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 1025 .loc 1 657 1 is_stmt 1 view -0 1026 .cfi_startproc ARM GAS /tmp/ccnQFf6s.s page 62 1027 @ args = 0, pretend = 0, frame = 0 1028 @ frame_needed = 0, uses_anonymous_args = 0 657:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tmpcr1; 1029 .loc 1 657 1 is_stmt 0 view .LVU292 1030 0000 38B5 push {r3, r4, r5, lr} 1031 .LCFI15: 1032 .cfi_def_cfa_offset 16 1033 .cfi_offset 3, -16 1034 .cfi_offset 4, -12 1035 .cfi_offset 5, -8 1036 .cfi_offset 14, -4 658:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1037 .loc 1 658 3 is_stmt 1 view .LVU293 661:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); 1038 .loc 1 661 3 view .LVU294 662:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1039 .loc 1 662 3 view .LVU295 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1040 .loc 1 665 3 view .LVU296 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1041 .loc 1 665 3 view .LVU297 1042 0002 90F88430 ldrb r3, [r0, #132] @ zero_extendqisi2 1043 0006 012B cmp r3, #1 1044 0008 1DD0 beq .L64 1045 000a 0446 mov r4, r0 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1046 .loc 1 665 3 discriminator 2 view .LVU298 1047 000c 0123 movs r3, #1 1048 000e 80F88430 strb r3, [r0, #132] 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1049 .loc 1 665 3 discriminator 2 view .LVU299 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1050 .loc 1 667 3 view .LVU300 667:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1051 .loc 1 667 17 is_stmt 0 view .LVU301 1052 0012 2423 movs r3, #36 1053 0014 C0F88830 str r3, [r0, #136] 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1054 .loc 1 670 3 is_stmt 1 view .LVU302 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1055 .loc 1 670 12 is_stmt 0 view .LVU303 1056 0018 0368 ldr r3, [r0] 670:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1057 .loc 1 670 10 view .LVU304 1058 001a 1D68 ldr r5, [r3] 1059 .LVL84: 673:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1060 .loc 1 673 3 is_stmt 1 view .LVU305 1061 001c 1A68 ldr r2, [r3] 1062 001e 22F00102 bic r2, r2, #1 1063 0022 1A60 str r2, [r3] 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1064 .loc 1 676 3 view .LVU306 1065 0024 0268 ldr r2, [r0] 1066 0026 9368 ldr r3, [r2, #8] 1067 0028 23F06063 bic r3, r3, #234881024 1068 002c 1943 orrs r1, r1, r3 ARM GAS /tmp/ccnQFf6s.s page 63 1069 .LVL85: 676:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1070 .loc 1 676 3 is_stmt 0 view .LVU307 1071 002e 9160 str r1, [r2, #8] 679:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1072 .loc 1 679 3 is_stmt 1 view .LVU308 1073 0030 FFF7FEFF bl UARTEx_SetNbDataToProcess 1074 .LVL86: 682:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1075 .loc 1 682 3 view .LVU309 1076 0034 2368 ldr r3, [r4] 1077 0036 1D60 str r5, [r3] 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1078 .loc 1 684 3 view .LVU310 684:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1079 .loc 1 684 17 is_stmt 0 view .LVU311 1080 0038 2023 movs r3, #32 1081 003a C4F88830 str r3, [r4, #136] 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1082 .loc 1 687 3 is_stmt 1 view .LVU312 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1083 .loc 1 687 3 view .LVU313 1084 003e 0020 movs r0, #0 1085 0040 84F88400 strb r0, [r4, #132] 687:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1086 .loc 1 687 3 view .LVU314 689:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1087 .loc 1 689 3 view .LVU315 1088 .LVL87: 1089 .L63: 690:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1090 .loc 1 690 1 is_stmt 0 view .LVU316 1091 0044 38BD pop {r3, r4, r5, pc} 1092 .LVL88: 1093 .L64: 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1094 .loc 1 665 3 discriminator 1 view .LVU317 1095 0046 0220 movs r0, #2 1096 .LVL89: 665:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1097 .loc 1 665 3 discriminator 1 view .LVU318 1098 0048 FCE7 b .L63 1099 .cfi_endproc 1100 .LFE340: 1102 .section .text.HAL_UARTEx_ReceiveToIdle,"ax",%progbits 1103 .align 1 1104 .global HAL_UARTEx_ReceiveToIdle 1105 .syntax unified 1106 .thumb 1107 .thumb_func 1109 HAL_UARTEx_ReceiveToIdle: 1110 .LVL90: 1111 .LFB341: 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t *pdata8bits; 1112 .loc 1 715 1 is_stmt 1 view -0 1113 .cfi_startproc 1114 @ args = 4, pretend = 0, frame = 0 ARM GAS /tmp/ccnQFf6s.s page 64 1115 @ frame_needed = 0, uses_anonymous_args = 0 715:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint8_t *pdata8bits; 1116 .loc 1 715 1 is_stmt 0 view .LVU320 1117 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} 1118 .LCFI16: 1119 .cfi_def_cfa_offset 32 1120 .cfi_offset 4, -32 1121 .cfi_offset 5, -28 1122 .cfi_offset 6, -24 1123 .cfi_offset 7, -20 1124 .cfi_offset 8, -16 1125 .cfi_offset 9, -12 1126 .cfi_offset 10, -8 1127 .cfi_offset 14, -4 1128 0004 1D46 mov r5, r3 1129 0006 089E ldr r6, [sp, #32] 716:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t *pdata16bits; 1130 .loc 1 716 3 is_stmt 1 view .LVU321 717:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint16_t uhMask; 1131 .loc 1 717 3 view .LVU322 718:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uint32_t tickstart; 1132 .loc 1 718 3 view .LVU323 719:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1133 .loc 1 719 3 view .LVU324 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1134 .loc 1 722 3 view .LVU325 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1135 .loc 1 722 12 is_stmt 0 view .LVU326 1136 0008 D0F88C30 ldr r3, [r0, #140] 1137 .LVL91: 722:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1138 .loc 1 722 6 view .LVU327 1139 000c 202B cmp r3, #32 1140 000e 40F0A380 bne .L84 1141 0012 0446 mov r4, r0 1142 0014 0F46 mov r7, r1 1143 0016 9146 mov r9, r2 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1144 .loc 1 724 5 is_stmt 1 view .LVU328 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1145 .loc 1 724 8 is_stmt 0 view .LVU329 1146 0018 0029 cmp r1, #0 1147 001a 00F0A080 beq .L85 724:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1148 .loc 1 724 25 discriminator 1 view .LVU330 1149 001e 0AB9 cbnz r2, .L90 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1150 .loc 1 726 15 view .LVU331 1151 0020 0120 movs r0, #1 1152 .LVL92: 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1153 .loc 1 726 15 view .LVU332 1154 0022 9AE0 b .L67 1155 .LVL93: 1156 .L90: 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; 1157 .loc 1 729 5 is_stmt 1 view .LVU333 ARM GAS /tmp/ccnQFf6s.s page 65 729:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; 1158 .loc 1 729 22 is_stmt 0 view .LVU334 1159 0024 0023 movs r3, #0 1160 0026 C0F89030 str r3, [r0, #144] 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 1161 .loc 1 730 5 is_stmt 1 view .LVU335 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 1162 .loc 1 730 20 is_stmt 0 view .LVU336 1163 002a 2222 movs r2, #34 1164 .LVL94: 730:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 1165 .loc 1 730 20 view .LVU337 1166 002c C0F88C20 str r2, [r0, #140] 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 1167 .loc 1 731 5 is_stmt 1 view .LVU338 731:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 1168 .loc 1 731 26 is_stmt 0 view .LVU339 1169 0030 0122 movs r2, #1 1170 0032 C266 str r2, [r0, #108] 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1171 .loc 1 732 5 is_stmt 1 view .LVU340 732:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1172 .loc 1 732 24 is_stmt 0 view .LVU341 1173 0034 0367 str r3, [r0, #112] 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1174 .loc 1 735 5 is_stmt 1 view .LVU342 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1175 .loc 1 735 17 is_stmt 0 view .LVU343 1176 0036 FFF7FEFF bl HAL_GetTick 1177 .LVL95: 735:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1178 .loc 1 735 17 view .LVU344 1179 003a 8046 mov r8, r0 1180 .LVL96: 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount = Size; 1181 .loc 1 737 5 is_stmt 1 view .LVU345 737:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount = Size; 1182 .loc 1 737 24 is_stmt 0 view .LVU346 1183 003c A4F85C90 strh r9, [r4, #92] @ movhi 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1184 .loc 1 738 5 is_stmt 1 view .LVU347 738:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1185 .loc 1 738 24 is_stmt 0 view .LVU348 1186 0040 A4F85E90 strh r9, [r4, #94] @ movhi 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1187 .loc 1 741 5 is_stmt 1 view .LVU349 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1188 .loc 1 741 5 view .LVU350 1189 0044 A368 ldr r3, [r4, #8] 1190 0046 B3F5805F cmp r3, #4096 1191 004a 06D0 beq .L91 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1192 .loc 1 741 5 discriminator 2 view .LVU351 1193 004c A3B9 cbnz r3, .L71 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1194 .loc 1 741 5 discriminator 5 view .LVU352 1195 004e 2269 ldr r2, [r4, #16] ARM GAS /tmp/ccnQFf6s.s page 66 1196 0050 72B9 cbnz r2, .L72 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1197 .loc 1 741 5 discriminator 7 view .LVU353 1198 0052 FF22 movs r2, #255 1199 0054 A4F86020 strh r2, [r4, #96] @ movhi 1200 0058 14E0 b .L70 1201 .L91: 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1202 .loc 1 741 5 discriminator 1 view .LVU354 1203 005a 2269 ldr r2, [r4, #16] 1204 005c 22B9 cbnz r2, .L69 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1205 .loc 1 741 5 discriminator 3 view .LVU355 1206 005e 40F2FF12 movw r2, #511 1207 0062 A4F86020 strh r2, [r4, #96] @ movhi 1208 0066 0DE0 b .L70 1209 .L69: 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1210 .loc 1 741 5 discriminator 4 view .LVU356 1211 0068 FF22 movs r2, #255 1212 006a A4F86020 strh r2, [r4, #96] @ movhi 1213 006e 09E0 b .L70 1214 .L72: 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1215 .loc 1 741 5 discriminator 8 view .LVU357 1216 0070 7F22 movs r2, #127 1217 0072 A4F86020 strh r2, [r4, #96] @ movhi 1218 0076 05E0 b .L70 1219 .L71: 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1220 .loc 1 741 5 discriminator 6 view .LVU358 1221 0078 B3F1805F cmp r3, #268435456 1222 007c 0CD0 beq .L92 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1223 .loc 1 741 5 discriminator 10 view .LVU359 1224 007e 0022 movs r2, #0 1225 0080 A4F86020 strh r2, [r4, #96] @ movhi 1226 .L70: 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1227 .loc 1 741 5 discriminator 13 view .LVU360 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1228 .loc 1 742 5 view .LVU361 742:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1229 .loc 1 742 12 is_stmt 0 view .LVU362 1230 0084 B4F86090 ldrh r9, [r4, #96] 1231 .LVL97: 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1232 .loc 1 745 5 is_stmt 1 view .LVU363 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1233 .loc 1 745 8 is_stmt 0 view .LVU364 1234 0088 B3F5805F cmp r3, #4096 1235 008c 0ED0 beq .L93 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1236 .loc 1 753 19 view .LVU365 1237 008e 4FF0000A mov r10, #0 1238 .LVL98: 1239 .L75: ARM GAS /tmp/ccnQFf6s.s page 67 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1240 .loc 1 757 5 is_stmt 1 view .LVU366 757:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1241 .loc 1 757 12 is_stmt 0 view .LVU367 1242 0092 0023 movs r3, #0 1243 0094 2B80 strh r3, [r5] @ movhi 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1244 .loc 1 760 5 is_stmt 1 view .LVU368 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1245 .loc 1 760 11 is_stmt 0 view .LVU369 1246 0096 2AE0 b .L76 1247 .LVL99: 1248 .L92: 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1249 .loc 1 741 5 is_stmt 1 discriminator 9 view .LVU370 1250 0098 2269 ldr r2, [r4, #16] 1251 009a 1AB9 cbnz r2, .L74 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1252 .loc 1 741 5 discriminator 11 view .LVU371 1253 009c 7F22 movs r2, #127 1254 009e A4F86020 strh r2, [r4, #96] @ movhi 1255 00a2 EFE7 b .L70 1256 .L74: 741:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** uhMask = huart->Mask; 1257 .loc 1 741 5 discriminator 12 view .LVU372 1258 00a4 3F22 movs r2, #63 1259 00a6 A4F86020 strh r2, [r4, #96] @ movhi 1260 00aa EBE7 b .L70 1261 .LVL100: 1262 .L93: 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1263 .loc 1 745 71 is_stmt 0 discriminator 1 view .LVU373 1264 00ac 2369 ldr r3, [r4, #16] 745:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1265 .loc 1 745 56 discriminator 1 view .LVU374 1266 00ae 13B1 cbz r3, .L88 753:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1267 .loc 1 753 19 view .LVU375 1268 00b0 4FF0000A mov r10, #0 1269 00b4 EDE7 b .L75 1270 .L88: 748:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1271 .loc 1 748 19 view .LVU376 1272 00b6 BA46 mov r10, r7 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData; 1273 .loc 1 747 19 view .LVU377 1274 00b8 0027 movs r7, #0 1275 .LVL101: 747:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData; 1276 .loc 1 747 19 view .LVU378 1277 00ba EAE7 b .L75 1278 .LVL102: 1279 .L96: 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; 1280 .loc 1 772 11 is_stmt 1 view .LVU379 772:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; 1281 .loc 1 772 30 is_stmt 0 view .LVU380 ARM GAS /tmp/ccnQFf6s.s page 68 1282 00bc 0223 movs r3, #2 1283 00be 2367 str r3, [r4, #112] 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1284 .loc 1 773 11 is_stmt 1 view .LVU381 773:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1285 .loc 1 773 26 is_stmt 0 view .LVU382 1286 00c0 2023 movs r3, #32 1287 00c2 C4F88C30 str r3, [r4, #140] 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1288 .loc 1 775 11 is_stmt 1 view .LVU383 775:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1289 .loc 1 775 18 is_stmt 0 view .LVU384 1290 00c6 0020 movs r0, #0 1291 00c8 47E0 b .L67 1292 .L97: 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++; 1293 .loc 1 784 11 is_stmt 1 view .LVU385 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++; 1294 .loc 1 784 52 is_stmt 0 view .LVU386 1295 00ca 5B6A ldr r3, [r3, #36] 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++; 1296 .loc 1 784 26 view .LVU387 1297 00cc 09EA0303 and r3, r9, r3 784:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata16bits++; 1298 .loc 1 784 24 view .LVU388 1299 00d0 2AF8023B strh r3, [r10], #2 @ movhi 1300 .LVL103: 785:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1301 .loc 1 785 11 is_stmt 1 view .LVU389 1302 .L80: 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount--; 1303 .loc 1 793 9 view .LVU390 1304 00d4 2B88 ldrh r3, [r5] 793:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxXferCount--; 1305 .loc 1 793 16 is_stmt 0 view .LVU391 1306 00d6 0133 adds r3, r3, #1 1307 00d8 2B80 strh r3, [r5] @ movhi 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1308 .loc 1 794 9 is_stmt 1 view .LVU392 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1309 .loc 1 794 14 is_stmt 0 view .LVU393 1310 00da B4F85E30 ldrh r3, [r4, #94] 1311 00de 9BB2 uxth r3, r3 794:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1312 .loc 1 794 27 view .LVU394 1313 00e0 013B subs r3, r3, #1 1314 00e2 9BB2 uxth r3, r3 1315 00e4 A4F85E30 strh r3, [r4, #94] @ movhi 1316 .L78: 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1317 .loc 1 798 7 is_stmt 1 view .LVU395 798:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1318 .loc 1 798 10 is_stmt 0 view .LVU396 1319 00e8 B6F1FF3F cmp r6, #-1 1320 00ec 1BD1 bne .L94 1321 .L76: 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { ARM GAS /tmp/ccnQFf6s.s page 69 1322 .loc 1 760 31 is_stmt 1 view .LVU397 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1323 .loc 1 760 17 is_stmt 0 view .LVU398 1324 00ee B4F85E20 ldrh r2, [r4, #94] 1325 00f2 92B2 uxth r2, r2 760:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1326 .loc 1 760 31 view .LVU399 1327 00f4 22B3 cbz r2, .L95 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1328 .loc 1 763 7 is_stmt 1 view .LVU400 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1329 .loc 1 763 11 is_stmt 0 view .LVU401 1330 00f6 2368 ldr r3, [r4] 1331 00f8 DA69 ldr r2, [r3, #28] 763:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1332 .loc 1 763 10 view .LVU402 1333 00fa 12F0100F tst r2, #16 1334 00fe 04D0 beq .L77 766:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1335 .loc 1 766 9 is_stmt 1 view .LVU403 1336 0100 1022 movs r2, #16 1337 0102 1A62 str r2, [r3, #32] 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1338 .loc 1 770 9 view .LVU404 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1339 .loc 1 770 13 is_stmt 0 view .LVU405 1340 0104 2B88 ldrh r3, [r5] 770:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1341 .loc 1 770 12 view .LVU406 1342 0106 002B cmp r3, #0 1343 0108 D8D1 bne .L96 1344 .L77: 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1345 .loc 1 780 7 is_stmt 1 view .LVU407 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1346 .loc 1 780 11 is_stmt 0 view .LVU408 1347 010a 2368 ldr r3, [r4] 1348 010c DA69 ldr r2, [r3, #28] 780:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1349 .loc 1 780 10 view .LVU409 1350 010e 12F0200F tst r2, #32 1351 0112 E9D0 beq .L78 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1352 .loc 1 782 9 is_stmt 1 view .LVU410 782:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1353 .loc 1 782 12 is_stmt 0 view .LVU411 1354 0114 002F cmp r7, #0 1355 0116 D8D0 beq .L97 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++; 1356 .loc 1 789 11 is_stmt 1 view .LVU412 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++; 1357 .loc 1 789 50 is_stmt 0 view .LVU413 1358 0118 5A6A ldr r2, [r3, #36] 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++; 1359 .loc 1 789 58 view .LVU414 1360 011a 5FFA89F3 uxtb r3, r9 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++; ARM GAS /tmp/ccnQFf6s.s page 70 1361 .loc 1 789 25 view .LVU415 1362 011e 1340 ands r3, r3, r2 789:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** pdata8bits++; 1363 .loc 1 789 23 view .LVU416 1364 0120 07F8013B strb r3, [r7], #1 1365 .LVL104: 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1366 .loc 1 790 11 is_stmt 1 view .LVU417 790:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1367 .loc 1 790 11 is_stmt 0 view .LVU418 1368 0124 D6E7 b .L80 1369 .L94: 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1370 .loc 1 800 9 is_stmt 1 view .LVU419 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1371 .loc 1 800 15 is_stmt 0 view .LVU420 1372 0126 FFF7FEFF bl HAL_GetTick 1373 .LVL105: 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1374 .loc 1 800 29 discriminator 1 view .LVU421 1375 012a A0EB0800 sub r0, r0, r8 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1376 .loc 1 800 12 discriminator 1 view .LVU422 1377 012e B042 cmp r0, r6 1378 0130 01D8 bhi .L82 800:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1379 .loc 1 800 53 discriminator 1 view .LVU423 1380 0132 002E cmp r6, #0 1381 0134 DBD1 bne .L76 1382 .L82: 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1383 .loc 1 802 11 is_stmt 1 view .LVU424 802:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1384 .loc 1 802 26 is_stmt 0 view .LVU425 1385 0136 2023 movs r3, #32 1386 0138 C4F88C30 str r3, [r4, #140] 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1387 .loc 1 804 11 is_stmt 1 view .LVU426 804:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1388 .loc 1 804 18 is_stmt 0 view .LVU427 1389 013c 0320 movs r0, #3 1390 013e 0CE0 b .L67 1391 .L95: 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ 1392 .loc 1 810 5 is_stmt 1 view .LVU428 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ 1393 .loc 1 810 19 is_stmt 0 view .LVU429 1394 0140 B4F85C30 ldrh r3, [r4, #92] 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ 1395 .loc 1 810 39 view .LVU430 1396 0144 B4F85E20 ldrh r2, [r4, #94] 1397 0148 92B2 uxth r2, r2 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ 1398 .loc 1 810 32 view .LVU431 1399 014a 9B1A subs r3, r3, r2 810:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ 1400 .loc 1 810 12 view .LVU432 ARM GAS /tmp/ccnQFf6s.s page 71 1401 014c 2B80 strh r3, [r5] @ movhi 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1402 .loc 1 812 5 is_stmt 1 view .LVU433 812:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1403 .loc 1 812 20 is_stmt 0 view .LVU434 1404 014e 2023 movs r3, #32 1405 0150 C4F88C30 str r3, [r4, #140] 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1406 .loc 1 814 5 is_stmt 1 view .LVU435 814:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1407 .loc 1 814 12 is_stmt 0 view .LVU436 1408 0154 0020 movs r0, #0 1409 0156 00E0 b .L67 1410 .LVL106: 1411 .L84: 818:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1412 .loc 1 818 12 view .LVU437 1413 0158 0220 movs r0, #2 1414 .LVL107: 1415 .L67: 820:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1416 .loc 1 820 1 view .LVU438 1417 015a BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} 1418 .LVL108: 1419 .L85: 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1420 .loc 1 726 15 view .LVU439 1421 015e 0120 movs r0, #1 1422 .LVL109: 726:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1423 .loc 1 726 15 view .LVU440 1424 0160 FBE7 b .L67 1425 .cfi_endproc 1426 .LFE341: 1428 .section .text.HAL_UARTEx_ReceiveToIdle_IT,"ax",%progbits 1429 .align 1 1430 .global HAL_UARTEx_ReceiveToIdle_IT 1431 .syntax unified 1432 .thumb 1433 .thumb_func 1435 HAL_UARTEx_ReceiveToIdle_IT: 1436 .LVL110: 1437 .LFB342: 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; 1438 .loc 1 837 1 is_stmt 1 view -0 1439 .cfi_startproc 1440 @ args = 0, pretend = 0, frame = 0 1441 @ frame_needed = 0, uses_anonymous_args = 0 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1442 .loc 1 838 3 view .LVU442 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1443 .loc 1 841 3 view .LVU443 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1444 .loc 1 841 12 is_stmt 0 view .LVU444 1445 0000 D0F88C30 ldr r3, [r0, #140] 841:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1446 .loc 1 841 6 view .LVU445 ARM GAS /tmp/ccnQFf6s.s page 72 1447 0004 202B cmp r3, #32 1448 0006 1ED1 bne .L102 837:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; 1449 .loc 1 837 1 view .LVU446 1450 0008 10B5 push {r4, lr} 1451 .LCFI17: 1452 .cfi_def_cfa_offset 8 1453 .cfi_offset 4, -8 1454 .cfi_offset 14, -4 1455 000a 0446 mov r4, r0 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1456 .loc 1 843 5 is_stmt 1 view .LVU447 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1457 .loc 1 843 8 is_stmt 0 view .LVU448 1458 000c E9B1 cbz r1, .L103 843:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1459 .loc 1 843 25 discriminator 1 view .LVU449 1460 000e 0AB9 cbnz r2, .L110 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1461 .loc 1 845 14 view .LVU450 1462 0010 0120 movs r0, #1 1463 .LVL111: 1464 .L99: 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1465 .loc 1 874 1 view .LVU451 1466 0012 10BD pop {r4, pc} 1467 .LVL112: 1468 .L110: 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 1469 .loc 1 849 5 is_stmt 1 view .LVU452 849:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 1470 .loc 1 849 26 is_stmt 0 view .LVU453 1471 0014 0123 movs r3, #1 1472 0016 C366 str r3, [r0, #108] 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1473 .loc 1 850 5 is_stmt 1 view .LVU454 850:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1474 .loc 1 850 24 is_stmt 0 view .LVU455 1475 0018 0023 movs r3, #0 1476 001a 0367 str r3, [r0, #112] 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1477 .loc 1 852 5 is_stmt 1 view .LVU456 852:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1478 .loc 1 852 11 is_stmt 0 view .LVU457 1479 001c FFF7FEFF bl UART_Start_Receive_IT 1480 .LVL113: 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1481 .loc 1 854 5 is_stmt 1 view .LVU458 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1482 .loc 1 854 14 is_stmt 0 view .LVU459 1483 0020 E36E ldr r3, [r4, #108] 854:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1484 .loc 1 854 8 view .LVU460 1485 0022 012B cmp r3, #1 1486 0024 01D0 beq .L111 865:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1487 .loc 1 865 14 view .LVU461 ARM GAS /tmp/ccnQFf6s.s page 73 1488 0026 0120 movs r0, #1 1489 .LVL114: 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1490 .loc 1 868 5 is_stmt 1 view .LVU462 868:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1491 .loc 1 868 12 is_stmt 0 view .LVU463 1492 0028 F3E7 b .L99 1493 .LVL115: 1494 .L111: 856:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 1495 .loc 1 856 7 is_stmt 1 view .LVU464 1496 002a 2368 ldr r3, [r4] 1497 002c 1022 movs r2, #16 1498 002e 1A62 str r2, [r3, #32] 1499 .L101: 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1500 .loc 1 857 7 discriminator 1 view .LVU465 1501 .LBB32: 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1502 .loc 1 857 7 discriminator 1 view .LVU466 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1503 .loc 1 857 7 discriminator 1 view .LVU467 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1504 .loc 1 857 7 discriminator 1 view .LVU468 1505 0030 2268 ldr r2, [r4] 1506 .LVL116: 1507 .LBB33: 1508 .LBI33: 1151:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1509 .loc 2 1151 31 view .LVU469 1510 .LBB34: 1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 1511 .loc 2 1153 5 view .LVU470 1155:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1512 .loc 2 1155 4 view .LVU471 1513 .syntax unified 1514 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1515 0032 52E8003F ldrex r3, [r2] 1516 @ 0 "" 2 1517 .LVL117: 1156:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1518 .loc 2 1156 4 view .LVU472 1156:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1519 .loc 2 1156 4 is_stmt 0 view .LVU473 1520 .thumb 1521 .syntax unified 1522 .LBE34: 1523 .LBE33: 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1524 .loc 1 857 7 discriminator 1 view .LVU474 1525 0036 43F01003 orr r3, r3, #16 1526 .LVL118: 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1527 .loc 1 857 7 is_stmt 1 discriminator 1 view .LVU475 1528 .LBB35: 1529 .LBI35: 1202:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccnQFf6s.s page 74 1530 .loc 2 1202 31 view .LVU476 1531 .LBB36: 1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 1532 .loc 2 1204 4 view .LVU477 1206:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1533 .loc 2 1206 4 view .LVU478 1534 .syntax unified 1535 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1536 003a 42E80031 strex r1, r3, [r2] 1537 @ 0 "" 2 1538 .LVL119: 1539 .loc 2 1207 4 view .LVU479 1540 .loc 2 1207 4 is_stmt 0 view .LVU480 1541 .thumb 1542 .syntax unified 1543 .LBE36: 1544 .LBE35: 857:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1545 .loc 1 857 7 discriminator 1 view .LVU481 1546 003e 0029 cmp r1, #0 1547 0040 F6D1 bne .L101 1548 .LBE32: 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1549 .loc 1 838 21 view .LVU482 1550 0042 0020 movs r0, #0 1551 .LBB37: 1552 0044 E5E7 b .L99 1553 .LVL120: 1554 .L102: 1555 .LCFI18: 1556 .cfi_def_cfa_offset 0 1557 .cfi_restore 4 1558 .cfi_restore 14 838:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1559 .loc 1 838 21 view .LVU483 1560 .LBE37: 872:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1561 .loc 1 872 12 view .LVU484 1562 0046 0220 movs r0, #2 1563 .LVL121: 874:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1564 .loc 1 874 1 view .LVU485 1565 0048 7047 bx lr 1566 .LVL122: 1567 .L103: 1568 .LCFI19: 1569 .cfi_def_cfa_offset 8 1570 .cfi_offset 4, -8 1571 .cfi_offset 14, -4 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1572 .loc 1 845 14 view .LVU486 1573 004a 0120 movs r0, #1 1574 .LVL123: 845:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1575 .loc 1 845 14 view .LVU487 1576 004c E1E7 b .L99 1577 .cfi_endproc ARM GAS /tmp/ccnQFf6s.s page 75 1578 .LFE342: 1580 .section .text.HAL_UARTEx_ReceiveToIdle_DMA,"ax",%progbits 1581 .align 1 1582 .global HAL_UARTEx_ReceiveToIdle_DMA 1583 .syntax unified 1584 .thumb 1585 .thumb_func 1587 HAL_UARTEx_ReceiveToIdle_DMA: 1588 .LVL124: 1589 .LFB343: 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status; 1590 .loc 1 894 1 is_stmt 1 view -0 1591 .cfi_startproc 1592 @ args = 0, pretend = 0, frame = 0 1593 @ frame_needed = 0, uses_anonymous_args = 0 895:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1594 .loc 1 895 3 view .LVU489 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1595 .loc 1 898 3 view .LVU490 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1596 .loc 1 898 12 is_stmt 0 view .LVU491 1597 0000 D0F88C30 ldr r3, [r0, #140] 898:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1598 .loc 1 898 6 view .LVU492 1599 0004 202B cmp r3, #32 1600 0006 1FD1 bne .L116 894:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** HAL_StatusTypeDef status; 1601 .loc 1 894 1 view .LVU493 1602 0008 10B5 push {r4, lr} 1603 .LCFI20: 1604 .cfi_def_cfa_offset 8 1605 .cfi_offset 4, -8 1606 .cfi_offset 14, -4 1607 000a 0446 mov r4, r0 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1608 .loc 1 900 5 is_stmt 1 view .LVU494 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1609 .loc 1 900 8 is_stmt 0 view .LVU495 1610 000c F1B1 cbz r1, .L117 900:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1611 .loc 1 900 25 discriminator 1 view .LVU496 1612 000e 0AB9 cbnz r2, .L124 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1613 .loc 1 902 14 view .LVU497 1614 0010 0120 movs r0, #1 1615 .LVL125: 1616 .L113: 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1617 .loc 1 935 1 view .LVU498 1618 0012 10BD pop {r4, pc} 1619 .LVL126: 1620 .L124: 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 1621 .loc 1 906 5 is_stmt 1 view .LVU499 906:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; 1622 .loc 1 906 26 is_stmt 0 view .LVU500 1623 0014 0123 movs r3, #1 ARM GAS /tmp/ccnQFf6s.s page 76 1624 0016 C366 str r3, [r0, #108] 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1625 .loc 1 907 5 is_stmt 1 view .LVU501 907:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1626 .loc 1 907 24 is_stmt 0 view .LVU502 1627 0018 0023 movs r3, #0 1628 001a 0367 str r3, [r0, #112] 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1629 .loc 1 909 5 is_stmt 1 view .LVU503 909:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1630 .loc 1 909 15 is_stmt 0 view .LVU504 1631 001c FFF7FEFF bl UART_Start_Receive_DMA 1632 .LVL127: 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1633 .loc 1 912 5 is_stmt 1 view .LVU505 912:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1634 .loc 1 912 8 is_stmt 0 view .LVU506 1635 0020 0028 cmp r0, #0 1636 0022 F6D1 bne .L113 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1637 .loc 1 914 7 is_stmt 1 view .LVU507 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1638 .loc 1 914 16 is_stmt 0 view .LVU508 1639 0024 E36E ldr r3, [r4, #108] 914:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** { 1640 .loc 1 914 10 view .LVU509 1641 0026 012B cmp r3, #1 1642 0028 01D0 beq .L125 925:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1643 .loc 1 925 16 view .LVU510 1644 002a 0120 movs r0, #1 1645 .LVL128: 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1646 .loc 1 929 5 is_stmt 1 view .LVU511 929:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1647 .loc 1 929 12 is_stmt 0 view .LVU512 1648 002c F1E7 b .L113 1649 .LVL129: 1650 .L125: 916:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 1651 .loc 1 916 9 is_stmt 1 view .LVU513 1652 002e 2368 ldr r3, [r4] 1653 0030 1022 movs r2, #16 1654 0032 1A62 str r2, [r3, #32] 1655 .L115: 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1656 .loc 1 917 9 discriminator 1 view .LVU514 1657 .LBB38: 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1658 .loc 1 917 9 discriminator 1 view .LVU515 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1659 .loc 1 917 9 discriminator 1 view .LVU516 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1660 .loc 1 917 9 discriminator 1 view .LVU517 1661 0034 2268 ldr r2, [r4] 1662 .LVL130: 1663 .LBB39: ARM GAS /tmp/ccnQFf6s.s page 77 1664 .LBI39: 1151:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1665 .loc 2 1151 31 view .LVU518 1666 .LBB40: 1153:Drivers/CMSIS/Include/cmsis_gcc.h **** 1667 .loc 2 1153 5 view .LVU519 1155:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1668 .loc 2 1155 4 view .LVU520 1669 .syntax unified 1670 @ 1155 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1671 0036 52E8003F ldrex r3, [r2] 1672 @ 0 "" 2 1673 .LVL131: 1156:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1674 .loc 2 1156 4 view .LVU521 1156:Drivers/CMSIS/Include/cmsis_gcc.h **** } 1675 .loc 2 1156 4 is_stmt 0 view .LVU522 1676 .thumb 1677 .syntax unified 1678 .LBE40: 1679 .LBE39: 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1680 .loc 1 917 9 discriminator 1 view .LVU523 1681 003a 43F01003 orr r3, r3, #16 1682 .LVL132: 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1683 .loc 1 917 9 is_stmt 1 discriminator 1 view .LVU524 1684 .LBB41: 1685 .LBI41: 1202:Drivers/CMSIS/Include/cmsis_gcc.h **** { 1686 .loc 2 1202 31 view .LVU525 1687 .LBB42: 1204:Drivers/CMSIS/Include/cmsis_gcc.h **** 1688 .loc 2 1204 4 view .LVU526 1206:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 1689 .loc 2 1206 4 view .LVU527 1690 .syntax unified 1691 @ 1206 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1692 003e 42E80031 strex r1, r3, [r2] 1693 @ 0 "" 2 1694 .LVL133: 1695 .loc 2 1207 4 view .LVU528 1696 .loc 2 1207 4 is_stmt 0 view .LVU529 1697 .thumb 1698 .syntax unified 1699 .LBE42: 1700 .LBE41: 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1701 .loc 1 917 9 discriminator 1 view .LVU530 1702 0042 0029 cmp r1, #0 1703 0044 F6D1 bne .L115 1704 0046 E4E7 b .L113 1705 .LVL134: 1706 .L116: 1707 .LCFI21: 1708 .cfi_def_cfa_offset 0 1709 .cfi_restore 4 ARM GAS /tmp/ccnQFf6s.s page 78 1710 .cfi_restore 14 917:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1711 .loc 1 917 9 discriminator 1 view .LVU531 1712 .LBE38: 933:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1713 .loc 1 933 12 view .LVU532 1714 0048 0220 movs r0, #2 1715 .LVL135: 935:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1716 .loc 1 935 1 view .LVU533 1717 004a 7047 bx lr 1718 .LVL136: 1719 .L117: 1720 .LCFI22: 1721 .cfi_def_cfa_offset 8 1722 .cfi_offset 4, -8 1723 .cfi_offset 14, -4 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1724 .loc 1 902 14 view .LVU534 1725 004c 0120 movs r0, #1 1726 .LVL137: 902:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1727 .loc 1 902 14 view .LVU535 1728 004e E0E7 b .L113 1729 .cfi_endproc 1730 .LFE343: 1732 .section .text.HAL_UARTEx_GetRxEventType,"ax",%progbits 1733 .align 1 1734 .global HAL_UARTEx_GetRxEventType 1735 .syntax unified 1736 .thumb 1737 .thumb_func 1739 HAL_UARTEx_GetRxEventType: 1740 .LVL138: 1741 .LFB344: 962:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** /* Return Rx Event type value, as stored in UART handle */ 1742 .loc 1 962 1 is_stmt 1 view -0 1743 .cfi_startproc 1744 @ args = 0, pretend = 0, frame = 0 1745 @ frame_needed = 0, uses_anonymous_args = 0 1746 @ link register save eliminated. 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1747 .loc 1 964 3 view .LVU537 964:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** } 1748 .loc 1 964 16 is_stmt 0 view .LVU538 1749 0000 006F ldr r0, [r0, #112] 1750 .LVL139: 965:Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c **** 1751 .loc 1 965 1 view .LVU539 1752 0002 7047 bx lr 1753 .cfi_endproc 1754 .LFE344: 1756 .section .rodata.denominator.0,"a" 1757 .align 2 1760 denominator.0: 1761 0000 08040204 .ascii "\010\004\002\004\010\001\001\001" 1761 08010101 ARM GAS /tmp/ccnQFf6s.s page 79 1762 .section .rodata.numerator.1,"a" 1763 .align 2 1766 numerator.1: 1767 0000 01010103 .ascii "\001\001\001\003\007\001\000\000" 1767 07010000 1768 .text 1769 .Letext0: 1770 .file 3 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach 1771 .file 4 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/ 1772 .file 5 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h" 1773 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h" 1774 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h" 1775 .file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h" 1776 .file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h" 1777 .file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h" 1778 .file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h" ARM GAS /tmp/ccnQFf6s.s page 80 DEFINED SYMBOLS *ABS*:00000000 stm32g4xx_hal_uart_ex.c /tmp/ccnQFf6s.s:21 .text.UARTEx_Wakeup_AddressConfig:00000000 $t /tmp/ccnQFf6s.s:26 .text.UARTEx_Wakeup_AddressConfig:00000000 UARTEx_Wakeup_AddressConfig /tmp/ccnQFf6s.s:65 .text.UARTEx_SetNbDataToProcess:00000000 $t /tmp/ccnQFf6s.s:70 .text.UARTEx_SetNbDataToProcess:00000000 UARTEx_SetNbDataToProcess /tmp/ccnQFf6s.s:156 .text.UARTEx_SetNbDataToProcess:00000044 $d /tmp/ccnQFf6s.s:1766 .rodata.numerator.1:00000000 numerator.1 /tmp/ccnQFf6s.s:1760 .rodata.denominator.0:00000000 denominator.0 /tmp/ccnQFf6s.s:162 .text.HAL_RS485Ex_Init:00000000 $t /tmp/ccnQFf6s.s:168 .text.HAL_RS485Ex_Init:00000000 HAL_RS485Ex_Init /tmp/ccnQFf6s.s:305 .text.HAL_UARTEx_WakeupCallback:00000000 $t /tmp/ccnQFf6s.s:311 .text.HAL_UARTEx_WakeupCallback:00000000 HAL_UARTEx_WakeupCallback /tmp/ccnQFf6s.s:326 .text.HAL_UARTEx_RxFifoFullCallback:00000000 $t /tmp/ccnQFf6s.s:332 .text.HAL_UARTEx_RxFifoFullCallback:00000000 HAL_UARTEx_RxFifoFullCallback /tmp/ccnQFf6s.s:347 .text.HAL_UARTEx_TxFifoEmptyCallback:00000000 $t /tmp/ccnQFf6s.s:353 .text.HAL_UARTEx_TxFifoEmptyCallback:00000000 HAL_UARTEx_TxFifoEmptyCallback /tmp/ccnQFf6s.s:368 .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 $t /tmp/ccnQFf6s.s:374 .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 HAL_MultiProcessorEx_AddressLength_Set /tmp/ccnQFf6s.s:438 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 $t /tmp/ccnQFf6s.s:444 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 HAL_UARTEx_StopModeWakeUpSourceConfig /tmp/ccnQFf6s.s:570 .text.HAL_UARTEx_EnableStopMode:00000000 $t /tmp/ccnQFf6s.s:576 .text.HAL_UARTEx_EnableStopMode:00000000 HAL_UARTEx_EnableStopMode /tmp/ccnQFf6s.s:669 .text.HAL_UARTEx_DisableStopMode:00000000 $t /tmp/ccnQFf6s.s:675 .text.HAL_UARTEx_DisableStopMode:00000000 HAL_UARTEx_DisableStopMode /tmp/ccnQFf6s.s:767 .text.HAL_UARTEx_EnableFifoMode:00000000 $t /tmp/ccnQFf6s.s:773 .text.HAL_UARTEx_EnableFifoMode:00000000 HAL_UARTEx_EnableFifoMode /tmp/ccnQFf6s.s:852 .text.HAL_UARTEx_DisableFifoMode:00000000 $t /tmp/ccnQFf6s.s:858 .text.HAL_UARTEx_DisableFifoMode:00000000 HAL_UARTEx_DisableFifoMode /tmp/ccnQFf6s.s:929 .text.HAL_UARTEx_SetTxFifoThreshold:00000000 $t /tmp/ccnQFf6s.s:935 .text.HAL_UARTEx_SetTxFifoThreshold:00000000 HAL_UARTEx_SetTxFifoThreshold /tmp/ccnQFf6s.s:1016 .text.HAL_UARTEx_SetRxFifoThreshold:00000000 $t /tmp/ccnQFf6s.s:1022 .text.HAL_UARTEx_SetRxFifoThreshold:00000000 HAL_UARTEx_SetRxFifoThreshold /tmp/ccnQFf6s.s:1103 .text.HAL_UARTEx_ReceiveToIdle:00000000 $t /tmp/ccnQFf6s.s:1109 .text.HAL_UARTEx_ReceiveToIdle:00000000 HAL_UARTEx_ReceiveToIdle /tmp/ccnQFf6s.s:1429 .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 $t /tmp/ccnQFf6s.s:1435 .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 HAL_UARTEx_ReceiveToIdle_IT /tmp/ccnQFf6s.s:1581 .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 $t /tmp/ccnQFf6s.s:1587 .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 HAL_UARTEx_ReceiveToIdle_DMA /tmp/ccnQFf6s.s:1733 .text.HAL_UARTEx_GetRxEventType:00000000 $t /tmp/ccnQFf6s.s:1739 .text.HAL_UARTEx_GetRxEventType:00000000 HAL_UARTEx_GetRxEventType /tmp/ccnQFf6s.s:1757 .rodata.denominator.0:00000000 $d /tmp/ccnQFf6s.s:1763 .rodata.numerator.1:00000000 $d UNDEFINED SYMBOLS UART_SetConfig UART_CheckIdleState HAL_UART_MspInit UART_AdvFeatureConfig HAL_GetTick UART_WaitOnFlagUntilTimeout UART_Start_Receive_IT UART_Start_Receive_DMA