ARM GAS /tmp/ccx0f9ME.s page 1 1 .cpu cortex-m4 2 .arch armv7e-m 3 .fpu fpv4-sp-d16 4 .eabi_attribute 27, 1 5 .eabi_attribute 28, 1 6 .eabi_attribute 20, 1 7 .eabi_attribute 21, 1 8 .eabi_attribute 23, 3 9 .eabi_attribute 24, 1 10 .eabi_attribute 25, 1 11 .eabi_attribute 26, 1 12 .eabi_attribute 30, 1 13 .eabi_attribute 34, 1 14 .eabi_attribute 18, 4 15 .file "si5351.c" 16 .text 17 .Ltext0: 18 .cfi_sections .debug_frame 19 .file 1 "Src/si5351.c" 20 .section .text.si5351_write8,"ax",%progbits 21 .align 1 22 .global si5351_write8 23 .syntax unified 24 .thumb 25 .thumb_func 27 si5351_write8: 28 .LVL0: 29 .LFB329: 1:Src/si5351.c **** #include "main.h" 2:Src/si5351.c **** #include "stm32g4xx_hal.h" 3:Src/si5351.c **** #include 4:Src/si5351.c **** #include "si5351.h" 5:Src/si5351.c **** 6:Src/si5351.c **** uint8_t oeb; 7:Src/si5351.c **** 8:Src/si5351.c **** void si5351_write8 (uint8_t reg, uint8_t value){ 30 .loc 1 8 48 view -0 31 .cfi_startproc 32 @ args = 0, pretend = 0, frame = 8 33 @ frame_needed = 0, uses_anonymous_args = 0 34 .loc 1 8 48 is_stmt 0 view .LVU1 35 0000 10B5 push {r4, lr} 36 .LCFI0: 37 .cfi_def_cfa_offset 8 38 .cfi_offset 4, -8 39 .cfi_offset 14, -4 40 0002 86B0 sub sp, sp, #24 41 .LCFI1: 42 .cfi_def_cfa_offset 32 43 0004 0446 mov r4, r0 44 0006 8DF81710 strb r1, [sp, #23] 9:Src/si5351.c **** while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { } 45 .loc 1 9 2 is_stmt 1 view .LVU2 46 .LVL1: 47 .L2: 48 .loc 1 9 91 discriminator 1 view .LVU3 49 .loc 1 9 78 discriminator 1 view .LVU4 ARM GAS /tmp/ccx0f9ME.s page 2 50 .loc 1 9 9 is_stmt 0 discriminator 1 view .LVU5 51 000a 6423 movs r3, #100 52 000c 0322 movs r2, #3 53 000e C021 movs r1, #192 54 0010 0948 ldr r0, .L4 55 0012 FFF7FEFF bl HAL_I2C_IsDeviceReady 56 .LVL2: 57 .loc 1 9 78 discriminator 1 view .LVU6 58 0016 0028 cmp r0, #0 59 0018 F7D1 bne .L2 10:Src/si5351.c **** HAL_I2C_Mem_Write(&hi2c1, (uint8_t)(SI5351_ADDRESS<<1), (uint8_t)reg, I2C_MEMADD_SIZE_8BIT, (uint8 60 .loc 1 10 2 is_stmt 1 view .LVU7 61 001a 6423 movs r3, #100 62 001c 0293 str r3, [sp, #8] 63 001e 0123 movs r3, #1 64 0020 0193 str r3, [sp, #4] 65 0022 0DF11702 add r2, sp, #23 66 0026 0092 str r2, [sp] 67 0028 2246 mov r2, r4 68 002a C021 movs r1, #192 69 002c 0248 ldr r0, .L4 70 002e FFF7FEFF bl HAL_I2C_Mem_Write 71 .LVL3: 11:Src/si5351.c **** } 72 .loc 1 11 1 is_stmt 0 view .LVU8 73 0032 06B0 add sp, sp, #24 74 .LCFI2: 75 .cfi_def_cfa_offset 8 76 @ sp needed 77 0034 10BD pop {r4, pc} 78 .L5: 79 0036 00BF .align 2 80 .L4: 81 0038 00000000 .word hi2c1 82 .cfi_endproc 83 .LFE329: 85 .section .text.si5351_read8,"ax",%progbits 86 .align 1 87 .global si5351_read8 88 .syntax unified 89 .thumb 90 .thumb_func 92 si5351_read8: 93 .LVL4: 94 .LFB330: 12:Src/si5351.c **** 13:Src/si5351.c **** uint8_t si5351_read8(uint8_t reg, uint8_t *value){ 95 .loc 1 13 50 is_stmt 1 view -0 96 .cfi_startproc 97 @ args = 0, pretend = 0, frame = 8 98 @ frame_needed = 0, uses_anonymous_args = 0 99 .loc 1 13 50 is_stmt 0 view .LVU10 100 0000 10B5 push {r4, lr} 101 .LCFI3: 102 .cfi_def_cfa_offset 8 103 .cfi_offset 4, -8 104 .cfi_offset 14, -4 ARM GAS /tmp/ccx0f9ME.s page 3 105 0002 86B0 sub sp, sp, #24 106 .LCFI4: 107 .cfi_def_cfa_offset 32 108 0004 0446 mov r4, r0 109 0006 0591 str r1, [sp, #20] 14:Src/si5351.c **** HAL_StatusTypeDef status = HAL_OK; 110 .loc 1 14 2 is_stmt 1 view .LVU11 111 .LVL5: 15:Src/si5351.c **** while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { } 112 .loc 1 15 2 view .LVU12 113 .L7: 114 .loc 1 15 91 discriminator 1 view .LVU13 115 .loc 1 15 78 discriminator 1 view .LVU14 116 .loc 1 15 9 is_stmt 0 discriminator 1 view .LVU15 117 0008 6423 movs r3, #100 118 000a 0322 movs r2, #3 119 000c C021 movs r1, #192 120 000e 0948 ldr r0, .L9 121 0010 FFF7FEFF bl HAL_I2C_IsDeviceReady 122 .LVL6: 123 .loc 1 15 78 discriminator 1 view .LVU16 124 0014 0028 cmp r0, #0 125 0016 F7D1 bne .L7 16:Src/si5351.c **** status = HAL_I2C_Mem_Read(&hi2c1, // i2c handle 126 .loc 1 16 2 is_stmt 1 view .LVU17 127 .loc 1 16 11 is_stmt 0 view .LVU18 128 0018 6423 movs r3, #100 129 001a 0293 str r3, [sp, #8] 130 001c 0123 movs r3, #1 131 001e 0193 str r3, [sp, #4] 132 0020 05AA add r2, sp, #20 133 0022 0092 str r2, [sp] 134 0024 2246 mov r2, r4 135 0026 C021 movs r1, #192 136 0028 0248 ldr r0, .L9 137 002a FFF7FEFF bl HAL_I2C_Mem_Read 138 .LVL7: 17:Src/si5351.c **** (uint8_t)(SI5351_ADDRESS<<1), // i2c address, left aligned 18:Src/si5351.c **** (uint8_t)reg, // register address 19:Src/si5351.c **** I2C_MEMADD_SIZE_8BIT, // si5351 uses 8bit register addresses 20:Src/si5351.c **** (uint8_t*)(&value), // write returned data to this variable 21:Src/si5351.c **** 1, // how many bytes to expect returned 22:Src/si5351.c **** 100); // timeout 23:Src/si5351.c **** 24:Src/si5351.c **** return status; 139 .loc 1 24 3 is_stmt 1 view .LVU19 25:Src/si5351.c **** } 140 .loc 1 25 1 is_stmt 0 view .LVU20 141 002e 06B0 add sp, sp, #24 142 .LCFI5: 143 .cfi_def_cfa_offset 8 144 @ sp needed 145 0030 10BD pop {r4, pc} 146 .L10: 147 0032 00BF .align 2 148 .L9: 149 0034 00000000 .word hi2c1 ARM GAS /tmp/ccx0f9ME.s page 4 150 .cfi_endproc 151 .LFE330: 153 .global __aeabi_ui2d 154 .global __aeabi_ddiv 155 .global __aeabi_d2uiz 156 .global __aeabi_d2iz 157 .global __aeabi_i2d 158 .global __aeabi_dsub 159 .global __aeabi_dmul 160 .global __aeabi_dadd 161 .section .text.CalcRegisters,"ax",%progbits 162 .align 1 163 .global CalcRegisters 164 .syntax unified 165 .thumb 166 .thumb_func 168 CalcRegisters: 169 .LVL8: 170 .LFB331: 26:Src/si5351.c **** 27:Src/si5351.c **** 28:Src/si5351.c **** void CalcRegisters(uint32_t fout, uint8_t *regs){ 171 .loc 1 28 49 is_stmt 1 view -0 172 .cfi_startproc 173 @ args = 0, pretend = 0, frame = 0 174 @ frame_needed = 0, uses_anonymous_args = 0 175 .loc 1 28 49 is_stmt 0 view .LVU22 176 0000 2DE9F84F push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr} 177 .LCFI6: 178 .cfi_def_cfa_offset 40 179 .cfi_offset 3, -40 180 .cfi_offset 4, -36 181 .cfi_offset 5, -32 182 .cfi_offset 6, -28 183 .cfi_offset 7, -24 184 .cfi_offset 8, -20 185 .cfi_offset 9, -16 186 .cfi_offset 10, -12 187 .cfi_offset 11, -8 188 .cfi_offset 14, -4 189 0004 8046 mov r8, r0 190 0006 0C46 mov r4, r1 29:Src/si5351.c **** // uint32_t fref = SI5351_CRYSTAL_FREQ; // The reference frequency 30:Src/si5351.c **** 31:Src/si5351.c **** // Calc Output Multisynth Divider and R with e = 0 and f = 1 => msx_p2 = 0 and msx_p3 = 1 32:Src/si5351.c **** uint32_t d = 4; 191 .loc 1 32 5 is_stmt 1 view .LVU23 192 .LVL9: 33:Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY 193 .loc 1 33 5 view .LVU24 34:Src/si5351.c **** int msx_divby4 = 0; 194 .loc 1 34 5 view .LVU25 35:Src/si5351.c **** int rx_div = 0; 195 .loc 1 35 5 view .LVU26 36:Src/si5351.c **** int r = 1; 196 .loc 1 36 5 view .LVU27 37:Src/si5351.c **** ARM GAS /tmp/ccx0f9ME.s page 5 38:Src/si5351.c **** if (fout > 150e6) 197 .loc 1 38 5 view .LVU28 198 .loc 1 38 8 is_stmt 0 view .LVU29 199 0008 674B ldr r3, .L29+24 200 000a 9842 cmp r0, r3 201 000c 49D8 bhi .L20 39:Src/si5351.c **** msx_divby4 = 0x0C; // MSx_DIVBY4[1:0] = 0b11, see datasheet 4.1.3 40:Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas 202 .loc 1 40 10 is_stmt 1 view .LVU30 203 .loc 1 40 13 is_stmt 0 view .LVU31 204 000e 674B ldr r3, .L29+28 205 0010 9842 cmp r0, r3 206 0012 38D9 bls .L21 41:Src/si5351.c **** { 42:Src/si5351.c **** int rd = 0; 43:Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL)) 44:Src/si5351.c **** { 45:Src/si5351.c **** r <<= 1; 46:Src/si5351.c **** rd++; 47:Src/si5351.c **** } 48:Src/si5351.c **** rx_div = rd << 4; 49:Src/si5351.c **** 50:Src/si5351.c **** d = 600e6 / (r * fout); // Use lowest VCO frequency but handle d minimum 51:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ 52:Src/si5351.c **** d++; 53:Src/si5351.c **** 54:Src/si5351.c **** if (d * r * fout < 600e6) // VCO frequency to low check and maintain an even 55:Src/si5351.c **** d += 2; 56:Src/si5351.c **** } 57:Src/si5351.c **** else // 292968 Hz <= fout <= 150 MHz 58:Src/si5351.c **** { 59:Src/si5351.c **** d = 600e6 / fout; // Use lowest VCO frequency but handle d minimum 207 .loc 1 59 9 is_stmt 1 view .LVU32 208 .loc 1 59 19 is_stmt 0 view .LVU33 209 0014 FFF7FEFF bl __aeabi_ui2d 210 .LVL10: 211 .loc 1 59 19 view .LVU34 212 0018 0246 mov r2, r0 213 001a 0B46 mov r3, r1 214 001c 5CA1 adr r1, .L29 215 001e D1E90001 ldrd r0, [r1] 216 0022 FFF7FEFF bl __aeabi_ddiv 217 .LVL11: 218 .loc 1 59 11 view .LVU35 219 0026 FFF7FEFF bl __aeabi_d2uiz 220 .LVL12: 60:Src/si5351.c **** if (d < 6) 221 .loc 1 60 9 is_stmt 1 view .LVU36 222 .loc 1 60 12 is_stmt 0 view .LVU37 223 002a 0528 cmp r0, #5 224 002c 2ED9 bls .L23 61:Src/si5351.c **** d = 6; 62:Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d 225 .loc 1 62 14 is_stmt 1 view .LVU38 226 .loc 1 62 17 is_stmt 0 view .LVU39 227 002e 10F0010F tst r0, #1 228 0032 2CD0 beq .L18 ARM GAS /tmp/ccx0f9ME.s page 6 63:Src/si5351.c **** d++; 229 .loc 1 63 12 is_stmt 1 view .LVU40 230 .loc 1 63 13 is_stmt 0 view .LVU41 231 0034 0130 adds r0, r0, #1 232 .LVL13: 233 .loc 1 63 13 view .LVU42 234 0036 2AE0 b .L18 235 .LVL14: 236 .L16: 237 .LBB2: 45:Src/si5351.c **** rd++; 238 .loc 1 45 13 is_stmt 1 view .LVU43 45:Src/si5351.c **** rd++; 239 .loc 1 45 15 is_stmt 0 view .LVU44 240 0038 7600 lsls r6, r6, #1 241 .LVL15: 46:Src/si5351.c **** } 242 .loc 1 46 13 is_stmt 1 view .LVU45 46:Src/si5351.c **** } 243 .loc 1 46 15 is_stmt 0 view .LVU46 244 003a 0135 adds r5, r5, #1 245 .LVL16: 246 .L13: 43:Src/si5351.c **** { 247 .loc 1 43 26 is_stmt 1 view .LVU47 248 003c 7F2E cmp r6, #127 249 003e 04DC bgt .L15 43:Src/si5351.c **** { 250 .loc 1 43 32 is_stmt 0 discriminator 1 view .LVU48 251 0040 08FB06F2 mul r2, r8, r6 43:Src/si5351.c **** { 252 .loc 1 43 26 discriminator 1 view .LVU49 253 0044 594B ldr r3, .L29+28 254 0046 9A42 cmp r2, r3 255 0048 F6D9 bls .L16 256 .L15: 48:Src/si5351.c **** 257 .loc 1 48 9 is_stmt 1 view .LVU50 48:Src/si5351.c **** 258 .loc 1 48 16 is_stmt 0 view .LVU51 259 004a 2D01 lsls r5, r5, #4 260 .LVL17: 50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ 261 .loc 1 50 9 is_stmt 1 view .LVU52 50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ 262 .loc 1 50 24 is_stmt 0 view .LVU53 263 004c 3746 mov r7, r6 50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ 264 .loc 1 50 19 view .LVU54 265 004e 08FB06F0 mul r0, r8, r6 266 .LVL18: 50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ 267 .loc 1 50 19 view .LVU55 268 0052 FFF7FEFF bl __aeabi_ui2d 269 .LVL19: 50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ 270 .loc 1 50 19 view .LVU56 ARM GAS /tmp/ccx0f9ME.s page 7 271 0056 0246 mov r2, r0 272 0058 0B46 mov r3, r1 273 005a 4DA1 adr r1, .L29 274 005c D1E90001 ldrd r0, [r1] 275 0060 FFF7FEFF bl __aeabi_ddiv 276 .LVL20: 50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ 277 .loc 1 50 11 view .LVU57 278 0064 FFF7FEFF bl __aeabi_d2uiz 279 .LVL21: 51:Src/si5351.c **** d++; 280 .loc 1 51 9 is_stmt 1 view .LVU58 51:Src/si5351.c **** d++; 281 .loc 1 51 12 is_stmt 0 view .LVU59 282 0068 10F0010F tst r0, #1 283 006c 00D0 beq .L17 52:Src/si5351.c **** 284 .loc 1 52 13 is_stmt 1 view .LVU60 52:Src/si5351.c **** 285 .loc 1 52 14 is_stmt 0 view .LVU61 286 006e 0130 adds r0, r0, #1 287 .LVL22: 288 .L17: 54:Src/si5351.c **** d += 2; 289 .loc 1 54 9 is_stmt 1 view .LVU62 54:Src/si5351.c **** d += 2; 290 .loc 1 54 15 is_stmt 0 view .LVU63 291 0070 00FB07F7 mul r7, r0, r7 54:Src/si5351.c **** d += 2; 292 .loc 1 54 19 view .LVU64 293 0074 08FB07F7 mul r7, r8, r7 54:Src/si5351.c **** d += 2; 294 .loc 1 54 12 view .LVU65 295 0078 4D4B ldr r3, .L29+32 296 007a 9F42 cmp r7, r3 297 007c 4ED8 bhi .L22 55:Src/si5351.c **** } 298 .loc 1 55 13 is_stmt 1 view .LVU66 55:Src/si5351.c **** } 299 .loc 1 55 15 is_stmt 0 view .LVU67 300 007e 0230 adds r0, r0, #2 301 .LVL23: 55:Src/si5351.c **** } 302 .loc 1 55 15 view .LVU68 303 .LBE2: 34:Src/si5351.c **** int rx_div = 0; 304 .loc 1 34 9 view .LVU69 305 0080 4FF0000A mov r10, #0 306 0084 12E0 b .L12 307 .LVL24: 308 .L21: 309 .LBB3: 42:Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL)) 310 .loc 1 42 13 view .LVU70 311 0086 0025 movs r5, #0 312 .LBE3: 36:Src/si5351.c **** ARM GAS /tmp/ccx0f9ME.s page 8 313 .loc 1 36 9 view .LVU71 314 0088 0126 movs r6, #1 315 008a D7E7 b .L13 316 .LVL25: 317 .L23: 61:Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d 318 .loc 1 61 15 view .LVU72 319 008c 0620 movs r0, #6 320 .LVL26: 321 .L18: 64:Src/si5351.c **** 65:Src/si5351.c **** if (d * fout < 600e6) // VCO frequency to low check and maintain an even 322 .loc 1 65 9 is_stmt 1 view .LVU73 323 .loc 1 65 15 is_stmt 0 view .LVU74 324 008e 08FB00F2 mul r2, r8, r0 325 .loc 1 65 12 view .LVU75 326 0092 474B ldr r3, .L29+32 327 0094 9A42 cmp r2, r3 328 0096 44D8 bhi .L24 66:Src/si5351.c **** d += 2; 329 .loc 1 66 13 is_stmt 1 view .LVU76 330 .loc 1 66 15 is_stmt 0 view .LVU77 331 0098 0230 adds r0, r0, #2 332 .LVL27: 36:Src/si5351.c **** 333 .loc 1 36 9 view .LVU78 334 009a 0126 movs r6, #1 35:Src/si5351.c **** int r = 1; 335 .loc 1 35 9 view .LVU79 336 009c 0025 movs r5, #0 34:Src/si5351.c **** int rx_div = 0; 337 .loc 1 34 9 view .LVU80 338 009e AA46 mov r10, r5 339 00a0 04E0 b .L12 340 .LVL28: 341 .L20: 36:Src/si5351.c **** 342 .loc 1 36 9 view .LVU81 343 00a2 0126 movs r6, #1 35:Src/si5351.c **** int r = 1; 344 .loc 1 35 9 view .LVU82 345 00a4 0025 movs r5, #0 39:Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas 346 .loc 1 39 20 view .LVU83 347 00a6 4FF00C0A mov r10, #12 32:Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY 348 .loc 1 32 14 view .LVU84 349 00aa 0420 movs r0, #4 350 .LVL29: 351 .L12: 67:Src/si5351.c **** } 68:Src/si5351.c **** msx_p1 = 128 * d - 512; 352 .loc 1 68 5 is_stmt 1 view .LVU85 353 .loc 1 68 22 is_stmt 0 view .LVU86 354 00ac 00F10077 add r7, r0, #33554432 355 00b0 043F subs r7, r7, #4 356 .loc 1 68 12 view .LVU87 ARM GAS /tmp/ccx0f9ME.s page 9 357 00b2 FF01 lsls r7, r7, #7 358 .LVL30: 69:Src/si5351.c **** 70:Src/si5351.c **** uint32_t fvco = (uint32_t) d * r * fout; 359 .loc 1 70 5 is_stmt 1 view .LVU88 360 .loc 1 70 34 is_stmt 0 view .LVU89 361 00b4 06FB00F0 mul r0, r6, r0 362 .LVL31: 71:Src/si5351.c **** 72:Src/si5351.c **** // Calc Feedback Multisynth Divider 73:Src/si5351.c **** double fmd = (double)fvco / SI5351_CRYSTAL_FREQ; // The FMD value has been found 363 .loc 1 73 5 is_stmt 1 view .LVU90 364 .loc 1 73 18 is_stmt 0 view .LVU91 365 00b8 08FB00F0 mul r0, r8, r0 366 .LVL32: 367 .loc 1 73 18 view .LVU92 368 00bc FFF7FEFF bl __aeabi_ui2d 369 .LVL33: 370 .loc 1 73 12 view .LVU93 371 00c0 35A3 adr r3, .L29+8 372 00c2 D3E90023 ldrd r2, [r3] 373 00c6 FFF7FEFF bl __aeabi_ddiv 374 .LVL34: 375 00ca 8046 mov r8, r0 376 .LVL35: 377 .loc 1 73 12 view .LVU94 378 00cc 8946 mov r9, r1 379 .LVL36: 74:Src/si5351.c **** int a = fmd; // a is the integer part of the FMD value 380 .loc 1 74 5 is_stmt 1 view .LVU95 381 .loc 1 74 9 is_stmt 0 view .LVU96 382 00ce FFF7FEFF bl __aeabi_d2iz 383 .LVL37: 384 00d2 0646 mov r6, r0 385 .LVL38: 75:Src/si5351.c **** 76:Src/si5351.c **** double b_c = (double)fmd - a; // Get b/c 386 .loc 1 76 5 is_stmt 1 view .LVU97 387 .loc 1 76 30 is_stmt 0 view .LVU98 388 00d4 FFF7FEFF bl __aeabi_i2d 389 .LVL39: 390 .loc 1 76 30 view .LVU99 391 00d8 0246 mov r2, r0 392 00da 0B46 mov r3, r1 393 .loc 1 76 12 view .LVU100 394 00dc 4046 mov r0, r8 395 00de 4946 mov r1, r9 396 00e0 FFF7FEFF bl __aeabi_dsub 397 .LVL40: 398 00e4 8046 mov r8, r0 399 .LVL41: 400 .loc 1 76 12 view .LVU101 401 00e6 8946 mov r9, r1 402 .LVL42: 77:Src/si5351.c **** uint32_t c = 1048575UL; 403 .loc 1 77 5 is_stmt 1 view .LVU102 78:Src/si5351.c **** uint32_t b = (double)b_c * c; ARM GAS /tmp/ccx0f9ME.s page 10 404 .loc 1 78 5 view .LVU103 405 .loc 1 78 30 is_stmt 0 view .LVU104 406 00e8 2DA3 adr r3, .L29+16 407 00ea D3E90023 ldrd r2, [r3] 408 00ee FFF7FEFF bl __aeabi_dmul 409 .LVL43: 410 .loc 1 78 14 view .LVU105 411 00f2 FFF7FEFF bl __aeabi_d2uiz 412 .LVL44: 79:Src/si5351.c **** if (b > 0) 413 .loc 1 79 5 is_stmt 1 view .LVU106 414 .loc 1 79 8 is_stmt 0 view .LVU107 415 00f6 8346 mov fp, r0 416 00f8 B8B1 cbz r0, .L25 80:Src/si5351.c **** { 81:Src/si5351.c **** c = (double)b / b_c + 0.5; // Improves frequency precision in some cases 417 .loc 1 81 9 is_stmt 1 view .LVU108 418 .loc 1 81 13 is_stmt 0 view .LVU109 419 00fa FFF7FEFF bl __aeabi_ui2d 420 .LVL45: 421 .loc 1 81 23 view .LVU110 422 00fe 4246 mov r2, r8 423 0100 4B46 mov r3, r9 424 0102 FFF7FEFF bl __aeabi_ddiv 425 .LVL46: 426 .loc 1 81 29 view .LVU111 427 0106 0022 movs r2, #0 428 0108 2A4B ldr r3, .L29+36 429 010a FFF7FEFF bl __aeabi_dadd 430 .LVL47: 431 .loc 1 81 11 view .LVU112 432 010e FFF7FEFF bl __aeabi_d2uiz 433 .LVL48: 82:Src/si5351.c **** if (c > 1048575UL) 434 .loc 1 82 9 is_stmt 1 view .LVU113 435 .loc 1 82 12 is_stmt 0 view .LVU114 436 0112 B0F5801F cmp r0, #1048576 437 0116 09D3 bcc .L19 83:Src/si5351.c **** c = 1048575UL; 438 .loc 1 83 15 view .LVU115 439 0118 2748 ldr r0, .L29+40 440 .LVL49: 441 .loc 1 83 15 view .LVU116 442 011a 07E0 b .L19 443 .LVL50: 444 .L22: 34:Src/si5351.c **** int rx_div = 0; 445 .loc 1 34 9 view .LVU117 446 011c 4FF0000A mov r10, #0 447 0120 C4E7 b .L12 448 .LVL51: 449 .L24: 36:Src/si5351.c **** 450 .loc 1 36 9 view .LVU118 451 0122 0126 movs r6, #1 35:Src/si5351.c **** int r = 1; 452 .loc 1 35 9 view .LVU119 ARM GAS /tmp/ccx0f9ME.s page 11 453 0124 0025 movs r5, #0 34:Src/si5351.c **** int rx_div = 0; 454 .loc 1 34 9 view .LVU120 455 0126 AA46 mov r10, r5 456 0128 C0E7 b .L12 457 .LVL52: 458 .L25: 77:Src/si5351.c **** uint32_t b = (double)b_c * c; 459 .loc 1 77 14 view .LVU121 460 012a 2348 ldr r0, .L29+40 461 .LVL53: 462 .L19: 84:Src/si5351.c **** } 85:Src/si5351.c **** 86:Src/si5351.c **** uint32_t msnx_p1 = 128 * a + 128 * b / c - 512; // See datasheet 3.2 463 .loc 1 86 5 is_stmt 1 view .LVU122 464 .loc 1 86 38 is_stmt 0 view .LVU123 465 012c 4FEACB1B lsl fp, fp, #7 466 .LVL54: 467 .loc 1 86 42 view .LVU124 468 0130 BBFBF0F3 udiv r3, fp, r0 469 .loc 1 86 32 view .LVU125 470 0134 03EBC616 add r6, r3, r6, lsl #7 471 .LVL55: 472 .loc 1 86 14 view .LVU126 473 0138 A6F50076 sub r6, r6, #512 474 .LVL56: 87:Src/si5351.c **** uint32_t msnx_p2 = 128 * b - c * (128 * b / c); 475 .loc 1 87 5 is_stmt 1 view .LVU127 476 .loc 1 87 14 is_stmt 0 view .LVU128 477 013c 00FB13BB mls fp, r0, r3, fp 478 .LVL57: 88:Src/si5351.c **** uint32_t msnx_p3 = c; 479 .loc 1 88 5 is_stmt 1 view .LVU129 89:Src/si5351.c **** 90:Src/si5351.c **** // Feedback Multisynth Divider registers 91:Src/si5351.c **** regs[0] = (msnx_p3 >> 8) & 0xFF; 480 .loc 1 91 5 view .LVU130 481 .loc 1 91 24 is_stmt 0 view .LVU131 482 0140 030A lsrs r3, r0, #8 483 .loc 1 91 13 view .LVU132 484 0142 2370 strb r3, [r4] 92:Src/si5351.c **** regs[1] = msnx_p3 & 0xFF; 485 .loc 1 92 5 is_stmt 1 view .LVU133 486 .loc 1 92 13 is_stmt 0 view .LVU134 487 0144 6070 strb r0, [r4, #1] 93:Src/si5351.c **** regs[2] = (msnx_p1 >> 16) & 0x03; 488 .loc 1 93 5 is_stmt 1 view .LVU135 489 .loc 1 93 31 is_stmt 0 view .LVU136 490 0146 C6F30143 ubfx r3, r6, #16, #2 491 .loc 1 93 13 view .LVU137 492 014a A370 strb r3, [r4, #2] 94:Src/si5351.c **** regs[3] = (msnx_p1 >> 8) & 0xFF; 493 .loc 1 94 5 is_stmt 1 view .LVU138 494 .loc 1 94 24 is_stmt 0 view .LVU139 495 014c 330A lsrs r3, r6, #8 496 .loc 1 94 13 view .LVU140 ARM GAS /tmp/ccx0f9ME.s page 12 497 014e E370 strb r3, [r4, #3] 95:Src/si5351.c **** regs[4] = msnx_p1 & 0xFF; 498 .loc 1 95 5 is_stmt 1 view .LVU141 499 .loc 1 95 13 is_stmt 0 view .LVU142 500 0150 2671 strb r6, [r4, #4] 96:Src/si5351.c **** regs[5] = ((msnx_p3 >> 12) & 0xF0) + ((msnx_p2 >> 16) & 0x0F); 501 .loc 1 96 5 is_stmt 1 view .LVU143 502 .loc 1 96 25 is_stmt 0 view .LVU144 503 0152 000B lsrs r0, r0, #12 504 .LVL58: 505 .loc 1 96 32 view .LVU145 506 0154 00F0F000 and r0, r0, #240 507 .loc 1 96 59 view .LVU146 508 0158 CBF30343 ubfx r3, fp, #16, #4 509 .loc 1 96 40 view .LVU147 510 015c 1843 orrs r0, r0, r3 511 .loc 1 96 13 view .LVU148 512 015e 6071 strb r0, [r4, #5] 97:Src/si5351.c **** regs[6] = (msnx_p2 >> 8) & 0xFF; 513 .loc 1 97 5 is_stmt 1 view .LVU149 514 .loc 1 97 24 is_stmt 0 view .LVU150 515 0160 4FEA1B23 lsr r3, fp, #8 516 .loc 1 97 13 view .LVU151 517 0164 A371 strb r3, [r4, #6] 98:Src/si5351.c **** regs[7] = msnx_p2 & 0xFF; 518 .loc 1 98 5 is_stmt 1 view .LVU152 519 .loc 1 98 13 is_stmt 0 view .LVU153 520 0166 84F807B0 strb fp, [r4, #7] 99:Src/si5351.c **** 100:Src/si5351.c **** // Output Multisynth Divider registers 101:Src/si5351.c **** regs[8] = 0; // (msx_p3 >> 8) & 0xFF 521 .loc 1 101 5 is_stmt 1 view .LVU154 522 .loc 1 101 13 is_stmt 0 view .LVU155 523 016a 0023 movs r3, #0 524 016c 2372 strb r3, [r4, #8] 102:Src/si5351.c **** regs[9] = 1; // msx_p3 & 0xFF 525 .loc 1 102 5 is_stmt 1 view .LVU156 526 .loc 1 102 13 is_stmt 0 view .LVU157 527 016e 0122 movs r2, #1 528 0170 6272 strb r2, [r4, #9] 103:Src/si5351.c **** regs[10] = rx_div + msx_divby4 + ((msx_p1 >> 16) & 0x03); 529 .loc 1 103 5 is_stmt 1 view .LVU158 530 .loc 1 103 23 is_stmt 0 view .LVU159 531 0172 5544 add r5, r5, r10 532 .LVL59: 533 .loc 1 103 23 view .LVU160 534 0174 EDB2 uxtb r5, r5 535 .loc 1 103 54 view .LVU161 536 0176 C7F30142 ubfx r2, r7, #16, #2 537 .loc 1 103 36 view .LVU162 538 017a 1544 add r5, r5, r2 539 .loc 1 103 14 view .LVU163 540 017c A572 strb r5, [r4, #10] 104:Src/si5351.c **** regs[11] = (msx_p1 >> 8) & 0xFF; 541 .loc 1 104 5 is_stmt 1 view .LVU164 542 .loc 1 104 24 is_stmt 0 view .LVU165 543 017e 3A0A lsrs r2, r7, #8 ARM GAS /tmp/ccx0f9ME.s page 13 544 .loc 1 104 14 view .LVU166 545 0180 E272 strb r2, [r4, #11] 105:Src/si5351.c **** regs[12] = msx_p1 & 0xFF; 546 .loc 1 105 5 is_stmt 1 view .LVU167 547 .loc 1 105 14 is_stmt 0 view .LVU168 548 0182 2773 strb r7, [r4, #12] 106:Src/si5351.c **** regs[13] = 0; // ((msx_p3 >> 12) & 0xF0) + (msx_p2 >> 16) & 0x0 549 .loc 1 106 5 is_stmt 1 view .LVU169 550 .loc 1 106 14 is_stmt 0 view .LVU170 551 0184 6373 strb r3, [r4, #13] 107:Src/si5351.c **** regs[14] = 0; // (msx_p2 >> 8) & 0xFF 552 .loc 1 107 5 is_stmt 1 view .LVU171 553 .loc 1 107 14 is_stmt 0 view .LVU172 554 0186 A373 strb r3, [r4, #14] 108:Src/si5351.c **** regs[15] = 0; // msx_p2 & 0xFF 555 .loc 1 108 5 is_stmt 1 view .LVU173 556 .loc 1 108 14 is_stmt 0 view .LVU174 557 0188 E373 strb r3, [r4, #15] 109:Src/si5351.c **** 110:Src/si5351.c **** // HAL_I2C_Master_Transmit(&hi2c2, Si5351_ConfigStruct->HW_I2C_Address, reg_data, sizeof(reg_data), 111:Src/si5351.c **** return; 558 .loc 1 111 5 is_stmt 1 view .LVU175 112:Src/si5351.c **** } 559 .loc 1 112 1 is_stmt 0 view .LVU176 560 018a BDE8F88F pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc} 561 .LVL60: 562 .L30: 563 .loc 1 112 1 view .LVU177 564 018e 00BF .align 3 565 .L29: 566 0190 00000000 .word 0 567 0194 A3E1C141 .word 1103225251 568 0198 00000000 .word 0 569 019c 60E37641 .word 1098310496 570 01a0 00000000 .word 0 571 01a4 FEFF2F41 .word 1093664766 572 01a8 80D1F008 .word 150000000 573 01ac 68780400 .word 292968 574 01b0 FF45C323 .word 599999999 575 01b4 0000E03F .word 1071644672 576 01b8 FFFF0F00 .word 1048575 577 .cfi_endproc 578 .LFE331: 580 .section .text.si5351_initialize,"ax",%progbits 581 .align 1 582 .global si5351_initialize 583 .syntax unified 584 .thumb 585 .thumb_func 587 si5351_initialize: 588 .LFB332: 113:Src/si5351.c **** 114:Src/si5351.c **** void si5351_initialize(){ 589 .loc 1 114 25 is_stmt 1 view -0 590 .cfi_startproc 591 @ args = 0, pretend = 0, frame = 0 592 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccx0f9ME.s page 14 593 0000 10B5 push {r4, lr} 594 .LCFI7: 595 .cfi_def_cfa_offset 8 596 .cfi_offset 4, -8 597 .cfi_offset 14, -4 598 0002 0024 movs r4, #0 115:Src/si5351.c **** uint8_t dummy; 599 .loc 1 115 2 view .LVU179 116:Src/si5351.c **** // Initialize Si5351A 117:Src/si5351.c **** while (si5351_read8(0,dummy) & 0x80); // Wait for Si5351A to initialize 600 .loc 1 117 2 view .LVU180 601 .L32: 602 .loc 1 117 9 discriminator 1 view .LVU181 603 0004 2146 mov r1, r4 604 0006 0020 movs r0, #0 605 0008 FFF7FEFF bl si5351_read8 606 .LVL61: 607 000c 10F0800F tst r0, #128 608 0010 F8D1 bne .L32 118:Src/si5351.c **** oeb = 0xFF; 609 .loc 1 118 2 view .LVU182 610 .loc 1 118 6 is_stmt 0 view .LVU183 611 0012 FF21 movs r1, #255 612 0014 2C4B ldr r3, .L34 613 0016 1970 strb r1, [r3] 119:Src/si5351.c **** 120:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb); // Output Enable Control, disable all 614 .loc 1 120 5 is_stmt 1 view .LVU184 615 0018 0320 movs r0, #3 616 001a FFF7FEFF bl si5351_write8 617 .LVL62: 121:Src/si5351.c **** 122:Src/si5351.c **** si5351_write8(SI5351_INPUT_SOURCE, 0x00); // PLL Input Source, select the XTAL input 618 .loc 1 122 5 view .LVU185 619 001e 0021 movs r1, #0 620 0020 0F20 movs r0, #15 621 0022 FFF7FEFF bl si5351_write8 622 .LVL63: 123:Src/si5351.c **** si5351_write8(SI5351_OUT_DIS_STATE, 0x00); // stato bassa Z giu se disabilitati 623 .loc 1 123 5 view .LVU186 624 0026 0021 movs r1, #0 625 0028 1820 movs r0, #24 626 002a FFF7FEFF bl si5351_write8 627 .LVL64: 124:Src/si5351.c **** 125:Src/si5351.c **** // Output MultisynthN, e = 0, f = 1, MS0_P2 and MSO_P3 126:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0, 0x00); 628 .loc 1 126 5 view .LVU187 629 002e 0021 movs r1, #0 630 0030 2A20 movs r0, #42 631 0032 FFF7FEFF bl si5351_write8 632 .LVL65: 127:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+1, 0x01); 633 .loc 1 127 5 view .LVU188 634 0036 0121 movs r1, #1 635 0038 2B20 movs r0, #43 636 003a FFF7FEFF bl si5351_write8 ARM GAS /tmp/ccx0f9ME.s page 15 637 .LVL66: 128:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+5, 0x00); 638 .loc 1 128 5 view .LVU189 639 003e 0021 movs r1, #0 640 0040 2F20 movs r0, #47 641 0042 FFF7FEFF bl si5351_write8 642 .LVL67: 129:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+6, 0x00); 643 .loc 1 129 5 view .LVU190 644 0046 0021 movs r1, #0 645 0048 3020 movs r0, #48 646 004a FFF7FEFF bl si5351_write8 647 .LVL68: 130:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+7, 0x00); 648 .loc 1 130 5 view .LVU191 649 004e 0021 movs r1, #0 650 0050 3120 movs r0, #49 651 0052 FFF7FEFF bl si5351_write8 652 .LVL69: 131:Src/si5351.c **** 132:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1, 0x00); 653 .loc 1 132 5 view .LVU192 654 0056 0021 movs r1, #0 655 0058 3220 movs r0, #50 656 005a FFF7FEFF bl si5351_write8 657 .LVL70: 133:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+1, 0x01); 658 .loc 1 133 5 view .LVU193 659 005e 0121 movs r1, #1 660 0060 3320 movs r0, #51 661 0062 FFF7FEFF bl si5351_write8 662 .LVL71: 134:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+5, 0x00); 663 .loc 1 134 5 view .LVU194 664 0066 0021 movs r1, #0 665 0068 3720 movs r0, #55 666 006a FFF7FEFF bl si5351_write8 667 .LVL72: 135:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+6, 0x00); 668 .loc 1 135 5 view .LVU195 669 006e 0021 movs r1, #0 670 0070 3820 movs r0, #56 671 0072 FFF7FEFF bl si5351_write8 672 .LVL73: 136:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+7, 0x00); 673 .loc 1 136 5 view .LVU196 674 0076 0021 movs r1, #0 675 0078 3920 movs r0, #57 676 007a FFF7FEFF bl si5351_write8 677 .LVL74: 137:Src/si5351.c **** 138:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2, 0x00); 678 .loc 1 138 5 view .LVU197 679 007e 0021 movs r1, #0 680 0080 3A20 movs r0, #58 681 0082 FFF7FEFF bl si5351_write8 682 .LVL75: ARM GAS /tmp/ccx0f9ME.s page 16 139:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+1, 0x01); 683 .loc 1 139 5 view .LVU198 684 0086 0121 movs r1, #1 685 0088 3B20 movs r0, #59 686 008a FFF7FEFF bl si5351_write8 687 .LVL76: 140:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+5, 0x00); 688 .loc 1 140 5 view .LVU199 689 008e 0021 movs r1, #0 690 0090 3F20 movs r0, #63 691 0092 FFF7FEFF bl si5351_write8 692 .LVL77: 141:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+6, 0x00); 693 .loc 1 141 5 view .LVU200 694 0096 0021 movs r1, #0 695 0098 4020 movs r0, #64 696 009a FFF7FEFF bl si5351_write8 697 .LVL78: 142:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+7, 0x00); 698 .loc 1 142 5 view .LVU201 699 009e 0021 movs r1, #0 700 00a0 4120 movs r0, #65 701 00a2 FFF7FEFF bl si5351_write8 702 .LVL79: 143:Src/si5351.c **** 144:Src/si5351.c **** si5351_write8(SI5351_CLK0_CONTROL, 0x4F); // Power up CLK0, PLLA, MS0 operates in integer mod 703 .loc 1 144 5 view .LVU202 704 00a6 4F21 movs r1, #79 705 00a8 1020 movs r0, #16 706 00aa FFF7FEFF bl si5351_write8 707 .LVL80: 145:Src/si5351.c **** si5351_write8(SI5351_CLK1_CONTROL, 0x5F); // Power up CLK1, PLLA, MS0 operates in integer mod 708 .loc 1 145 5 view .LVU203 709 00ae 5F21 movs r1, #95 710 00b0 1120 movs r0, #17 711 00b2 FFF7FEFF bl si5351_write8 712 .LVL81: 146:Src/si5351.c **** si5351_write8(SI5351_CLK2_CONTROL, 0x6F); // Power up CLK2, PLLB, int, non inv, multisynth 2, 713 .loc 1 146 5 view .LVU204 714 00b6 6F21 movs r1, #111 715 00b8 1220 movs r0, #18 716 00ba FFF7FEFF bl si5351_write8 717 .LVL82: 147:Src/si5351.c **** 148:Src/si5351.c **** // Reference load configuration 149:Src/si5351.c **** si5351_write8(SI5351_CRYSTAL_LOAD, 0x12); // Set reference load C: 6 pF = 0x12, 8 pF = 718 .loc 1 149 5 view .LVU205 719 00be 1221 movs r1, #18 720 00c0 B720 movs r0, #183 721 00c2 FFF7FEFF bl si5351_write8 722 .LVL83: 150:Src/si5351.c **** } 723 .loc 1 150 1 is_stmt 0 view .LVU206 724 00c6 10BD pop {r4, pc} 725 .L35: 726 .align 2 727 .L34: ARM GAS /tmp/ccx0f9ME.s page 17 728 00c8 00000000 .word oeb 729 .cfi_endproc 730 .LFE332: 732 .section .text.si5351_set_frequency,"ax",%progbits 733 .align 1 734 .global si5351_set_frequency 735 .syntax unified 736 .thumb 737 .thumb_func 739 si5351_set_frequency: 740 .LVL84: 741 .LFB333: 151:Src/si5351.c **** 152:Src/si5351.c **** void si5351_set_frequency(uint32_t freq, uint8_t pll){ 742 .loc 1 152 54 is_stmt 1 view -0 743 .cfi_startproc 744 @ args = 0, pretend = 0, frame = 16 745 @ frame_needed = 0, uses_anonymous_args = 0 746 .loc 1 152 54 is_stmt 0 view .LVU208 747 0000 10B5 push {r4, lr} 748 .LCFI8: 749 .cfi_def_cfa_offset 8 750 .cfi_offset 4, -8 751 .cfi_offset 14, -4 752 0002 84B0 sub sp, sp, #16 753 .LCFI9: 754 .cfi_def_cfa_offset 24 755 0004 0C46 mov r4, r1 153:Src/si5351.c **** uint8_t regs[16]; 756 .loc 1 153 2 is_stmt 1 view .LVU209 154:Src/si5351.c **** CalcRegisters(freq, regs); 757 .loc 1 154 2 view .LVU210 758 0006 6946 mov r1, sp 759 .LVL85: 760 .loc 1 154 2 is_stmt 0 view .LVU211 761 0008 FFF7FEFF bl CalcRegisters 762 .LVL86: 155:Src/si5351.c **** 156:Src/si5351.c **** // Load Output Multisynth0 with d (e and f already set during init. and never changed) 157:Src/si5351.c **** if(pll == 0){ 763 .loc 1 157 2 is_stmt 1 view .LVU212 764 .loc 1 157 4 is_stmt 0 view .LVU213 765 000c 94B1 cbz r4, .L47 158:Src/si5351.c **** for (int i = 0; i < 8; i++) 159:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]); 160:Src/si5351.c **** for (int i = 10; i < 13; i++) 161:Src/si5351.c **** si5351_write8(34 + i, regs[i]); 162:Src/si5351.c **** } else if(pll == 1){ 766 .loc 1 162 9 is_stmt 1 view .LVU214 767 .loc 1 162 11 is_stmt 0 view .LVU215 768 000e 012C cmp r4, #1 769 0010 1FD1 bne .L42 770 .LBB4: 163:Src/si5351.c **** for (int i = 0; i < 8; i++) 771 .loc 1 163 12 view .LVU216 772 0012 0024 movs r4, #0 773 0014 2EE0 b .L43 ARM GAS /tmp/ccx0f9ME.s page 18 774 .LVL87: 775 .L39: 776 .loc 1 163 12 view .LVU217 777 .LBE4: 778 .LBB5: 159:Src/si5351.c **** for (int i = 10; i < 13; i++) 779 .loc 1 159 4 is_stmt 1 discriminator 3 view .LVU218 780 0016 04F11003 add r3, r4, #16 781 001a 6B44 add r3, sp, r3 782 001c 04F11A00 add r0, r4, #26 783 0020 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2 784 0024 C0B2 uxtb r0, r0 785 0026 FFF7FEFF bl si5351_write8 786 .LVL88: 158:Src/si5351.c **** for (int i = 0; i < 8; i++) 787 .loc 1 158 27 discriminator 3 view .LVU219 788 002a 0134 adds r4, r4, #1 789 .LVL89: 790 .L37: 158:Src/si5351.c **** for (int i = 0; i < 8; i++) 791 .loc 1 158 21 discriminator 1 view .LVU220 792 002c 072C cmp r4, #7 793 002e F2DD ble .L39 794 .LBE5: 795 .LBB6: 160:Src/si5351.c **** si5351_write8(34 + i, regs[i]); 796 .loc 1 160 12 is_stmt 0 view .LVU221 797 0030 0A24 movs r4, #10 798 .LVL90: 160:Src/si5351.c **** si5351_write8(34 + i, regs[i]); 799 .loc 1 160 12 view .LVU222 800 0032 0CE0 b .L40 801 .LVL91: 802 .L47: 160:Src/si5351.c **** si5351_write8(34 + i, regs[i]); 803 .loc 1 160 12 view .LVU223 804 .LBE6: 805 .LBB7: 158:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]); 806 .loc 1 158 12 view .LVU224 807 0034 0024 movs r4, #0 808 0036 F9E7 b .L37 809 .LVL92: 810 .L41: 158:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]); 811 .loc 1 158 12 view .LVU225 812 .LBE7: 813 .LBB8: 161:Src/si5351.c **** } else if(pll == 1){ 814 .loc 1 161 11 is_stmt 1 discriminator 3 view .LVU226 815 0038 04F11003 add r3, r4, #16 816 003c 6B44 add r3, sp, r3 817 003e 04F12200 add r0, r4, #34 818 0042 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2 819 0046 C0B2 uxtb r0, r0 820 0048 FFF7FEFF bl si5351_write8 821 .LVL93: ARM GAS /tmp/ccx0f9ME.s page 19 160:Src/si5351.c **** si5351_write8(34 + i, regs[i]); 822 .loc 1 160 29 discriminator 3 view .LVU227 823 004c 0134 adds r4, r4, #1 824 .LVL94: 825 .L40: 160:Src/si5351.c **** si5351_write8(34 + i, regs[i]); 826 .loc 1 160 22 discriminator 1 view .LVU228 827 004e 0C2C cmp r4, #12 828 0050 F2DD ble .L41 829 .LVL95: 830 .L42: 160:Src/si5351.c **** si5351_write8(34 + i, regs[i]); 831 .loc 1 160 22 is_stmt 0 discriminator 1 view .LVU229 832 .LBE8: 164:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]); 165:Src/si5351.c **** for (int i = 10; i < 13; i++) 166:Src/si5351.c **** si5351_write8(42 + i, regs[i]); 167:Src/si5351.c **** } 168:Src/si5351.c **** 169:Src/si5351.c **** // Reset PLLA 170:Src/si5351.c **** // delayMicroseconds(500); // Allow registers to settle before resetting the PLL 171:Src/si5351.c **** si5351_write8(SI5351_RESET, 0x20); 833 .loc 1 171 5 is_stmt 1 view .LVU230 834 0052 2021 movs r1, #32 835 0054 B120 movs r0, #177 836 0056 FFF7FEFF bl si5351_write8 837 .LVL96: 172:Src/si5351.c **** } 838 .loc 1 172 1 is_stmt 0 view .LVU231 839 005a 04B0 add sp, sp, #16 840 .LCFI10: 841 .cfi_remember_state 842 .cfi_def_cfa_offset 8 843 @ sp needed 844 005c 10BD pop {r4, pc} 845 .LVL97: 846 .L44: 847 .LCFI11: 848 .cfi_restore_state 849 .LBB9: 164:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]); 850 .loc 1 164 4 is_stmt 1 discriminator 3 view .LVU232 851 005e 04F11003 add r3, r4, #16 852 0062 6B44 add r3, sp, r3 853 0064 04F12200 add r0, r4, #34 854 0068 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2 855 006c C0B2 uxtb r0, r0 856 006e FFF7FEFF bl si5351_write8 857 .LVL98: 163:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]); 858 .loc 1 163 27 discriminator 3 view .LVU233 859 0072 0134 adds r4, r4, #1 860 .LVL99: 861 .L43: 163:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]); 862 .loc 1 163 21 discriminator 1 view .LVU234 863 0074 072C cmp r4, #7 ARM GAS /tmp/ccx0f9ME.s page 20 864 0076 F2DD ble .L44 865 .LBE9: 866 .LBB10: 165:Src/si5351.c **** si5351_write8(42 + i, regs[i]); 867 .loc 1 165 12 is_stmt 0 view .LVU235 868 0078 0A24 movs r4, #10 869 .LVL100: 165:Src/si5351.c **** si5351_write8(42 + i, regs[i]); 870 .loc 1 165 12 view .LVU236 871 007a 0AE0 b .L45 872 .LVL101: 873 .L46: 166:Src/si5351.c **** } 874 .loc 1 166 11 is_stmt 1 discriminator 3 view .LVU237 875 007c 04F11003 add r3, r4, #16 876 0080 6B44 add r3, sp, r3 877 0082 04F12A00 add r0, r4, #42 878 0086 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2 879 008a C0B2 uxtb r0, r0 880 008c FFF7FEFF bl si5351_write8 881 .LVL102: 165:Src/si5351.c **** si5351_write8(42 + i, regs[i]); 882 .loc 1 165 29 discriminator 3 view .LVU238 883 0090 0134 adds r4, r4, #1 884 .LVL103: 885 .L45: 165:Src/si5351.c **** si5351_write8(42 + i, regs[i]); 886 .loc 1 165 22 discriminator 1 view .LVU239 887 0092 0C2C cmp r4, #12 888 0094 F2DD ble .L46 889 0096 DCE7 b .L42 890 .LBE10: 891 .cfi_endproc 892 .LFE333: 894 .section .text.si5351_off_clk,"ax",%progbits 895 .align 1 896 .global si5351_off_clk 897 .syntax unified 898 .thumb 899 .thumb_func 901 si5351_off_clk: 902 .LVL104: 903 .LFB334: 173:Src/si5351.c **** 174:Src/si5351.c **** void si5351_off_clk(uint8_t clk){ 904 .loc 1 174 33 view -0 905 .cfi_startproc 906 @ args = 0, pretend = 0, frame = 0 907 @ frame_needed = 0, uses_anonymous_args = 0 908 .loc 1 174 33 is_stmt 0 view .LVU241 909 0000 08B5 push {r3, lr} 910 .LCFI12: 911 .cfi_def_cfa_offset 8 912 .cfi_offset 3, -8 913 .cfi_offset 14, -4 175:Src/si5351.c **** oeb |= 1U << clk; 914 .loc 1 175 2 is_stmt 1 view .LVU242 ARM GAS /tmp/ccx0f9ME.s page 21 915 .loc 1 175 12 is_stmt 0 view .LVU243 916 0002 0123 movs r3, #1 917 0004 8340 lsls r3, r3, r0 918 .loc 1 175 6 view .LVU244 919 0006 044A ldr r2, .L53 920 0008 1178 ldrb r1, [r2] @ zero_extendqisi2 921 000a 1943 orrs r1, r1, r3 922 000c C9B2 uxtb r1, r1 923 000e 1170 strb r1, [r2] 176:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb); 924 .loc 1 176 2 is_stmt 1 view .LVU245 925 0010 0320 movs r0, #3 926 .LVL105: 927 .loc 1 176 2 is_stmt 0 view .LVU246 928 0012 FFF7FEFF bl si5351_write8 929 .LVL106: 177:Src/si5351.c **** } 930 .loc 1 177 1 view .LVU247 931 0016 08BD pop {r3, pc} 932 .L54: 933 .align 2 934 .L53: 935 0018 00000000 .word oeb 936 .cfi_endproc 937 .LFE334: 939 .section .text.si5351_on_clk,"ax",%progbits 940 .align 1 941 .global si5351_on_clk 942 .syntax unified 943 .thumb 944 .thumb_func 946 si5351_on_clk: 947 .LVL107: 948 .LFB335: 178:Src/si5351.c **** 179:Src/si5351.c **** void si5351_on_clk(uint8_t clk){ 949 .loc 1 179 32 is_stmt 1 view -0 950 .cfi_startproc 951 @ args = 0, pretend = 0, frame = 0 952 @ frame_needed = 0, uses_anonymous_args = 0 953 .loc 1 179 32 is_stmt 0 view .LVU249 954 0000 08B5 push {r3, lr} 955 .LCFI13: 956 .cfi_def_cfa_offset 8 957 .cfi_offset 3, -8 958 .cfi_offset 14, -4 180:Src/si5351.c **** oeb &= ~(1U << clk); 959 .loc 1 180 2 is_stmt 1 view .LVU250 960 .loc 1 180 14 is_stmt 0 view .LVU251 961 0002 0123 movs r3, #1 962 0004 8340 lsls r3, r3, r0 963 .loc 1 180 6 view .LVU252 964 0006 044A ldr r2, .L57 965 0008 1178 ldrb r1, [r2] @ zero_extendqisi2 966 000a 21EA0301 bic r1, r1, r3 967 000e 1170 strb r1, [r2] 181:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb); ARM GAS /tmp/ccx0f9ME.s page 22 968 .loc 1 181 2 is_stmt 1 view .LVU253 969 0010 0320 movs r0, #3 970 .LVL108: 971 .loc 1 181 2 is_stmt 0 view .LVU254 972 0012 FFF7FEFF bl si5351_write8 973 .LVL109: 182:Src/si5351.c **** } 974 .loc 1 182 1 view .LVU255 975 0016 08BD pop {r3, pc} 976 .L58: 977 .align 2 978 .L57: 979 0018 00000000 .word oeb 980 .cfi_endproc 981 .LFE335: 983 .global oeb 984 .section .bss.oeb,"aw",%nobits 987 oeb: 988 0000 00 .space 1 989 .text 990 .Letext0: 991 .file 2 "/usr/lib/gcc/arm-none-eabi/12.2.1/include/stdint.h" 992 .file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h" 993 .file 4 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h" 994 .file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h" 995 .file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h" 996 .file 7 "Inc/si5351.h" ARM GAS /tmp/ccx0f9ME.s page 23 DEFINED SYMBOLS *ABS*:00000000 si5351.c /tmp/ccx0f9ME.s:21 .text.si5351_write8:00000000 $t /tmp/ccx0f9ME.s:27 .text.si5351_write8:00000000 si5351_write8 /tmp/ccx0f9ME.s:81 .text.si5351_write8:00000038 $d /tmp/ccx0f9ME.s:86 .text.si5351_read8:00000000 $t /tmp/ccx0f9ME.s:92 .text.si5351_read8:00000000 si5351_read8 /tmp/ccx0f9ME.s:149 .text.si5351_read8:00000034 $d /tmp/ccx0f9ME.s:162 .text.CalcRegisters:00000000 $t /tmp/ccx0f9ME.s:168 .text.CalcRegisters:00000000 CalcRegisters /tmp/ccx0f9ME.s:566 .text.CalcRegisters:00000190 $d /tmp/ccx0f9ME.s:581 .text.si5351_initialize:00000000 $t /tmp/ccx0f9ME.s:587 .text.si5351_initialize:00000000 si5351_initialize /tmp/ccx0f9ME.s:728 .text.si5351_initialize:000000c8 $d /tmp/ccx0f9ME.s:987 .bss.oeb:00000000 oeb /tmp/ccx0f9ME.s:733 .text.si5351_set_frequency:00000000 $t /tmp/ccx0f9ME.s:739 .text.si5351_set_frequency:00000000 si5351_set_frequency /tmp/ccx0f9ME.s:895 .text.si5351_off_clk:00000000 $t /tmp/ccx0f9ME.s:901 .text.si5351_off_clk:00000000 si5351_off_clk /tmp/ccx0f9ME.s:935 .text.si5351_off_clk:00000018 $d /tmp/ccx0f9ME.s:940 .text.si5351_on_clk:00000000 $t /tmp/ccx0f9ME.s:946 .text.si5351_on_clk:00000000 si5351_on_clk /tmp/ccx0f9ME.s:979 .text.si5351_on_clk:00000018 $d /tmp/ccx0f9ME.s:988 .bss.oeb:00000000 $d UNDEFINED SYMBOLS HAL_I2C_IsDeviceReady HAL_I2C_Mem_Write hi2c1 HAL_I2C_Mem_Read __aeabi_ui2d __aeabi_ddiv __aeabi_d2uiz __aeabi_d2iz __aeabi_i2d __aeabi_dsub __aeabi_dmul __aeabi_dadd