1339 lines
55 KiB
Plaintext
1339 lines
55 KiB
Plaintext
ARM GAS /tmp/ccY965Wh.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 1
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "si5351.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Src/si5351.c"
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20 .section .text.si5351_write8,"ax",%progbits
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21 .align 1
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22 .global si5351_write8
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23 .syntax unified
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24 .thumb
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25 .thumb_func
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27 si5351_write8:
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28 .LVL0:
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29 .LFB329:
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1:Src/si5351.c **** #include "main.h"
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2:Src/si5351.c **** #include "stm32g4xx_hal.h"
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3:Src/si5351.c **** #include <math.h>
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4:Src/si5351.c **** #include "si5351.h"
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5:Src/si5351.c ****
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6:Src/si5351.c **** uint8_t oeb;
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7:Src/si5351.c ****
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8:Src/si5351.c **** void si5351_write8 (uint8_t reg, uint8_t value){
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30 .loc 1 8 48 view -0
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31 .cfi_startproc
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32 @ args = 0, pretend = 0, frame = 8
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33 @ frame_needed = 0, uses_anonymous_args = 0
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34 .loc 1 8 48 is_stmt 0 view .LVU1
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35 0000 10B5 push {r4, lr}
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36 .LCFI0:
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37 .cfi_def_cfa_offset 8
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38 .cfi_offset 4, -8
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39 .cfi_offset 14, -4
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40 0002 86B0 sub sp, sp, #24
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41 .LCFI1:
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42 .cfi_def_cfa_offset 32
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43 0004 0446 mov r4, r0
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44 0006 8DF81710 strb r1, [sp, #23]
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9:Src/si5351.c **** while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { }
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45 .loc 1 9 2 is_stmt 1 view .LVU2
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46 .LVL1:
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47 .L2:
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48 .loc 1 9 91 discriminator 1 view .LVU3
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49 .loc 1 9 78 discriminator 1 view .LVU4
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ARM GAS /tmp/ccY965Wh.s page 2
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50 .loc 1 9 9 is_stmt 0 discriminator 1 view .LVU5
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51 000a 6423 movs r3, #100
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52 000c 0322 movs r2, #3
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53 000e C021 movs r1, #192
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54 0010 0948 ldr r0, .L4
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55 0012 FFF7FEFF bl HAL_I2C_IsDeviceReady
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56 .LVL2:
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57 .loc 1 9 78 discriminator 1 view .LVU6
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58 0016 0028 cmp r0, #0
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59 0018 F7D1 bne .L2
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10:Src/si5351.c **** HAL_I2C_Mem_Write(&hi2c1, (uint8_t)(SI5351_ADDRESS<<1), (uint8_t)reg, I2C_MEMADD_SIZE_8BIT, (uint8
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60 .loc 1 10 2 is_stmt 1 view .LVU7
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61 001a 6423 movs r3, #100
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62 001c 0293 str r3, [sp, #8]
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63 001e 0123 movs r3, #1
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64 0020 0193 str r3, [sp, #4]
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65 0022 0DF11702 add r2, sp, #23
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66 0026 0092 str r2, [sp]
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67 0028 2246 mov r2, r4
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68 002a C021 movs r1, #192
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69 002c 0248 ldr r0, .L4
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70 002e FFF7FEFF bl HAL_I2C_Mem_Write
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71 .LVL3:
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11:Src/si5351.c **** }
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72 .loc 1 11 1 is_stmt 0 view .LVU8
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73 0032 06B0 add sp, sp, #24
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74 .LCFI2:
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75 .cfi_def_cfa_offset 8
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76 @ sp needed
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77 0034 10BD pop {r4, pc}
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78 .LVL4:
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79 .L5:
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80 .loc 1 11 1 view .LVU9
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81 0036 00BF .align 2
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82 .L4:
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83 0038 00000000 .word hi2c1
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84 .cfi_endproc
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85 .LFE329:
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87 .section .text.si5351_read8,"ax",%progbits
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88 .align 1
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89 .global si5351_read8
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90 .syntax unified
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91 .thumb
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92 .thumb_func
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94 si5351_read8:
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95 .LVL5:
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96 .LFB330:
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12:Src/si5351.c ****
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13:Src/si5351.c **** uint8_t si5351_read8(uint8_t reg, uint8_t *value){
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97 .loc 1 13 50 is_stmt 1 view -0
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98 .cfi_startproc
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99 @ args = 0, pretend = 0, frame = 8
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100 @ frame_needed = 0, uses_anonymous_args = 0
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101 .loc 1 13 50 is_stmt 0 view .LVU11
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102 0000 10B5 push {r4, lr}
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103 .LCFI3:
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104 .cfi_def_cfa_offset 8
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ARM GAS /tmp/ccY965Wh.s page 3
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105 .cfi_offset 4, -8
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106 .cfi_offset 14, -4
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107 0002 86B0 sub sp, sp, #24
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108 .LCFI4:
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109 .cfi_def_cfa_offset 32
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110 0004 0446 mov r4, r0
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111 0006 0591 str r1, [sp, #20]
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14:Src/si5351.c **** HAL_StatusTypeDef status = HAL_OK;
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112 .loc 1 14 2 is_stmt 1 view .LVU12
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113 .LVL6:
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15:Src/si5351.c **** while (HAL_I2C_IsDeviceReady(&hi2c1, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { }
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114 .loc 1 15 2 view .LVU13
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115 .L7:
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116 .loc 1 15 91 discriminator 1 view .LVU14
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117 .loc 1 15 78 discriminator 1 view .LVU15
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118 .loc 1 15 9 is_stmt 0 discriminator 1 view .LVU16
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119 0008 6423 movs r3, #100
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120 000a 0322 movs r2, #3
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121 000c C021 movs r1, #192
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122 000e 0948 ldr r0, .L9
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123 0010 FFF7FEFF bl HAL_I2C_IsDeviceReady
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124 .LVL7:
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125 .loc 1 15 78 discriminator 1 view .LVU17
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126 0014 0028 cmp r0, #0
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127 0016 F7D1 bne .L7
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16:Src/si5351.c **** status = HAL_I2C_Mem_Read(&hi2c1, // i2c handle
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128 .loc 1 16 2 is_stmt 1 view .LVU18
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129 .loc 1 16 11 is_stmt 0 view .LVU19
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130 0018 6423 movs r3, #100
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131 001a 0293 str r3, [sp, #8]
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132 001c 0123 movs r3, #1
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133 001e 0193 str r3, [sp, #4]
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134 0020 05AA add r2, sp, #20
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135 0022 0092 str r2, [sp]
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136 0024 2246 mov r2, r4
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137 0026 C021 movs r1, #192
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138 0028 0248 ldr r0, .L9
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139 002a FFF7FEFF bl HAL_I2C_Mem_Read
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140 .LVL8:
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17:Src/si5351.c **** (uint8_t)(SI5351_ADDRESS<<1), // i2c address, left aligned
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18:Src/si5351.c **** (uint8_t)reg, // register address
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19:Src/si5351.c **** I2C_MEMADD_SIZE_8BIT, // si5351 uses 8bit register addresses
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20:Src/si5351.c **** (uint8_t*)(&value), // write returned data to this variable
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21:Src/si5351.c **** 1, // how many bytes to expect returned
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22:Src/si5351.c **** 100); // timeout
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23:Src/si5351.c ****
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24:Src/si5351.c **** return status;
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141 .loc 1 24 3 is_stmt 1 view .LVU20
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25:Src/si5351.c **** }
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142 .loc 1 25 1 is_stmt 0 view .LVU21
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143 002e 06B0 add sp, sp, #24
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144 .LCFI5:
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145 .cfi_def_cfa_offset 8
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146 @ sp needed
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147 0030 10BD pop {r4, pc}
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148 .LVL9:
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149 .L10:
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ARM GAS /tmp/ccY965Wh.s page 4
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150 .loc 1 25 1 view .LVU22
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151 0032 00BF .align 2
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152 .L9:
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153 0034 00000000 .word hi2c1
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154 .cfi_endproc
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155 .LFE330:
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157 .global __aeabi_ui2d
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158 .global __aeabi_ddiv
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159 .global __aeabi_d2uiz
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160 .global __aeabi_d2iz
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161 .global __aeabi_i2d
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162 .global __aeabi_dsub
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163 .global __aeabi_dmul
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164 .global __aeabi_dadd
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165 .section .text.CalcRegisters,"ax",%progbits
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166 .align 1
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167 .global CalcRegisters
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168 .syntax unified
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169 .thumb
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170 .thumb_func
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172 CalcRegisters:
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173 .LVL10:
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174 .LFB331:
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26:Src/si5351.c ****
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27:Src/si5351.c ****
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28:Src/si5351.c **** void CalcRegisters(uint32_t fout, uint8_t *regs){
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175 .loc 1 28 49 is_stmt 1 view -0
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176 .cfi_startproc
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177 @ args = 0, pretend = 0, frame = 0
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178 @ frame_needed = 0, uses_anonymous_args = 0
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179 .loc 1 28 49 is_stmt 0 view .LVU24
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180 0000 2DE9F84F push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
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181 .LCFI6:
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182 .cfi_def_cfa_offset 40
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183 .cfi_offset 3, -40
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184 .cfi_offset 4, -36
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185 .cfi_offset 5, -32
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186 .cfi_offset 6, -28
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187 .cfi_offset 7, -24
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188 .cfi_offset 8, -20
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189 .cfi_offset 9, -16
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190 .cfi_offset 10, -12
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191 .cfi_offset 11, -8
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192 .cfi_offset 14, -4
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193 0004 8046 mov r8, r0
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194 0006 0C46 mov r4, r1
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29:Src/si5351.c **** // uint32_t fref = SI5351_CRYSTAL_FREQ; // The reference frequency
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30:Src/si5351.c ****
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31:Src/si5351.c **** // Calc Output Multisynth Divider and R with e = 0 and f = 1 => msx_p2 = 0 and msx_p3 = 1
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32:Src/si5351.c **** uint32_t d = 4;
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195 .loc 1 32 5 is_stmt 1 view .LVU25
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196 .LVL11:
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33:Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY
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197 .loc 1 33 5 view .LVU26
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34:Src/si5351.c **** int msx_divby4 = 0;
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198 .loc 1 34 5 view .LVU27
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35:Src/si5351.c **** int rx_div = 0;
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ARM GAS /tmp/ccY965Wh.s page 5
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199 .loc 1 35 5 view .LVU28
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36:Src/si5351.c **** int r = 1;
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200 .loc 1 36 5 view .LVU29
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37:Src/si5351.c ****
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38:Src/si5351.c **** if (fout > 150e6)
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201 .loc 1 38 5 view .LVU30
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202 .loc 1 38 8 is_stmt 0 view .LVU31
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203 0008 674B ldr r3, .L29+24
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204 000a 9842 cmp r0, r3
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205 000c 49D8 bhi .L20
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39:Src/si5351.c **** msx_divby4 = 0x0C; // MSx_DIVBY4[1:0] = 0b11, see datasheet 4.1.3
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40:Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas
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206 .loc 1 40 10 is_stmt 1 view .LVU32
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207 .loc 1 40 13 is_stmt 0 view .LVU33
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208 000e 674B ldr r3, .L29+28
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209 0010 9842 cmp r0, r3
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210 0012 38D9 bls .L21
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41:Src/si5351.c **** {
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42:Src/si5351.c **** int rd = 0;
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43:Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL))
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44:Src/si5351.c **** {
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45:Src/si5351.c **** r <<= 1;
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46:Src/si5351.c **** rd++;
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47:Src/si5351.c **** }
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48:Src/si5351.c **** rx_div = rd << 4;
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49:Src/si5351.c ****
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50:Src/si5351.c **** d = 600e6 / (r * fout); // Use lowest VCO frequency but handle d minimum
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51:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
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52:Src/si5351.c **** d++;
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53:Src/si5351.c ****
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54:Src/si5351.c **** if (d * r * fout < 600e6) // VCO frequency to low check and maintain an even
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55:Src/si5351.c **** d += 2;
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56:Src/si5351.c **** }
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57:Src/si5351.c **** else // 292968 Hz <= fout <= 150 MHz
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58:Src/si5351.c **** {
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59:Src/si5351.c **** d = 600e6 / fout; // Use lowest VCO frequency but handle d minimum
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211 .loc 1 59 9 is_stmt 1 view .LVU34
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212 .loc 1 59 19 is_stmt 0 view .LVU35
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213 0014 FFF7FEFF bl __aeabi_ui2d
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214 .LVL12:
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215 .loc 1 59 19 view .LVU36
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216 0018 0246 mov r2, r0
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217 001a 0B46 mov r3, r1
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218 001c 5CA1 adr r1, .L29
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219 001e D1E90001 ldrd r0, [r1]
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220 0022 FFF7FEFF bl __aeabi_ddiv
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221 .LVL13:
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222 .loc 1 59 11 view .LVU37
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223 0026 FFF7FEFF bl __aeabi_d2uiz
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224 .LVL14:
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60:Src/si5351.c **** if (d < 6)
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225 .loc 1 60 9 is_stmt 1 view .LVU38
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226 .loc 1 60 12 is_stmt 0 view .LVU39
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227 002a 0528 cmp r0, #5
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228 002c 2ED9 bls .L23
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61:Src/si5351.c **** d = 6;
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62:Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d
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ARM GAS /tmp/ccY965Wh.s page 6
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229 .loc 1 62 14 is_stmt 1 view .LVU40
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230 .loc 1 62 17 is_stmt 0 view .LVU41
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231 002e 10F0010F tst r0, #1
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232 0032 2CD0 beq .L18
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63:Src/si5351.c **** d++;
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233 .loc 1 63 12 is_stmt 1 view .LVU42
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234 .loc 1 63 13 is_stmt 0 view .LVU43
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235 0034 0130 adds r0, r0, #1
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236 .LVL15:
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237 .loc 1 63 13 view .LVU44
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238 0036 2AE0 b .L18
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239 .LVL16:
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240 .L16:
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241 .LBB2:
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45:Src/si5351.c **** rd++;
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242 .loc 1 45 13 is_stmt 1 view .LVU45
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45:Src/si5351.c **** rd++;
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243 .loc 1 45 15 is_stmt 0 view .LVU46
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244 0038 7600 lsls r6, r6, #1
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245 .LVL17:
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46:Src/si5351.c **** }
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246 .loc 1 46 13 is_stmt 1 view .LVU47
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46:Src/si5351.c **** }
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247 .loc 1 46 15 is_stmt 0 view .LVU48
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248 003a 0135 adds r5, r5, #1
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249 .LVL18:
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250 .L13:
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43:Src/si5351.c **** {
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251 .loc 1 43 26 is_stmt 1 view .LVU49
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252 003c 7F2E cmp r6, #127
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253 003e 04DC bgt .L15
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43:Src/si5351.c **** {
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254 .loc 1 43 32 is_stmt 0 discriminator 1 view .LVU50
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255 0040 08FB06F2 mul r2, r8, r6
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43:Src/si5351.c **** {
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256 .loc 1 43 26 discriminator 1 view .LVU51
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257 0044 594B ldr r3, .L29+28
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258 0046 9A42 cmp r2, r3
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259 0048 F6D9 bls .L16
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260 .L15:
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48:Src/si5351.c ****
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261 .loc 1 48 9 is_stmt 1 view .LVU52
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48:Src/si5351.c ****
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262 .loc 1 48 16 is_stmt 0 view .LVU53
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263 004a 2D01 lsls r5, r5, #4
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264 .LVL19:
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50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
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265 .loc 1 50 9 is_stmt 1 view .LVU54
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50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
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266 .loc 1 50 24 is_stmt 0 view .LVU55
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267 004c 3746 mov r7, r6
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50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
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268 .loc 1 50 19 view .LVU56
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269 004e 08FB06F0 mul r0, r8, r6
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270 .LVL20:
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50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
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271 .loc 1 50 19 view .LVU57
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ARM GAS /tmp/ccY965Wh.s page 7
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272 0052 FFF7FEFF bl __aeabi_ui2d
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273 .LVL21:
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50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
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274 .loc 1 50 19 view .LVU58
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275 0056 0246 mov r2, r0
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276 0058 0B46 mov r3, r1
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277 005a 4DA1 adr r1, .L29
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278 005c D1E90001 ldrd r0, [r1]
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279 0060 FFF7FEFF bl __aeabi_ddiv
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280 .LVL22:
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50:Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/
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281 .loc 1 50 11 view .LVU59
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282 0064 FFF7FEFF bl __aeabi_d2uiz
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283 .LVL23:
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51:Src/si5351.c **** d++;
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284 .loc 1 51 9 is_stmt 1 view .LVU60
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51:Src/si5351.c **** d++;
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285 .loc 1 51 12 is_stmt 0 view .LVU61
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286 0068 10F0010F tst r0, #1
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287 006c 00D0 beq .L17
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52:Src/si5351.c ****
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288 .loc 1 52 13 is_stmt 1 view .LVU62
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52:Src/si5351.c ****
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289 .loc 1 52 14 is_stmt 0 view .LVU63
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290 006e 0130 adds r0, r0, #1
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291 .LVL24:
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292 .L17:
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54:Src/si5351.c **** d += 2;
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293 .loc 1 54 9 is_stmt 1 view .LVU64
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54:Src/si5351.c **** d += 2;
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294 .loc 1 54 15 is_stmt 0 view .LVU65
|
||
295 0070 00FB07F7 mul r7, r0, r7
|
||
54:Src/si5351.c **** d += 2;
|
||
296 .loc 1 54 19 view .LVU66
|
||
297 0074 08FB07F7 mul r7, r8, r7
|
||
54:Src/si5351.c **** d += 2;
|
||
298 .loc 1 54 12 view .LVU67
|
||
299 0078 4D4B ldr r3, .L29+32
|
||
300 007a 9F42 cmp r7, r3
|
||
301 007c 4ED8 bhi .L22
|
||
55:Src/si5351.c **** }
|
||
302 .loc 1 55 13 is_stmt 1 view .LVU68
|
||
55:Src/si5351.c **** }
|
||
303 .loc 1 55 15 is_stmt 0 view .LVU69
|
||
304 007e 0230 adds r0, r0, #2
|
||
305 .LVL25:
|
||
55:Src/si5351.c **** }
|
||
306 .loc 1 55 15 view .LVU70
|
||
307 .LBE2:
|
||
34:Src/si5351.c **** int rx_div = 0;
|
||
308 .loc 1 34 9 view .LVU71
|
||
309 0080 4FF0000A mov r10, #0
|
||
310 0084 12E0 b .L12
|
||
311 .LVL26:
|
||
312 .L21:
|
||
313 .LBB3:
|
||
42:Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL))
|
||
ARM GAS /tmp/ccY965Wh.s page 8
|
||
|
||
|
||
314 .loc 1 42 13 view .LVU72
|
||
315 0086 0025 movs r5, #0
|
||
316 .LBE3:
|
||
36:Src/si5351.c ****
|
||
317 .loc 1 36 9 view .LVU73
|
||
318 0088 0126 movs r6, #1
|
||
319 008a D7E7 b .L13
|
||
320 .LVL27:
|
||
321 .L23:
|
||
61:Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d
|
||
322 .loc 1 61 15 view .LVU74
|
||
323 008c 0620 movs r0, #6
|
||
324 .LVL28:
|
||
325 .L18:
|
||
64:Src/si5351.c ****
|
||
65:Src/si5351.c **** if (d * fout < 600e6) // VCO frequency to low check and maintain an even
|
||
326 .loc 1 65 9 is_stmt 1 view .LVU75
|
||
327 .loc 1 65 15 is_stmt 0 view .LVU76
|
||
328 008e 08FB00F2 mul r2, r8, r0
|
||
329 .loc 1 65 12 view .LVU77
|
||
330 0092 474B ldr r3, .L29+32
|
||
331 0094 9A42 cmp r2, r3
|
||
332 0096 44D8 bhi .L24
|
||
66:Src/si5351.c **** d += 2;
|
||
333 .loc 1 66 13 is_stmt 1 view .LVU78
|
||
334 .loc 1 66 15 is_stmt 0 view .LVU79
|
||
335 0098 0230 adds r0, r0, #2
|
||
336 .LVL29:
|
||
36:Src/si5351.c ****
|
||
337 .loc 1 36 9 view .LVU80
|
||
338 009a 0126 movs r6, #1
|
||
35:Src/si5351.c **** int r = 1;
|
||
339 .loc 1 35 9 view .LVU81
|
||
340 009c 0025 movs r5, #0
|
||
34:Src/si5351.c **** int rx_div = 0;
|
||
341 .loc 1 34 9 view .LVU82
|
||
342 009e AA46 mov r10, r5
|
||
343 00a0 04E0 b .L12
|
||
344 .LVL30:
|
||
345 .L20:
|
||
36:Src/si5351.c ****
|
||
346 .loc 1 36 9 view .LVU83
|
||
347 00a2 0126 movs r6, #1
|
||
35:Src/si5351.c **** int r = 1;
|
||
348 .loc 1 35 9 view .LVU84
|
||
349 00a4 0025 movs r5, #0
|
||
39:Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas
|
||
350 .loc 1 39 20 view .LVU85
|
||
351 00a6 4FF00C0A mov r10, #12
|
||
32:Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY
|
||
352 .loc 1 32 14 view .LVU86
|
||
353 00aa 0420 movs r0, #4
|
||
354 .LVL31:
|
||
355 .L12:
|
||
67:Src/si5351.c **** }
|
||
68:Src/si5351.c **** msx_p1 = 128 * d - 512;
|
||
356 .loc 1 68 5 is_stmt 1 view .LVU87
|
||
ARM GAS /tmp/ccY965Wh.s page 9
|
||
|
||
|
||
357 .loc 1 68 22 is_stmt 0 view .LVU88
|
||
358 00ac 00F10077 add r7, r0, #33554432
|
||
359 00b0 043F subs r7, r7, #4
|
||
360 .loc 1 68 12 view .LVU89
|
||
361 00b2 FF01 lsls r7, r7, #7
|
||
362 .LVL32:
|
||
69:Src/si5351.c ****
|
||
70:Src/si5351.c **** uint32_t fvco = (uint32_t) d * r * fout;
|
||
363 .loc 1 70 5 is_stmt 1 view .LVU90
|
||
364 .loc 1 70 34 is_stmt 0 view .LVU91
|
||
365 00b4 06FB00F0 mul r0, r6, r0
|
||
366 .LVL33:
|
||
71:Src/si5351.c ****
|
||
72:Src/si5351.c **** // Calc Feedback Multisynth Divider
|
||
73:Src/si5351.c **** double fmd = (double)fvco / SI5351_CRYSTAL_FREQ; // The FMD value has been found
|
||
367 .loc 1 73 5 is_stmt 1 view .LVU92
|
||
368 .loc 1 73 18 is_stmt 0 view .LVU93
|
||
369 00b8 08FB00F0 mul r0, r8, r0
|
||
370 .LVL34:
|
||
371 .loc 1 73 18 view .LVU94
|
||
372 00bc FFF7FEFF bl __aeabi_ui2d
|
||
373 .LVL35:
|
||
374 .loc 1 73 12 view .LVU95
|
||
375 00c0 35A3 adr r3, .L29+8
|
||
376 00c2 D3E90023 ldrd r2, [r3]
|
||
377 00c6 FFF7FEFF bl __aeabi_ddiv
|
||
378 .LVL36:
|
||
379 00ca 8046 mov r8, r0
|
||
380 .LVL37:
|
||
381 .loc 1 73 12 view .LVU96
|
||
382 00cc 8946 mov r9, r1
|
||
383 .LVL38:
|
||
74:Src/si5351.c **** int a = fmd; // a is the integer part of the FMD value
|
||
384 .loc 1 74 5 is_stmt 1 view .LVU97
|
||
385 .loc 1 74 9 is_stmt 0 view .LVU98
|
||
386 00ce FFF7FEFF bl __aeabi_d2iz
|
||
387 .LVL39:
|
||
388 00d2 0646 mov r6, r0
|
||
389 .LVL40:
|
||
75:Src/si5351.c ****
|
||
76:Src/si5351.c **** double b_c = (double)fmd - a; // Get b/c
|
||
390 .loc 1 76 5 is_stmt 1 view .LVU99
|
||
391 .loc 1 76 30 is_stmt 0 view .LVU100
|
||
392 00d4 FFF7FEFF bl __aeabi_i2d
|
||
393 .LVL41:
|
||
394 .loc 1 76 30 view .LVU101
|
||
395 00d8 0246 mov r2, r0
|
||
396 00da 0B46 mov r3, r1
|
||
397 .loc 1 76 12 view .LVU102
|
||
398 00dc 4046 mov r0, r8
|
||
399 00de 4946 mov r1, r9
|
||
400 00e0 FFF7FEFF bl __aeabi_dsub
|
||
401 .LVL42:
|
||
402 00e4 8046 mov r8, r0
|
||
403 .LVL43:
|
||
404 .loc 1 76 12 view .LVU103
|
||
405 00e6 8946 mov r9, r1
|
||
ARM GAS /tmp/ccY965Wh.s page 10
|
||
|
||
|
||
406 .LVL44:
|
||
77:Src/si5351.c **** uint32_t c = 1048575UL;
|
||
407 .loc 1 77 5 is_stmt 1 view .LVU104
|
||
78:Src/si5351.c **** uint32_t b = (double)b_c * c;
|
||
408 .loc 1 78 5 view .LVU105
|
||
409 .loc 1 78 30 is_stmt 0 view .LVU106
|
||
410 00e8 2DA3 adr r3, .L29+16
|
||
411 00ea D3E90023 ldrd r2, [r3]
|
||
412 00ee FFF7FEFF bl __aeabi_dmul
|
||
413 .LVL45:
|
||
414 .loc 1 78 14 view .LVU107
|
||
415 00f2 FFF7FEFF bl __aeabi_d2uiz
|
||
416 .LVL46:
|
||
79:Src/si5351.c **** if (b > 0)
|
||
417 .loc 1 79 5 is_stmt 1 view .LVU108
|
||
418 .loc 1 79 8 is_stmt 0 view .LVU109
|
||
419 00f6 8346 mov fp, r0
|
||
420 00f8 B8B1 cbz r0, .L25
|
||
80:Src/si5351.c **** {
|
||
81:Src/si5351.c **** c = (double)b / b_c + 0.5; // Improves frequency precision in some cases
|
||
421 .loc 1 81 9 is_stmt 1 view .LVU110
|
||
422 .loc 1 81 13 is_stmt 0 view .LVU111
|
||
423 00fa FFF7FEFF bl __aeabi_ui2d
|
||
424 .LVL47:
|
||
425 .loc 1 81 23 view .LVU112
|
||
426 00fe 4246 mov r2, r8
|
||
427 0100 4B46 mov r3, r9
|
||
428 0102 FFF7FEFF bl __aeabi_ddiv
|
||
429 .LVL48:
|
||
430 .loc 1 81 29 view .LVU113
|
||
431 0106 0022 movs r2, #0
|
||
432 0108 2A4B ldr r3, .L29+36
|
||
433 010a FFF7FEFF bl __aeabi_dadd
|
||
434 .LVL49:
|
||
435 .loc 1 81 11 view .LVU114
|
||
436 010e FFF7FEFF bl __aeabi_d2uiz
|
||
437 .LVL50:
|
||
82:Src/si5351.c **** if (c > 1048575UL)
|
||
438 .loc 1 82 9 is_stmt 1 view .LVU115
|
||
439 .loc 1 82 12 is_stmt 0 view .LVU116
|
||
440 0112 B0F5801F cmp r0, #1048576
|
||
441 0116 09D3 bcc .L19
|
||
83:Src/si5351.c **** c = 1048575UL;
|
||
442 .loc 1 83 15 view .LVU117
|
||
443 0118 2748 ldr r0, .L29+40
|
||
444 .LVL51:
|
||
445 .loc 1 83 15 view .LVU118
|
||
446 011a 07E0 b .L19
|
||
447 .LVL52:
|
||
448 .L22:
|
||
34:Src/si5351.c **** int rx_div = 0;
|
||
449 .loc 1 34 9 view .LVU119
|
||
450 011c 4FF0000A mov r10, #0
|
||
451 0120 C4E7 b .L12
|
||
452 .LVL53:
|
||
453 .L24:
|
||
36:Src/si5351.c ****
|
||
ARM GAS /tmp/ccY965Wh.s page 11
|
||
|
||
|
||
454 .loc 1 36 9 view .LVU120
|
||
455 0122 0126 movs r6, #1
|
||
35:Src/si5351.c **** int r = 1;
|
||
456 .loc 1 35 9 view .LVU121
|
||
457 0124 0025 movs r5, #0
|
||
34:Src/si5351.c **** int rx_div = 0;
|
||
458 .loc 1 34 9 view .LVU122
|
||
459 0126 AA46 mov r10, r5
|
||
460 0128 C0E7 b .L12
|
||
461 .LVL54:
|
||
462 .L25:
|
||
77:Src/si5351.c **** uint32_t b = (double)b_c * c;
|
||
463 .loc 1 77 14 view .LVU123
|
||
464 012a 2348 ldr r0, .L29+40
|
||
465 .LVL55:
|
||
466 .L19:
|
||
84:Src/si5351.c **** }
|
||
85:Src/si5351.c ****
|
||
86:Src/si5351.c **** uint32_t msnx_p1 = 128 * a + 128 * b / c - 512; // See datasheet 3.2
|
||
467 .loc 1 86 5 is_stmt 1 view .LVU124
|
||
468 .loc 1 86 38 is_stmt 0 view .LVU125
|
||
469 012c 4FEACB1B lsl fp, fp, #7
|
||
470 .LVL56:
|
||
471 .loc 1 86 42 view .LVU126
|
||
472 0130 BBFBF0F3 udiv r3, fp, r0
|
||
473 .loc 1 86 32 view .LVU127
|
||
474 0134 03EBC616 add r6, r3, r6, lsl #7
|
||
475 .LVL57:
|
||
476 .loc 1 86 14 view .LVU128
|
||
477 0138 A6F50076 sub r6, r6, #512
|
||
478 .LVL58:
|
||
87:Src/si5351.c **** uint32_t msnx_p2 = 128 * b - c * (128 * b / c);
|
||
479 .loc 1 87 5 is_stmt 1 view .LVU129
|
||
480 .loc 1 87 14 is_stmt 0 view .LVU130
|
||
481 013c 00FB13BB mls fp, r0, r3, fp
|
||
482 .LVL59:
|
||
88:Src/si5351.c **** uint32_t msnx_p3 = c;
|
||
483 .loc 1 88 5 is_stmt 1 view .LVU131
|
||
89:Src/si5351.c ****
|
||
90:Src/si5351.c **** // Feedback Multisynth Divider registers
|
||
91:Src/si5351.c **** regs[0] = (msnx_p3 >> 8) & 0xFF;
|
||
484 .loc 1 91 5 view .LVU132
|
||
485 .loc 1 91 24 is_stmt 0 view .LVU133
|
||
486 0140 030A lsrs r3, r0, #8
|
||
487 .loc 1 91 13 view .LVU134
|
||
488 0142 2370 strb r3, [r4]
|
||
92:Src/si5351.c **** regs[1] = msnx_p3 & 0xFF;
|
||
489 .loc 1 92 5 is_stmt 1 view .LVU135
|
||
490 .loc 1 92 13 is_stmt 0 view .LVU136
|
||
491 0144 6070 strb r0, [r4, #1]
|
||
93:Src/si5351.c **** regs[2] = (msnx_p1 >> 16) & 0x03;
|
||
492 .loc 1 93 5 is_stmt 1 view .LVU137
|
||
493 .loc 1 93 31 is_stmt 0 view .LVU138
|
||
494 0146 C6F30143 ubfx r3, r6, #16, #2
|
||
495 .loc 1 93 13 view .LVU139
|
||
496 014a A370 strb r3, [r4, #2]
|
||
94:Src/si5351.c **** regs[3] = (msnx_p1 >> 8) & 0xFF;
|
||
ARM GAS /tmp/ccY965Wh.s page 12
|
||
|
||
|
||
497 .loc 1 94 5 is_stmt 1 view .LVU140
|
||
498 .loc 1 94 24 is_stmt 0 view .LVU141
|
||
499 014c 330A lsrs r3, r6, #8
|
||
500 .loc 1 94 13 view .LVU142
|
||
501 014e E370 strb r3, [r4, #3]
|
||
95:Src/si5351.c **** regs[4] = msnx_p1 & 0xFF;
|
||
502 .loc 1 95 5 is_stmt 1 view .LVU143
|
||
503 .loc 1 95 13 is_stmt 0 view .LVU144
|
||
504 0150 2671 strb r6, [r4, #4]
|
||
96:Src/si5351.c **** regs[5] = ((msnx_p3 >> 12) & 0xF0) + ((msnx_p2 >> 16) & 0x0F);
|
||
505 .loc 1 96 5 is_stmt 1 view .LVU145
|
||
506 .loc 1 96 25 is_stmt 0 view .LVU146
|
||
507 0152 000B lsrs r0, r0, #12
|
||
508 .LVL60:
|
||
509 .loc 1 96 32 view .LVU147
|
||
510 0154 00F0F000 and r0, r0, #240
|
||
511 .loc 1 96 59 view .LVU148
|
||
512 0158 CBF30343 ubfx r3, fp, #16, #4
|
||
513 .loc 1 96 40 view .LVU149
|
||
514 015c 1843 orrs r0, r0, r3
|
||
515 .loc 1 96 13 view .LVU150
|
||
516 015e 6071 strb r0, [r4, #5]
|
||
97:Src/si5351.c **** regs[6] = (msnx_p2 >> 8) & 0xFF;
|
||
517 .loc 1 97 5 is_stmt 1 view .LVU151
|
||
518 .loc 1 97 24 is_stmt 0 view .LVU152
|
||
519 0160 4FEA1B23 lsr r3, fp, #8
|
||
520 .loc 1 97 13 view .LVU153
|
||
521 0164 A371 strb r3, [r4, #6]
|
||
98:Src/si5351.c **** regs[7] = msnx_p2 & 0xFF;
|
||
522 .loc 1 98 5 is_stmt 1 view .LVU154
|
||
523 .loc 1 98 13 is_stmt 0 view .LVU155
|
||
524 0166 84F807B0 strb fp, [r4, #7]
|
||
99:Src/si5351.c ****
|
||
100:Src/si5351.c **** // Output Multisynth Divider registers
|
||
101:Src/si5351.c **** regs[8] = 0; // (msx_p3 >> 8) & 0xFF
|
||
525 .loc 1 101 5 is_stmt 1 view .LVU156
|
||
526 .loc 1 101 13 is_stmt 0 view .LVU157
|
||
527 016a 0023 movs r3, #0
|
||
528 016c 2372 strb r3, [r4, #8]
|
||
102:Src/si5351.c **** regs[9] = 1; // msx_p3 & 0xFF
|
||
529 .loc 1 102 5 is_stmt 1 view .LVU158
|
||
530 .loc 1 102 13 is_stmt 0 view .LVU159
|
||
531 016e 0122 movs r2, #1
|
||
532 0170 6272 strb r2, [r4, #9]
|
||
103:Src/si5351.c **** regs[10] = rx_div + msx_divby4 + ((msx_p1 >> 16) & 0x03);
|
||
533 .loc 1 103 5 is_stmt 1 view .LVU160
|
||
534 .loc 1 103 23 is_stmt 0 view .LVU161
|
||
535 0172 5544 add r5, r5, r10
|
||
536 .LVL61:
|
||
537 .loc 1 103 23 view .LVU162
|
||
538 0174 EDB2 uxtb r5, r5
|
||
539 .loc 1 103 54 view .LVU163
|
||
540 0176 C7F30142 ubfx r2, r7, #16, #2
|
||
541 .loc 1 103 36 view .LVU164
|
||
542 017a 1544 add r5, r5, r2
|
||
543 .loc 1 103 14 view .LVU165
|
||
544 017c A572 strb r5, [r4, #10]
|
||
ARM GAS /tmp/ccY965Wh.s page 13
|
||
|
||
|
||
104:Src/si5351.c **** regs[11] = (msx_p1 >> 8) & 0xFF;
|
||
545 .loc 1 104 5 is_stmt 1 view .LVU166
|
||
546 .loc 1 104 24 is_stmt 0 view .LVU167
|
||
547 017e 3A0A lsrs r2, r7, #8
|
||
548 .loc 1 104 14 view .LVU168
|
||
549 0180 E272 strb r2, [r4, #11]
|
||
105:Src/si5351.c **** regs[12] = msx_p1 & 0xFF;
|
||
550 .loc 1 105 5 is_stmt 1 view .LVU169
|
||
551 .loc 1 105 14 is_stmt 0 view .LVU170
|
||
552 0182 2773 strb r7, [r4, #12]
|
||
106:Src/si5351.c **** regs[13] = 0; // ((msx_p3 >> 12) & 0xF0) + (msx_p2 >> 16) & 0x0
|
||
553 .loc 1 106 5 is_stmt 1 view .LVU171
|
||
554 .loc 1 106 14 is_stmt 0 view .LVU172
|
||
555 0184 6373 strb r3, [r4, #13]
|
||
107:Src/si5351.c **** regs[14] = 0; // (msx_p2 >> 8) & 0xFF
|
||
556 .loc 1 107 5 is_stmt 1 view .LVU173
|
||
557 .loc 1 107 14 is_stmt 0 view .LVU174
|
||
558 0186 A373 strb r3, [r4, #14]
|
||
108:Src/si5351.c **** regs[15] = 0; // msx_p2 & 0xFF
|
||
559 .loc 1 108 5 is_stmt 1 view .LVU175
|
||
560 .loc 1 108 14 is_stmt 0 view .LVU176
|
||
561 0188 E373 strb r3, [r4, #15]
|
||
109:Src/si5351.c ****
|
||
110:Src/si5351.c **** // HAL_I2C_Master_Transmit(&hi2c2, Si5351_ConfigStruct->HW_I2C_Address, reg_data, sizeof(reg_data),
|
||
111:Src/si5351.c **** return;
|
||
562 .loc 1 111 5 is_stmt 1 view .LVU177
|
||
112:Src/si5351.c **** }
|
||
563 .loc 1 112 1 is_stmt 0 view .LVU178
|
||
564 018a BDE8F88F pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
|
||
565 .LVL62:
|
||
566 .L30:
|
||
567 .loc 1 112 1 view .LVU179
|
||
568 018e 00BF .align 3
|
||
569 .L29:
|
||
570 0190 00000000 .word 0
|
||
571 0194 A3E1C141 .word 1103225251
|
||
572 0198 00000000 .word 0
|
||
573 019c FC647241 .word 1098015996
|
||
574 01a0 00000000 .word 0
|
||
575 01a4 FEFF2F41 .word 1093664766
|
||
576 01a8 80D1F008 .word 150000000
|
||
577 01ac 68780400 .word 292968
|
||
578 01b0 FF45C323 .word 599999999
|
||
579 01b4 0000E03F .word 1071644672
|
||
580 01b8 FFFF0F00 .word 1048575
|
||
581 .cfi_endproc
|
||
582 .LFE331:
|
||
584 .section .text.si5351_initialize,"ax",%progbits
|
||
585 .align 1
|
||
586 .global si5351_initialize
|
||
587 .syntax unified
|
||
588 .thumb
|
||
589 .thumb_func
|
||
591 si5351_initialize:
|
||
592 .LFB332:
|
||
113:Src/si5351.c ****
|
||
114:Src/si5351.c **** void si5351_initialize(){
|
||
ARM GAS /tmp/ccY965Wh.s page 14
|
||
|
||
|
||
593 .loc 1 114 25 is_stmt 1 view -0
|
||
594 .cfi_startproc
|
||
595 @ args = 0, pretend = 0, frame = 0
|
||
596 @ frame_needed = 0, uses_anonymous_args = 0
|
||
597 0000 10B5 push {r4, lr}
|
||
598 .LCFI7:
|
||
599 .cfi_def_cfa_offset 8
|
||
600 .cfi_offset 4, -8
|
||
601 .cfi_offset 14, -4
|
||
602 0002 0024 movs r4, #0
|
||
115:Src/si5351.c **** uint8_t dummy;
|
||
603 .loc 1 115 2 view .LVU181
|
||
116:Src/si5351.c **** // Initialize Si5351A
|
||
117:Src/si5351.c **** while (si5351_read8(0,dummy) & 0x80); // Wait for Si5351A to initialize
|
||
604 .loc 1 117 2 view .LVU182
|
||
605 .L32:
|
||
606 .loc 1 117 9 discriminator 1 view .LVU183
|
||
607 0004 2146 mov r1, r4
|
||
608 0006 0020 movs r0, #0
|
||
609 0008 FFF7FEFF bl si5351_read8
|
||
610 .LVL63:
|
||
611 000c 10F0800F tst r0, #128
|
||
612 0010 F8D1 bne .L32
|
||
118:Src/si5351.c **** oeb = 0xFF;
|
||
613 .loc 1 118 2 view .LVU184
|
||
614 .loc 1 118 6 is_stmt 0 view .LVU185
|
||
615 0012 FF21 movs r1, #255
|
||
616 0014 2C4B ldr r3, .L34
|
||
617 0016 1970 strb r1, [r3]
|
||
119:Src/si5351.c ****
|
||
120:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb); // Output Enable Control, disable all
|
||
618 .loc 1 120 5 is_stmt 1 view .LVU186
|
||
619 0018 0320 movs r0, #3
|
||
620 001a FFF7FEFF bl si5351_write8
|
||
621 .LVL64:
|
||
121:Src/si5351.c ****
|
||
122:Src/si5351.c **** si5351_write8(SI5351_INPUT_SOURCE, 0x00); // PLL Input Source, select the XTAL input
|
||
622 .loc 1 122 5 view .LVU187
|
||
623 001e 0021 movs r1, #0
|
||
624 0020 0F20 movs r0, #15
|
||
625 0022 FFF7FEFF bl si5351_write8
|
||
626 .LVL65:
|
||
123:Src/si5351.c **** si5351_write8(SI5351_OUT_DIS_STATE, 0x00); // stato bassa Z giu se disabilitati
|
||
627 .loc 1 123 5 view .LVU188
|
||
628 0026 0021 movs r1, #0
|
||
629 0028 1820 movs r0, #24
|
||
630 002a FFF7FEFF bl si5351_write8
|
||
631 .LVL66:
|
||
124:Src/si5351.c ****
|
||
125:Src/si5351.c **** // Output MultisynthN, e = 0, f = 1, MS0_P2 and MSO_P3
|
||
126:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0, 0x00);
|
||
632 .loc 1 126 5 view .LVU189
|
||
633 002e 0021 movs r1, #0
|
||
634 0030 2A20 movs r0, #42
|
||
635 0032 FFF7FEFF bl si5351_write8
|
||
636 .LVL67:
|
||
127:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+1, 0x01);
|
||
ARM GAS /tmp/ccY965Wh.s page 15
|
||
|
||
|
||
637 .loc 1 127 5 view .LVU190
|
||
638 0036 0121 movs r1, #1
|
||
639 0038 2B20 movs r0, #43
|
||
640 003a FFF7FEFF bl si5351_write8
|
||
641 .LVL68:
|
||
128:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+5, 0x00);
|
||
642 .loc 1 128 5 view .LVU191
|
||
643 003e 0021 movs r1, #0
|
||
644 0040 2F20 movs r0, #47
|
||
645 0042 FFF7FEFF bl si5351_write8
|
||
646 .LVL69:
|
||
129:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+6, 0x00);
|
||
647 .loc 1 129 5 view .LVU192
|
||
648 0046 0021 movs r1, #0
|
||
649 0048 3020 movs r0, #48
|
||
650 004a FFF7FEFF bl si5351_write8
|
||
651 .LVL70:
|
||
130:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH0+7, 0x00);
|
||
652 .loc 1 130 5 view .LVU193
|
||
653 004e 0021 movs r1, #0
|
||
654 0050 3120 movs r0, #49
|
||
655 0052 FFF7FEFF bl si5351_write8
|
||
656 .LVL71:
|
||
131:Src/si5351.c ****
|
||
132:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1, 0x00);
|
||
657 .loc 1 132 5 view .LVU194
|
||
658 0056 0021 movs r1, #0
|
||
659 0058 3220 movs r0, #50
|
||
660 005a FFF7FEFF bl si5351_write8
|
||
661 .LVL72:
|
||
133:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+1, 0x01);
|
||
662 .loc 1 133 5 view .LVU195
|
||
663 005e 0121 movs r1, #1
|
||
664 0060 3320 movs r0, #51
|
||
665 0062 FFF7FEFF bl si5351_write8
|
||
666 .LVL73:
|
||
134:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+5, 0x00);
|
||
667 .loc 1 134 5 view .LVU196
|
||
668 0066 0021 movs r1, #0
|
||
669 0068 3720 movs r0, #55
|
||
670 006a FFF7FEFF bl si5351_write8
|
||
671 .LVL74:
|
||
135:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+6, 0x00);
|
||
672 .loc 1 135 5 view .LVU197
|
||
673 006e 0021 movs r1, #0
|
||
674 0070 3820 movs r0, #56
|
||
675 0072 FFF7FEFF bl si5351_write8
|
||
676 .LVL75:
|
||
136:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH1+7, 0x00);
|
||
677 .loc 1 136 5 view .LVU198
|
||
678 0076 0021 movs r1, #0
|
||
679 0078 3920 movs r0, #57
|
||
680 007a FFF7FEFF bl si5351_write8
|
||
681 .LVL76:
|
||
137:Src/si5351.c ****
|
||
138:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2, 0x00);
|
||
682 .loc 1 138 5 view .LVU199
|
||
ARM GAS /tmp/ccY965Wh.s page 16
|
||
|
||
|
||
683 007e 0021 movs r1, #0
|
||
684 0080 3A20 movs r0, #58
|
||
685 0082 FFF7FEFF bl si5351_write8
|
||
686 .LVL77:
|
||
139:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+1, 0x01);
|
||
687 .loc 1 139 5 view .LVU200
|
||
688 0086 0121 movs r1, #1
|
||
689 0088 3B20 movs r0, #59
|
||
690 008a FFF7FEFF bl si5351_write8
|
||
691 .LVL78:
|
||
140:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+5, 0x00);
|
||
692 .loc 1 140 5 view .LVU201
|
||
693 008e 0021 movs r1, #0
|
||
694 0090 3F20 movs r0, #63
|
||
695 0092 FFF7FEFF bl si5351_write8
|
||
696 .LVL79:
|
||
141:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+6, 0x00);
|
||
697 .loc 1 141 5 view .LVU202
|
||
698 0096 0021 movs r1, #0
|
||
699 0098 4020 movs r0, #64
|
||
700 009a FFF7FEFF bl si5351_write8
|
||
701 .LVL80:
|
||
142:Src/si5351.c **** si5351_write8(SI5351_MULTISYNTH2+7, 0x00);
|
||
702 .loc 1 142 5 view .LVU203
|
||
703 009e 0021 movs r1, #0
|
||
704 00a0 4120 movs r0, #65
|
||
705 00a2 FFF7FEFF bl si5351_write8
|
||
706 .LVL81:
|
||
143:Src/si5351.c ****
|
||
144:Src/si5351.c **** si5351_write8(SI5351_CLK0_CONTROL, 0x4F); // Power up CLK0, PLLA, MS0 operates in integer mod
|
||
707 .loc 1 144 5 view .LVU204
|
||
708 00a6 4F21 movs r1, #79
|
||
709 00a8 1020 movs r0, #16
|
||
710 00aa FFF7FEFF bl si5351_write8
|
||
711 .LVL82:
|
||
145:Src/si5351.c **** si5351_write8(SI5351_CLK1_CONTROL, 0x5F); // Power up CLK1, PLLA, MS0 operates in integer mod
|
||
712 .loc 1 145 5 view .LVU205
|
||
713 00ae 5F21 movs r1, #95
|
||
714 00b0 1120 movs r0, #17
|
||
715 00b2 FFF7FEFF bl si5351_write8
|
||
716 .LVL83:
|
||
146:Src/si5351.c **** si5351_write8(SI5351_CLK2_CONTROL, 0x6F); // Power up CLK2, PLLB, int, non inv, multisynth 2,
|
||
717 .loc 1 146 5 view .LVU206
|
||
718 00b6 6F21 movs r1, #111
|
||
719 00b8 1220 movs r0, #18
|
||
720 00ba FFF7FEFF bl si5351_write8
|
||
721 .LVL84:
|
||
147:Src/si5351.c ****
|
||
148:Src/si5351.c **** // Reference load configuration
|
||
149:Src/si5351.c **** si5351_write8(SI5351_CRYSTAL_LOAD, 0x12); // Set reference load C: 6 pF = 0x12, 8 pF =
|
||
722 .loc 1 149 5 view .LVU207
|
||
723 00be 1221 movs r1, #18
|
||
724 00c0 B720 movs r0, #183
|
||
725 00c2 FFF7FEFF bl si5351_write8
|
||
726 .LVL85:
|
||
150:Src/si5351.c **** }
|
||
727 .loc 1 150 1 is_stmt 0 view .LVU208
|
||
ARM GAS /tmp/ccY965Wh.s page 17
|
||
|
||
|
||
728 00c6 10BD pop {r4, pc}
|
||
729 .L35:
|
||
730 .align 2
|
||
731 .L34:
|
||
732 00c8 00000000 .word oeb
|
||
733 .cfi_endproc
|
||
734 .LFE332:
|
||
736 .section .text.si5351_set_frequency,"ax",%progbits
|
||
737 .align 1
|
||
738 .global si5351_set_frequency
|
||
739 .syntax unified
|
||
740 .thumb
|
||
741 .thumb_func
|
||
743 si5351_set_frequency:
|
||
744 .LVL86:
|
||
745 .LFB333:
|
||
151:Src/si5351.c ****
|
||
152:Src/si5351.c **** void si5351_set_frequency(uint32_t freq, uint8_t pll){
|
||
746 .loc 1 152 54 is_stmt 1 view -0
|
||
747 .cfi_startproc
|
||
748 @ args = 0, pretend = 0, frame = 16
|
||
749 @ frame_needed = 0, uses_anonymous_args = 0
|
||
750 .loc 1 152 54 is_stmt 0 view .LVU210
|
||
751 0000 10B5 push {r4, lr}
|
||
752 .LCFI8:
|
||
753 .cfi_def_cfa_offset 8
|
||
754 .cfi_offset 4, -8
|
||
755 .cfi_offset 14, -4
|
||
756 0002 84B0 sub sp, sp, #16
|
||
757 .LCFI9:
|
||
758 .cfi_def_cfa_offset 24
|
||
759 0004 0C46 mov r4, r1
|
||
153:Src/si5351.c **** uint8_t regs[16];
|
||
760 .loc 1 153 2 is_stmt 1 view .LVU211
|
||
154:Src/si5351.c **** CalcRegisters(freq, regs);
|
||
761 .loc 1 154 2 view .LVU212
|
||
762 0006 6946 mov r1, sp
|
||
763 .LVL87:
|
||
764 .loc 1 154 2 is_stmt 0 view .LVU213
|
||
765 0008 FFF7FEFF bl CalcRegisters
|
||
766 .LVL88:
|
||
155:Src/si5351.c ****
|
||
156:Src/si5351.c **** // Load Output Multisynth0 with d (e and f already set during init. and never changed)
|
||
157:Src/si5351.c **** if(pll == 0){
|
||
767 .loc 1 157 2 is_stmt 1 view .LVU214
|
||
768 .loc 1 157 4 is_stmt 0 view .LVU215
|
||
769 000c 94B1 cbz r4, .L47
|
||
158:Src/si5351.c **** for (int i = 0; i < 8; i++)
|
||
159:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]);
|
||
160:Src/si5351.c **** for (int i = 10; i < 13; i++)
|
||
161:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
|
||
162:Src/si5351.c **** } else if(pll == 1){
|
||
770 .loc 1 162 9 is_stmt 1 view .LVU216
|
||
771 .loc 1 162 11 is_stmt 0 view .LVU217
|
||
772 000e 012C cmp r4, #1
|
||
773 0010 1FD1 bne .L42
|
||
774 .LBB4:
|
||
ARM GAS /tmp/ccY965Wh.s page 18
|
||
|
||
|
||
163:Src/si5351.c **** for (int i = 0; i < 8; i++)
|
||
775 .loc 1 163 12 view .LVU218
|
||
776 0012 0024 movs r4, #0
|
||
777 .LVL89:
|
||
778 .loc 1 163 12 view .LVU219
|
||
779 0014 2EE0 b .L43
|
||
780 .LVL90:
|
||
781 .L39:
|
||
782 .loc 1 163 12 view .LVU220
|
||
783 .LBE4:
|
||
784 .LBB5:
|
||
159:Src/si5351.c **** for (int i = 10; i < 13; i++)
|
||
785 .loc 1 159 4 is_stmt 1 view .LVU221
|
||
786 0016 04F11003 add r3, r4, #16
|
||
787 001a 6B44 add r3, sp, r3
|
||
788 001c 04F11A00 add r0, r4, #26
|
||
789 0020 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
|
||
790 0024 C0B2 uxtb r0, r0
|
||
791 0026 FFF7FEFF bl si5351_write8
|
||
792 .LVL91:
|
||
158:Src/si5351.c **** for (int i = 0; i < 8; i++)
|
||
793 .loc 1 158 27 discriminator 3 view .LVU222
|
||
794 002a 0134 adds r4, r4, #1
|
||
795 .LVL92:
|
||
796 .L37:
|
||
158:Src/si5351.c **** for (int i = 0; i < 8; i++)
|
||
797 .loc 1 158 21 discriminator 1 view .LVU223
|
||
798 002c 072C cmp r4, #7
|
||
799 002e F2DD ble .L39
|
||
800 .LBE5:
|
||
801 .LBB6:
|
||
160:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
|
||
802 .loc 1 160 12 is_stmt 0 view .LVU224
|
||
803 0030 0A24 movs r4, #10
|
||
804 .LVL93:
|
||
160:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
|
||
805 .loc 1 160 12 view .LVU225
|
||
806 0032 0CE0 b .L40
|
||
807 .LVL94:
|
||
808 .L47:
|
||
160:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
|
||
809 .loc 1 160 12 view .LVU226
|
||
810 .LBE6:
|
||
811 .LBB7:
|
||
158:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]);
|
||
812 .loc 1 158 12 view .LVU227
|
||
813 0034 0024 movs r4, #0
|
||
814 0036 F9E7 b .L37
|
||
815 .LVL95:
|
||
816 .L41:
|
||
158:Src/si5351.c **** si5351_write8(SI5351_PLLA + i, regs[i]);
|
||
817 .loc 1 158 12 view .LVU228
|
||
818 .LBE7:
|
||
819 .LBB8:
|
||
161:Src/si5351.c **** } else if(pll == 1){
|
||
820 .loc 1 161 11 is_stmt 1 view .LVU229
|
||
821 0038 04F11003 add r3, r4, #16
|
||
ARM GAS /tmp/ccY965Wh.s page 19
|
||
|
||
|
||
822 003c 6B44 add r3, sp, r3
|
||
823 003e 04F12200 add r0, r4, #34
|
||
824 0042 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
|
||
825 0046 C0B2 uxtb r0, r0
|
||
826 0048 FFF7FEFF bl si5351_write8
|
||
827 .LVL96:
|
||
160:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
|
||
828 .loc 1 160 29 discriminator 3 view .LVU230
|
||
829 004c 0134 adds r4, r4, #1
|
||
830 .LVL97:
|
||
831 .L40:
|
||
160:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
|
||
832 .loc 1 160 22 discriminator 1 view .LVU231
|
||
833 004e 0C2C cmp r4, #12
|
||
834 0050 F2DD ble .L41
|
||
835 .LVL98:
|
||
836 .L42:
|
||
160:Src/si5351.c **** si5351_write8(34 + i, regs[i]);
|
||
837 .loc 1 160 22 is_stmt 0 discriminator 1 view .LVU232
|
||
838 .LBE8:
|
||
164:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
|
||
165:Src/si5351.c **** for (int i = 10; i < 13; i++)
|
||
166:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
|
||
167:Src/si5351.c **** }
|
||
168:Src/si5351.c ****
|
||
169:Src/si5351.c **** // Reset PLLA
|
||
170:Src/si5351.c **** // delayMicroseconds(500); // Allow registers to settle before resetting the PLL
|
||
171:Src/si5351.c **** si5351_write8(SI5351_RESET, 0x20);
|
||
839 .loc 1 171 5 is_stmt 1 view .LVU233
|
||
840 0052 2021 movs r1, #32
|
||
841 0054 B120 movs r0, #177
|
||
842 0056 FFF7FEFF bl si5351_write8
|
||
843 .LVL99:
|
||
172:Src/si5351.c **** }
|
||
844 .loc 1 172 1 is_stmt 0 view .LVU234
|
||
845 005a 04B0 add sp, sp, #16
|
||
846 .LCFI10:
|
||
847 .cfi_remember_state
|
||
848 .cfi_def_cfa_offset 8
|
||
849 @ sp needed
|
||
850 005c 10BD pop {r4, pc}
|
||
851 .LVL100:
|
||
852 .L44:
|
||
853 .LCFI11:
|
||
854 .cfi_restore_state
|
||
855 .LBB9:
|
||
164:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
|
||
856 .loc 1 164 4 is_stmt 1 view .LVU235
|
||
857 005e 04F11003 add r3, r4, #16
|
||
858 0062 6B44 add r3, sp, r3
|
||
859 0064 04F12200 add r0, r4, #34
|
||
860 0068 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
|
||
861 006c C0B2 uxtb r0, r0
|
||
862 006e FFF7FEFF bl si5351_write8
|
||
863 .LVL101:
|
||
163:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
|
||
864 .loc 1 163 27 discriminator 3 view .LVU236
|
||
ARM GAS /tmp/ccY965Wh.s page 20
|
||
|
||
|
||
865 0072 0134 adds r4, r4, #1
|
||
866 .LVL102:
|
||
867 .L43:
|
||
163:Src/si5351.c **** si5351_write8(SI5351_PLLB + i, regs[i]);
|
||
868 .loc 1 163 21 discriminator 1 view .LVU237
|
||
869 0074 072C cmp r4, #7
|
||
870 0076 F2DD ble .L44
|
||
871 .LBE9:
|
||
872 .LBB10:
|
||
165:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
|
||
873 .loc 1 165 12 is_stmt 0 view .LVU238
|
||
874 0078 0A24 movs r4, #10
|
||
875 .LVL103:
|
||
165:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
|
||
876 .loc 1 165 12 view .LVU239
|
||
877 007a 0AE0 b .L45
|
||
878 .LVL104:
|
||
879 .L46:
|
||
166:Src/si5351.c **** }
|
||
880 .loc 1 166 11 is_stmt 1 view .LVU240
|
||
881 007c 04F11003 add r3, r4, #16
|
||
882 0080 6B44 add r3, sp, r3
|
||
883 0082 04F12A00 add r0, r4, #42
|
||
884 0086 13F8101C ldrb r1, [r3, #-16] @ zero_extendqisi2
|
||
885 008a C0B2 uxtb r0, r0
|
||
886 008c FFF7FEFF bl si5351_write8
|
||
887 .LVL105:
|
||
165:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
|
||
888 .loc 1 165 29 discriminator 3 view .LVU241
|
||
889 0090 0134 adds r4, r4, #1
|
||
890 .LVL106:
|
||
891 .L45:
|
||
165:Src/si5351.c **** si5351_write8(42 + i, regs[i]);
|
||
892 .loc 1 165 22 discriminator 1 view .LVU242
|
||
893 0092 0C2C cmp r4, #12
|
||
894 0094 F2DD ble .L46
|
||
895 0096 DCE7 b .L42
|
||
896 .LBE10:
|
||
897 .cfi_endproc
|
||
898 .LFE333:
|
||
900 .section .text.si5351_off_clk,"ax",%progbits
|
||
901 .align 1
|
||
902 .global si5351_off_clk
|
||
903 .syntax unified
|
||
904 .thumb
|
||
905 .thumb_func
|
||
907 si5351_off_clk:
|
||
908 .LVL107:
|
||
909 .LFB334:
|
||
173:Src/si5351.c ****
|
||
174:Src/si5351.c **** void si5351_off_clk(uint8_t clk){
|
||
910 .loc 1 174 33 view -0
|
||
911 .cfi_startproc
|
||
912 @ args = 0, pretend = 0, frame = 0
|
||
913 @ frame_needed = 0, uses_anonymous_args = 0
|
||
914 .loc 1 174 33 is_stmt 0 view .LVU244
|
||
915 0000 08B5 push {r3, lr}
|
||
ARM GAS /tmp/ccY965Wh.s page 21
|
||
|
||
|
||
916 .LCFI12:
|
||
917 .cfi_def_cfa_offset 8
|
||
918 .cfi_offset 3, -8
|
||
919 .cfi_offset 14, -4
|
||
175:Src/si5351.c **** oeb |= 1U << clk;
|
||
920 .loc 1 175 2 is_stmt 1 view .LVU245
|
||
921 .loc 1 175 12 is_stmt 0 view .LVU246
|
||
922 0002 0123 movs r3, #1
|
||
923 0004 8340 lsls r3, r3, r0
|
||
924 .loc 1 175 6 view .LVU247
|
||
925 0006 044A ldr r2, .L53
|
||
926 0008 1178 ldrb r1, [r2] @ zero_extendqisi2
|
||
927 000a 1943 orrs r1, r1, r3
|
||
928 000c C9B2 uxtb r1, r1
|
||
929 000e 1170 strb r1, [r2]
|
||
176:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb);
|
||
930 .loc 1 176 2 is_stmt 1 view .LVU248
|
||
931 0010 0320 movs r0, #3
|
||
932 .LVL108:
|
||
933 .loc 1 176 2 is_stmt 0 view .LVU249
|
||
934 0012 FFF7FEFF bl si5351_write8
|
||
935 .LVL109:
|
||
177:Src/si5351.c **** }
|
||
936 .loc 1 177 1 view .LVU250
|
||
937 0016 08BD pop {r3, pc}
|
||
938 .L54:
|
||
939 .align 2
|
||
940 .L53:
|
||
941 0018 00000000 .word oeb
|
||
942 .cfi_endproc
|
||
943 .LFE334:
|
||
945 .section .text.si5351_on_clk,"ax",%progbits
|
||
946 .align 1
|
||
947 .global si5351_on_clk
|
||
948 .syntax unified
|
||
949 .thumb
|
||
950 .thumb_func
|
||
952 si5351_on_clk:
|
||
953 .LVL110:
|
||
954 .LFB335:
|
||
178:Src/si5351.c ****
|
||
179:Src/si5351.c **** void si5351_on_clk(uint8_t clk){
|
||
955 .loc 1 179 32 is_stmt 1 view -0
|
||
956 .cfi_startproc
|
||
957 @ args = 0, pretend = 0, frame = 0
|
||
958 @ frame_needed = 0, uses_anonymous_args = 0
|
||
959 .loc 1 179 32 is_stmt 0 view .LVU252
|
||
960 0000 08B5 push {r3, lr}
|
||
961 .LCFI13:
|
||
962 .cfi_def_cfa_offset 8
|
||
963 .cfi_offset 3, -8
|
||
964 .cfi_offset 14, -4
|
||
180:Src/si5351.c **** oeb &= ~(1U << clk);
|
||
965 .loc 1 180 2 is_stmt 1 view .LVU253
|
||
966 .loc 1 180 14 is_stmt 0 view .LVU254
|
||
967 0002 0123 movs r3, #1
|
||
968 0004 8340 lsls r3, r3, r0
|
||
ARM GAS /tmp/ccY965Wh.s page 22
|
||
|
||
|
||
969 .loc 1 180 6 view .LVU255
|
||
970 0006 044A ldr r2, .L57
|
||
971 0008 1178 ldrb r1, [r2] @ zero_extendqisi2
|
||
972 000a 21EA0301 bic r1, r1, r3
|
||
973 000e 1170 strb r1, [r2]
|
||
181:Src/si5351.c **** si5351_write8(SI5351_OUT_ENABLE, oeb);
|
||
974 .loc 1 181 2 is_stmt 1 view .LVU256
|
||
975 0010 0320 movs r0, #3
|
||
976 .LVL111:
|
||
977 .loc 1 181 2 is_stmt 0 view .LVU257
|
||
978 0012 FFF7FEFF bl si5351_write8
|
||
979 .LVL112:
|
||
182:Src/si5351.c **** }
|
||
980 .loc 1 182 1 view .LVU258
|
||
981 0016 08BD pop {r3, pc}
|
||
982 .L58:
|
||
983 .align 2
|
||
984 .L57:
|
||
985 0018 00000000 .word oeb
|
||
986 .cfi_endproc
|
||
987 .LFE335:
|
||
989 .global oeb
|
||
990 .section .bss.oeb,"aw",%nobits
|
||
993 oeb:
|
||
994 0000 00 .space 1
|
||
995 .text
|
||
996 .Letext0:
|
||
997 .file 2 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach
|
||
998 .file 3 "/home/fra/bin/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/
|
||
999 .file 4 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
|
||
1000 .file 5 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
|
||
1001 .file 6 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
|
||
1002 .file 7 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h"
|
||
1003 .file 8 "Inc/si5351.h"
|
||
ARM GAS /tmp/ccY965Wh.s page 23
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 si5351.c
|
||
/tmp/ccY965Wh.s:21 .text.si5351_write8:00000000 $t
|
||
/tmp/ccY965Wh.s:27 .text.si5351_write8:00000000 si5351_write8
|
||
/tmp/ccY965Wh.s:83 .text.si5351_write8:00000038 $d
|
||
/tmp/ccY965Wh.s:88 .text.si5351_read8:00000000 $t
|
||
/tmp/ccY965Wh.s:94 .text.si5351_read8:00000000 si5351_read8
|
||
/tmp/ccY965Wh.s:153 .text.si5351_read8:00000034 $d
|
||
/tmp/ccY965Wh.s:166 .text.CalcRegisters:00000000 $t
|
||
/tmp/ccY965Wh.s:172 .text.CalcRegisters:00000000 CalcRegisters
|
||
/tmp/ccY965Wh.s:570 .text.CalcRegisters:00000190 $d
|
||
/tmp/ccY965Wh.s:585 .text.si5351_initialize:00000000 $t
|
||
/tmp/ccY965Wh.s:591 .text.si5351_initialize:00000000 si5351_initialize
|
||
/tmp/ccY965Wh.s:732 .text.si5351_initialize:000000c8 $d
|
||
/tmp/ccY965Wh.s:993 .bss.oeb:00000000 oeb
|
||
/tmp/ccY965Wh.s:737 .text.si5351_set_frequency:00000000 $t
|
||
/tmp/ccY965Wh.s:743 .text.si5351_set_frequency:00000000 si5351_set_frequency
|
||
/tmp/ccY965Wh.s:901 .text.si5351_off_clk:00000000 $t
|
||
/tmp/ccY965Wh.s:907 .text.si5351_off_clk:00000000 si5351_off_clk
|
||
/tmp/ccY965Wh.s:941 .text.si5351_off_clk:00000018 $d
|
||
/tmp/ccY965Wh.s:946 .text.si5351_on_clk:00000000 $t
|
||
/tmp/ccY965Wh.s:952 .text.si5351_on_clk:00000000 si5351_on_clk
|
||
/tmp/ccY965Wh.s:985 .text.si5351_on_clk:00000018 $d
|
||
/tmp/ccY965Wh.s:994 .bss.oeb:00000000 $d
|
||
|
||
UNDEFINED SYMBOLS
|
||
HAL_I2C_IsDeviceReady
|
||
HAL_I2C_Mem_Write
|
||
hi2c1
|
||
HAL_I2C_Mem_Read
|
||
__aeabi_ui2d
|
||
__aeabi_ddiv
|
||
__aeabi_d2uiz
|
||
__aeabi_d2iz
|
||
__aeabi_i2d
|
||
__aeabi_dsub
|
||
__aeabi_dmul
|
||
__aeabi_dadd
|