ARM GAS  /tmp/ccCxCgQe.s 			page 1


   1              		.cpu cortex-m0plus
   2              		.eabi_attribute 20, 1
   3              		.eabi_attribute 21, 1
   4              		.eabi_attribute 23, 3
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 1
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"main.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.section	.text.MX_GPIO_Init,"ax",%progbits
  16              		.align	1
  17              		.arch armv6s-m
  18              		.syntax unified
  19              		.code	16
  20              		.thumb_func
  21              		.fpu softvfp
  23              	MX_GPIO_Init:
  24              	.LFB300:
  25              		.file 1 "Core/Src/main.c"
   1:Core/Src/main.c **** /* USER CODE BEGIN Header */
   2:Core/Src/main.c **** /**
   3:Core/Src/main.c ****   ******************************************************************************
   4:Core/Src/main.c ****   * @file           : main.c
   5:Core/Src/main.c ****   * @brief          : Main program body
   6:Core/Src/main.c ****   ******************************************************************************
   7:Core/Src/main.c ****   * @attention
   8:Core/Src/main.c ****   *
   9:Core/Src/main.c ****   * Copyright (c) 2021 STMicroelectronics.
  10:Core/Src/main.c ****   * All rights reserved.
  11:Core/Src/main.c ****   *
  12:Core/Src/main.c ****   * This software is licensed under terms that can be found in the LICENSE file
  13:Core/Src/main.c ****   * in the root directory of this software component.
  14:Core/Src/main.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  15:Core/Src/main.c ****   *
  16:Core/Src/main.c ****   ******************************************************************************
  17:Core/Src/main.c ****   */
  18:Core/Src/main.c **** /* USER CODE END Header */
  19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
  20:Core/Src/main.c **** #include "main.h"
  21:Core/Src/main.c **** 
  22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
  23:Core/Src/main.c **** /* USER CODE BEGIN Includes */
  24:Core/Src/main.c **** #include <stdint.h>
  25:Core/Src/main.c **** #include "si5351.h"
  26:Core/Src/main.c **** 
  27:Core/Src/main.c **** /* USER CODE END Includes */
  28:Core/Src/main.c **** 
  29:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
  30:Core/Src/main.c **** /* USER CODE BEGIN PTD */
  31:Core/Src/main.c **** 
  32:Core/Src/main.c **** /* USER CODE END PTD */
  33:Core/Src/main.c **** 
ARM GAS  /tmp/ccCxCgQe.s 			page 2


  34:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
  35:Core/Src/main.c **** /* USER CODE BEGIN PD */
  36:Core/Src/main.c **** /* USER CODE END PD */
  37:Core/Src/main.c **** 
  38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
  39:Core/Src/main.c **** /* USER CODE BEGIN PM */
  40:Core/Src/main.c **** 
  41:Core/Src/main.c **** /* USER CODE END PM */
  42:Core/Src/main.c **** 
  43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
  44:Core/Src/main.c **** I2C_HandleTypeDef hi2c2;
  45:Core/Src/main.c **** 
  46:Core/Src/main.c **** /* USER CODE BEGIN PV */
  47:Core/Src/main.c **** uint32_t frequenza;
  48:Core/Src/main.c **** 
  49:Core/Src/main.c **** /* USER CODE END PV */
  50:Core/Src/main.c **** 
  51:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
  52:Core/Src/main.c **** void SystemClock_Config(void);
  53:Core/Src/main.c **** static void MX_GPIO_Init(void);
  54:Core/Src/main.c **** static void MX_I2C2_Init(void);
  55:Core/Src/main.c **** /* USER CODE BEGIN PFP */
  56:Core/Src/main.c **** 
  57:Core/Src/main.c **** /* USER CODE END PFP */
  58:Core/Src/main.c **** 
  59:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
  60:Core/Src/main.c **** /* USER CODE BEGIN 0 */
  61:Core/Src/main.c **** 
  62:Core/Src/main.c **** /* USER CODE END 0 */
  63:Core/Src/main.c **** 
  64:Core/Src/main.c **** /**
  65:Core/Src/main.c ****   * @brief  The application entry point.
  66:Core/Src/main.c ****   * @retval int
  67:Core/Src/main.c ****   */
  68:Core/Src/main.c **** int main(void)
  69:Core/Src/main.c **** {
  70:Core/Src/main.c ****   /* USER CODE BEGIN 1 */
  71:Core/Src/main.c **** 
  72:Core/Src/main.c ****   /* USER CODE END 1 */
  73:Core/Src/main.c **** 
  74:Core/Src/main.c ****   /* MCU Configuration--------------------------------------------------------*/
  75:Core/Src/main.c **** 
  76:Core/Src/main.c ****   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  77:Core/Src/main.c ****   HAL_Init();
  78:Core/Src/main.c **** 
  79:Core/Src/main.c ****   /* USER CODE BEGIN Init */
  80:Core/Src/main.c **** 
  81:Core/Src/main.c ****   /* USER CODE END Init */
  82:Core/Src/main.c **** 
  83:Core/Src/main.c ****   /* Configure the system clock */
  84:Core/Src/main.c ****   SystemClock_Config();
  85:Core/Src/main.c **** 
  86:Core/Src/main.c ****   /* USER CODE BEGIN SysInit */
  87:Core/Src/main.c **** 
  88:Core/Src/main.c ****   /* USER CODE END SysInit */
  89:Core/Src/main.c **** 
  90:Core/Src/main.c ****   /* Initialize all configured peripherals */
ARM GAS  /tmp/ccCxCgQe.s 			page 3


  91:Core/Src/main.c ****   MX_GPIO_Init();
  92:Core/Src/main.c ****   MX_I2C2_Init();
  93:Core/Src/main.c ****   /* USER CODE BEGIN 2 */
  94:Core/Src/main.c ****   	frequenza = 1359000;
  95:Core/Src/main.c **** 	HAL_Delay(100);
  96:Core/Src/main.c **** 	si5351_Init();
  97:Core/Src/main.c **** 	HAL_Delay(500);
  98:Core/Src/main.c **** 	CalcRegisters(frequenza);
  99:Core/Src/main.c ****   /* USER CODE END 2 */
 100:Core/Src/main.c **** 
 101:Core/Src/main.c ****   /* Infinite loop */
 102:Core/Src/main.c ****   /* USER CODE BEGIN WHILE */
 103:Core/Src/main.c ****   while (1)
 104:Core/Src/main.c ****   {
 105:Core/Src/main.c ****     /* USER CODE END WHILE */
 106:Core/Src/main.c **** 
 107:Core/Src/main.c ****     /* USER CODE BEGIN 3 */
 108:Core/Src/main.c **** 
 109:Core/Src/main.c **** 
 110:Core/Src/main.c **** //	HAL_I2C_Master_Transmit(&hi2c2, ((uint16_t)0x60)<<1, "ciao", 4, HAL_MAX_DELAY);
 111:Core/Src/main.c **** 	// da 24 a 36
 112:Core/Src/main.c **** /*
 113:Core/Src/main.c **** 	a = 24;
 114:Core/Src/main.c **** 	b = 28437;
 115:Core/Src/main.c **** 	c = 1048562;
 116:Core/Src/main.c **** 	d = 442;
 117:Core/Src/main.c **** 	e = 0;
 118:Core/Src/main.c **** 	f = 1;
 119:Core/Src/main.c **** 	*/
 120:Core/Src/main.c **** /*
 121:Core/Src/main.c **** 	si5351_setupPLL(SI5351_PLL_A, a, b, c);
 122:Core/Src/main.c **** 	HAL_Delay(10);
 123:Core/Src/main.c **** 	si5351_setupMultisynth(0, SI5351_PLL_A, d, e, f);
 124:Core/Src/main.c **** 	HAL_Delay(10);
 125:Core/Src/main.c **** 	si5351_setupRdiv(0, SI5351_R_DIV_1);
 126:Core/Src/main.c **** 	HAL_Delay(10);
 127:Core/Src/main.c **** 
 128:Core/Src/main.c **** 	si5351_setupMultisynth(1, SI5351_PLL_A, d, e, f);
 129:Core/Src/main.c **** 	HAL_Delay(10);
 130:Core/Src/main.c **** 	si5351_setupRdiv(1, SI5351_R_DIV_1);
 131:Core/Src/main.c **** 	HAL_Delay(10);
 132:Core/Src/main.c **** */
 133:Core/Src/main.c **** 	if(HAL_GPIO_ReadPin(UP_GPIO_Port, UP_Pin)){
 134:Core/Src/main.c **** 		frequenza += 9000;
 135:Core/Src/main.c **** 		if(frequenza > 1800000) frequenza = 585000;
 136:Core/Src/main.c **** 		CalcRegisters(frequenza);
 137:Core/Src/main.c **** 	}
 138:Core/Src/main.c **** 
 139:Core/Src/main.c **** 	// 2a volta serve per avere fase non casuale
 140:Core/Src/main.c **** //	si5351_setupPLL(SI5351_PLL_A, 24, 28437, 1048562);
 141:Core/Src/main.c **** 
 142:Core/Src/main.c **** /*
 143:Core/Src/main.c **** 	si5351_setupPLL(SI5351_PLL_B, 28, 7012, 390625);
 144:Core/Src/main.c **** 	si5351_setupMultisynth(2, SI5351_PLL_B, 1336, 0, 1);
 145:Core/Src/main.c **** 	si5351_setupRdiv(2, SI5351_R_DIV_16);
 146:Core/Src/main.c **** */
 147:Core/Src/main.c **** 
ARM GAS  /tmp/ccCxCgQe.s 			page 4


 148:Core/Src/main.c **** 	si5351_enableOutputs(0xFF);
 149:Core/Src/main.c **** 	HAL_Delay(100);
 150:Core/Src/main.c **** 
 151:Core/Src/main.c ****   }
 152:Core/Src/main.c ****   /* USER CODE END 3 */
 153:Core/Src/main.c **** }
 154:Core/Src/main.c **** 
 155:Core/Src/main.c **** /**
 156:Core/Src/main.c ****   * @brief System Clock Configuration
 157:Core/Src/main.c ****   * @retval None
 158:Core/Src/main.c ****   */
 159:Core/Src/main.c **** void SystemClock_Config(void)
 160:Core/Src/main.c **** {
 161:Core/Src/main.c ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 162:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 163:Core/Src/main.c **** 
 164:Core/Src/main.c ****   /** Configure the main internal regulator output voltage
 165:Core/Src/main.c ****   */
 166:Core/Src/main.c ****   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 167:Core/Src/main.c ****   /** Initializes the RCC Oscillators according to the specified parameters
 168:Core/Src/main.c ****   * in the RCC_OscInitTypeDef structure.
 169:Core/Src/main.c ****   */
 170:Core/Src/main.c ****   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 171:Core/Src/main.c ****   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 172:Core/Src/main.c ****   RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
 173:Core/Src/main.c ****   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 174:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
 175:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 176:Core/Src/main.c ****   {
 177:Core/Src/main.c ****     Error_Handler();
 178:Core/Src/main.c ****   }
 179:Core/Src/main.c ****   /** Initializes the CPU, AHB and APB buses clocks
 180:Core/Src/main.c ****   */
 181:Core/Src/main.c ****   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 182:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1;
 183:Core/Src/main.c ****   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
 184:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 185:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 186:Core/Src/main.c **** 
 187:Core/Src/main.c ****   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 188:Core/Src/main.c ****   {
 189:Core/Src/main.c ****     Error_Handler();
 190:Core/Src/main.c ****   }
 191:Core/Src/main.c **** }
 192:Core/Src/main.c **** 
 193:Core/Src/main.c **** /**
 194:Core/Src/main.c ****   * @brief I2C2 Initialization Function
 195:Core/Src/main.c ****   * @param None
 196:Core/Src/main.c ****   * @retval None
 197:Core/Src/main.c ****   */
 198:Core/Src/main.c **** static void MX_I2C2_Init(void)
 199:Core/Src/main.c **** {
 200:Core/Src/main.c **** 
 201:Core/Src/main.c ****   /* USER CODE BEGIN I2C2_Init 0 */
 202:Core/Src/main.c **** 
 203:Core/Src/main.c ****   /* USER CODE END I2C2_Init 0 */
 204:Core/Src/main.c **** 
ARM GAS  /tmp/ccCxCgQe.s 			page 5


 205:Core/Src/main.c ****   /* USER CODE BEGIN I2C2_Init 1 */
 206:Core/Src/main.c **** 
 207:Core/Src/main.c ****   /* USER CODE END I2C2_Init 1 */
 208:Core/Src/main.c ****   hi2c2.Instance = I2C2;
 209:Core/Src/main.c ****   hi2c2.Init.Timing = 0x00303D5B;
 210:Core/Src/main.c ****   hi2c2.Init.OwnAddress1 = 0;
 211:Core/Src/main.c ****   hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 212:Core/Src/main.c ****   hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 213:Core/Src/main.c ****   hi2c2.Init.OwnAddress2 = 0;
 214:Core/Src/main.c ****   hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
 215:Core/Src/main.c ****   hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 216:Core/Src/main.c ****   hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 217:Core/Src/main.c ****   if (HAL_I2C_Init(&hi2c2) != HAL_OK)
 218:Core/Src/main.c ****   {
 219:Core/Src/main.c ****     Error_Handler();
 220:Core/Src/main.c ****   }
 221:Core/Src/main.c ****   /** Configure Analogue filter
 222:Core/Src/main.c ****   */
 223:Core/Src/main.c ****   if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
 224:Core/Src/main.c ****   {
 225:Core/Src/main.c ****     Error_Handler();
 226:Core/Src/main.c ****   }
 227:Core/Src/main.c ****   /** Configure Digital filter
 228:Core/Src/main.c ****   */
 229:Core/Src/main.c ****   if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
 230:Core/Src/main.c ****   {
 231:Core/Src/main.c ****     Error_Handler();
 232:Core/Src/main.c ****   }
 233:Core/Src/main.c ****   /* USER CODE BEGIN I2C2_Init 2 */
 234:Core/Src/main.c **** 
 235:Core/Src/main.c ****   /* USER CODE END I2C2_Init 2 */
 236:Core/Src/main.c **** 
 237:Core/Src/main.c **** }
 238:Core/Src/main.c **** 
 239:Core/Src/main.c **** /**
 240:Core/Src/main.c ****   * @brief GPIO Initialization Function
 241:Core/Src/main.c ****   * @param None
 242:Core/Src/main.c ****   * @retval None
 243:Core/Src/main.c ****   */
 244:Core/Src/main.c **** static void MX_GPIO_Init(void)
 245:Core/Src/main.c **** {
  26              		.loc 1 245 1 view -0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 32
  29              		@ frame_needed = 0, uses_anonymous_args = 0
  30 0000 00B5     		push	{lr}
  31              	.LCFI0:
  32              		.cfi_def_cfa_offset 4
  33              		.cfi_offset 14, -4
  34 0002 89B0     		sub	sp, sp, #36
  35              	.LCFI1:
  36              		.cfi_def_cfa_offset 40
 246:Core/Src/main.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
  37              		.loc 1 246 3 view .LVU1
  38              		.loc 1 246 20 is_stmt 0 view .LVU2
  39 0004 1422     		movs	r2, #20
  40 0006 0021     		movs	r1, #0
ARM GAS  /tmp/ccCxCgQe.s 			page 6


  41 0008 03A8     		add	r0, sp, #12
  42 000a FFF7FEFF 		bl	memset
  43              	.LVL0:
 247:Core/Src/main.c **** 
 248:Core/Src/main.c ****   /* GPIO Ports Clock Enable */
 249:Core/Src/main.c ****   __HAL_RCC_GPIOC_CLK_ENABLE();
  44              		.loc 1 249 3 is_stmt 1 view .LVU3
  45              	.LBB4:
  46              		.loc 1 249 3 view .LVU4
  47              		.loc 1 249 3 view .LVU5
  48 000e 0E4B     		ldr	r3, .L2
  49 0010 596B     		ldr	r1, [r3, #52]
  50 0012 0422     		movs	r2, #4
  51 0014 1143     		orrs	r1, r2
  52 0016 5963     		str	r1, [r3, #52]
  53              		.loc 1 249 3 view .LVU6
  54 0018 596B     		ldr	r1, [r3, #52]
  55 001a 0A40     		ands	r2, r1
  56 001c 0192     		str	r2, [sp, #4]
  57              		.loc 1 249 3 view .LVU7
  58 001e 019A     		ldr	r2, [sp, #4]
  59              	.LBE4:
  60              		.loc 1 249 3 view .LVU8
 250:Core/Src/main.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
  61              		.loc 1 250 3 view .LVU9
  62              	.LBB5:
  63              		.loc 1 250 3 view .LVU10
  64              		.loc 1 250 3 view .LVU11
  65 0020 596B     		ldr	r1, [r3, #52]
  66 0022 0122     		movs	r2, #1
  67 0024 1143     		orrs	r1, r2
  68 0026 5963     		str	r1, [r3, #52]
  69              		.loc 1 250 3 view .LVU12
  70 0028 5B6B     		ldr	r3, [r3, #52]
  71 002a 1A40     		ands	r2, r3
  72 002c 0292     		str	r2, [sp, #8]
  73              		.loc 1 250 3 view .LVU13
  74 002e 029B     		ldr	r3, [sp, #8]
  75              	.LBE5:
  76              		.loc 1 250 3 view .LVU14
 251:Core/Src/main.c **** 
 252:Core/Src/main.c ****   /*Configure GPIO pin : PC14 */
 253:Core/Src/main.c ****   GPIO_InitStruct.Pin = GPIO_PIN_14;
  77              		.loc 1 253 3 view .LVU15
  78              		.loc 1 253 23 is_stmt 0 view .LVU16
  79 0030 8023     		movs	r3, #128
  80 0032 DB01     		lsls	r3, r3, #7
  81 0034 0393     		str	r3, [sp, #12]
 254:Core/Src/main.c ****   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  82              		.loc 1 254 3 is_stmt 1 view .LVU17
 255:Core/Src/main.c ****   GPIO_InitStruct.Pull = GPIO_PULLDOWN;
  83              		.loc 1 255 3 view .LVU18
  84              		.loc 1 255 24 is_stmt 0 view .LVU19
  85 0036 0223     		movs	r3, #2
  86 0038 0593     		str	r3, [sp, #20]
 256:Core/Src/main.c ****   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  87              		.loc 1 256 3 is_stmt 1 view .LVU20
ARM GAS  /tmp/ccCxCgQe.s 			page 7


  88 003a 03A9     		add	r1, sp, #12
  89 003c 0348     		ldr	r0, .L2+4
  90 003e FFF7FEFF 		bl	HAL_GPIO_Init
  91              	.LVL1:
 257:Core/Src/main.c **** 
 258:Core/Src/main.c **** }
  92              		.loc 1 258 1 is_stmt 0 view .LVU21
  93 0042 09B0     		add	sp, sp, #36
  94              		@ sp needed
  95 0044 00BD     		pop	{pc}
  96              	.L3:
  97 0046 C046     		.align	2
  98              	.L2:
  99 0048 00100240 		.word	1073876992
 100 004c 00080050 		.word	1342179328
 101              		.cfi_endproc
 102              	.LFE300:
 104              		.section	.text.Error_Handler,"ax",%progbits
 105              		.align	1
 106              		.global	Error_Handler
 107              		.syntax unified
 108              		.code	16
 109              		.thumb_func
 110              		.fpu softvfp
 112              	Error_Handler:
 113              	.LFB301:
 259:Core/Src/main.c **** 
 260:Core/Src/main.c **** /* USER CODE BEGIN 4 */
 261:Core/Src/main.c **** 
 262:Core/Src/main.c **** /* USER CODE END 4 */
 263:Core/Src/main.c **** 
 264:Core/Src/main.c **** /**
 265:Core/Src/main.c ****   * @brief  This function is executed in case of error occurrence.
 266:Core/Src/main.c ****   * @retval None
 267:Core/Src/main.c ****   */
 268:Core/Src/main.c **** void Error_Handler(void)
 269:Core/Src/main.c **** {
 114              		.loc 1 269 1 is_stmt 1 view -0
 115              		.cfi_startproc
 116              		@ Volatile: function does not return.
 117              		@ args = 0, pretend = 0, frame = 0
 118              		@ frame_needed = 0, uses_anonymous_args = 0
 119              		@ link register save eliminated.
 270:Core/Src/main.c ****   /* USER CODE BEGIN Error_Handler_Debug */
 271:Core/Src/main.c ****   /* User can add his own implementation to report the HAL error return state */
 272:Core/Src/main.c ****   __disable_irq();
 120              		.loc 1 272 3 view .LVU23
 121              	.LBB6:
 122              	.LBI6:
 123              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
ARM GAS  /tmp/ccCxCgQe.s 			page 8


   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
ARM GAS  /tmp/ccCxCgQe.s 			page 9


  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/ccCxCgQe.s 			page 10


 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
ARM GAS  /tmp/ccCxCgQe.s 			page 11


 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 124              		.loc 2 207 27 view .LVU24
 125              	.LBB7:
 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 126              		.loc 2 209 3 view .LVU25
 127              		.syntax divided
 128              	@ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 129 0000 72B6     		cpsid i
 130              	@ 0 "" 2
 131              		.thumb
 132              		.syntax unified
 133              	.L5:
 134              	.LBE7:
 135              	.LBE6:
 273:Core/Src/main.c ****   while (1)
 136              		.loc 1 273 3 discriminator 1 view .LVU26
 274:Core/Src/main.c ****   {
 275:Core/Src/main.c ****   }
 137              		.loc 1 275 3 discriminator 1 view .LVU27
 273:Core/Src/main.c ****   while (1)
 138              		.loc 1 273 9 discriminator 1 view .LVU28
 139 0002 FEE7     		b	.L5
 140              		.cfi_endproc
 141              	.LFE301:
 143              		.section	.text.MX_I2C2_Init,"ax",%progbits
 144              		.align	1
 145              		.syntax unified
 146              		.code	16
ARM GAS  /tmp/ccCxCgQe.s 			page 12


 147              		.thumb_func
 148              		.fpu softvfp
 150              	MX_I2C2_Init:
 151              	.LFB299:
 199:Core/Src/main.c **** 
 152              		.loc 1 199 1 view -0
 153              		.cfi_startproc
 154              		@ args = 0, pretend = 0, frame = 0
 155              		@ frame_needed = 0, uses_anonymous_args = 0
 156 0000 10B5     		push	{r4, lr}
 157              	.LCFI2:
 158              		.cfi_def_cfa_offset 8
 159              		.cfi_offset 4, -8
 160              		.cfi_offset 14, -4
 208:Core/Src/main.c ****   hi2c2.Init.Timing = 0x00303D5B;
 161              		.loc 1 208 3 view .LVU30
 208:Core/Src/main.c ****   hi2c2.Init.Timing = 0x00303D5B;
 162              		.loc 1 208 18 is_stmt 0 view .LVU31
 163 0002 1248     		ldr	r0, .L13
 164 0004 124B     		ldr	r3, .L13+4
 165 0006 0360     		str	r3, [r0]
 209:Core/Src/main.c ****   hi2c2.Init.OwnAddress1 = 0;
 166              		.loc 1 209 3 is_stmt 1 view .LVU32
 209:Core/Src/main.c ****   hi2c2.Init.OwnAddress1 = 0;
 167              		.loc 1 209 21 is_stmt 0 view .LVU33
 168 0008 124B     		ldr	r3, .L13+8
 169 000a 4360     		str	r3, [r0, #4]
 210:Core/Src/main.c ****   hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 170              		.loc 1 210 3 is_stmt 1 view .LVU34
 210:Core/Src/main.c ****   hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 171              		.loc 1 210 26 is_stmt 0 view .LVU35
 172 000c 0023     		movs	r3, #0
 173 000e 8360     		str	r3, [r0, #8]
 211:Core/Src/main.c ****   hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 174              		.loc 1 211 3 is_stmt 1 view .LVU36
 211:Core/Src/main.c ****   hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 175              		.loc 1 211 29 is_stmt 0 view .LVU37
 176 0010 0122     		movs	r2, #1
 177 0012 C260     		str	r2, [r0, #12]
 212:Core/Src/main.c ****   hi2c2.Init.OwnAddress2 = 0;
 178              		.loc 1 212 3 is_stmt 1 view .LVU38
 212:Core/Src/main.c ****   hi2c2.Init.OwnAddress2 = 0;
 179              		.loc 1 212 30 is_stmt 0 view .LVU39
 180 0014 0361     		str	r3, [r0, #16]
 213:Core/Src/main.c ****   hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
 181              		.loc 1 213 3 is_stmt 1 view .LVU40
 213:Core/Src/main.c ****   hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
 182              		.loc 1 213 26 is_stmt 0 view .LVU41
 183 0016 4361     		str	r3, [r0, #20]
 214:Core/Src/main.c ****   hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 184              		.loc 1 214 3 is_stmt 1 view .LVU42
 214:Core/Src/main.c ****   hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 185              		.loc 1 214 31 is_stmt 0 view .LVU43
 186 0018 8361     		str	r3, [r0, #24]
 215:Core/Src/main.c ****   hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 187              		.loc 1 215 3 is_stmt 1 view .LVU44
 215:Core/Src/main.c ****   hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
ARM GAS  /tmp/ccCxCgQe.s 			page 13


 188              		.loc 1 215 30 is_stmt 0 view .LVU45
 189 001a C361     		str	r3, [r0, #28]
 216:Core/Src/main.c ****   if (HAL_I2C_Init(&hi2c2) != HAL_OK)
 190              		.loc 1 216 3 is_stmt 1 view .LVU46
 216:Core/Src/main.c ****   if (HAL_I2C_Init(&hi2c2) != HAL_OK)
 191              		.loc 1 216 28 is_stmt 0 view .LVU47
 192 001c 0362     		str	r3, [r0, #32]
 217:Core/Src/main.c ****   {
 193              		.loc 1 217 3 is_stmt 1 view .LVU48
 217:Core/Src/main.c ****   {
 194              		.loc 1 217 7 is_stmt 0 view .LVU49
 195 001e FFF7FEFF 		bl	HAL_I2C_Init
 196              	.LVL2:
 217:Core/Src/main.c ****   {
 197              		.loc 1 217 6 view .LVU50
 198 0022 0028     		cmp	r0, #0
 199 0024 0CD1     		bne	.L10
 223:Core/Src/main.c ****   {
 200              		.loc 1 223 3 is_stmt 1 view .LVU51
 223:Core/Src/main.c ****   {
 201              		.loc 1 223 7 is_stmt 0 view .LVU52
 202 0026 0021     		movs	r1, #0
 203 0028 0848     		ldr	r0, .L13
 204 002a FFF7FEFF 		bl	HAL_I2CEx_ConfigAnalogFilter
 205              	.LVL3:
 223:Core/Src/main.c ****   {
 206              		.loc 1 223 6 view .LVU53
 207 002e 0028     		cmp	r0, #0
 208 0030 08D1     		bne	.L11
 229:Core/Src/main.c ****   {
 209              		.loc 1 229 3 is_stmt 1 view .LVU54
 229:Core/Src/main.c ****   {
 210              		.loc 1 229 7 is_stmt 0 view .LVU55
 211 0032 0021     		movs	r1, #0
 212 0034 0548     		ldr	r0, .L13
 213 0036 FFF7FEFF 		bl	HAL_I2CEx_ConfigDigitalFilter
 214              	.LVL4:
 229:Core/Src/main.c ****   {
 215              		.loc 1 229 6 view .LVU56
 216 003a 0028     		cmp	r0, #0
 217 003c 04D1     		bne	.L12
 237:Core/Src/main.c **** 
 218              		.loc 1 237 1 view .LVU57
 219              		@ sp needed
 220 003e 10BD     		pop	{r4, pc}
 221              	.L10:
 219:Core/Src/main.c ****   }
 222              		.loc 1 219 5 is_stmt 1 view .LVU58
 223 0040 FFF7FEFF 		bl	Error_Handler
 224              	.LVL5:
 225              	.L11:
 225:Core/Src/main.c ****   }
 226              		.loc 1 225 5 view .LVU59
 227 0044 FFF7FEFF 		bl	Error_Handler
 228              	.LVL6:
 229              	.L12:
 231:Core/Src/main.c ****   }
ARM GAS  /tmp/ccCxCgQe.s 			page 14


 230              		.loc 1 231 5 view .LVU60
 231 0048 FFF7FEFF 		bl	Error_Handler
 232              	.LVL7:
 233              	.L14:
 234              		.align	2
 235              	.L13:
 236 004c 00000000 		.word	.LANCHOR0
 237 0050 00580040 		.word	1073764352
 238 0054 5B3D3000 		.word	3161435
 239              		.cfi_endproc
 240              	.LFE299:
 242              		.section	.text.SystemClock_Config,"ax",%progbits
 243              		.align	1
 244              		.global	SystemClock_Config
 245              		.syntax unified
 246              		.code	16
 247              		.thumb_func
 248              		.fpu softvfp
 250              	SystemClock_Config:
 251              	.LFB298:
 160:Core/Src/main.c ****   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 252              		.loc 1 160 1 view -0
 253              		.cfi_startproc
 254              		@ args = 0, pretend = 0, frame = 72
 255              		@ frame_needed = 0, uses_anonymous_args = 0
 256 0000 00B5     		push	{lr}
 257              	.LCFI3:
 258              		.cfi_def_cfa_offset 4
 259              		.cfi_offset 14, -4
 260 0002 93B0     		sub	sp, sp, #76
 261              	.LCFI4:
 262              		.cfi_def_cfa_offset 80
 161:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 263              		.loc 1 161 3 view .LVU62
 161:Core/Src/main.c ****   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 264              		.loc 1 161 22 is_stmt 0 view .LVU63
 265 0004 3822     		movs	r2, #56
 266 0006 0021     		movs	r1, #0
 267 0008 04A8     		add	r0, sp, #16
 268 000a FFF7FEFF 		bl	memset
 269              	.LVL8:
 162:Core/Src/main.c **** 
 270              		.loc 1 162 3 is_stmt 1 view .LVU64
 162:Core/Src/main.c **** 
 271              		.loc 1 162 22 is_stmt 0 view .LVU65
 272 000e 1022     		movs	r2, #16
 273 0010 0021     		movs	r1, #0
 274 0012 6846     		mov	r0, sp
 275 0014 FFF7FEFF 		bl	memset
 276              	.LVL9:
 166:Core/Src/main.c ****   /** Initializes the RCC Oscillators according to the specified parameters
 277              		.loc 1 166 3 is_stmt 1 view .LVU66
 278 0018 8020     		movs	r0, #128
 279 001a 8000     		lsls	r0, r0, #2
 280 001c FFF7FEFF 		bl	HAL_PWREx_ControlVoltageScaling
 281              	.LVL10:
 170:Core/Src/main.c ****   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
ARM GAS  /tmp/ccCxCgQe.s 			page 15


 282              		.loc 1 170 3 view .LVU67
 170:Core/Src/main.c ****   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 283              		.loc 1 170 36 is_stmt 0 view .LVU68
 284 0020 0223     		movs	r3, #2
 285 0022 0493     		str	r3, [sp, #16]
 171:Core/Src/main.c ****   RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
 286              		.loc 1 171 3 is_stmt 1 view .LVU69
 171:Core/Src/main.c ****   RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
 287              		.loc 1 171 30 is_stmt 0 view .LVU70
 288 0024 FE33     		adds	r3, r3, #254
 289 0026 0793     		str	r3, [sp, #28]
 172:Core/Src/main.c ****   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 290              		.loc 1 172 3 is_stmt 1 view .LVU71
 172:Core/Src/main.c ****   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 291              		.loc 1 172 28 is_stmt 0 view .LVU72
 292 0028 0023     		movs	r3, #0
 293 002a 0893     		str	r3, [sp, #32]
 173:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
 294              		.loc 1 173 3 is_stmt 1 view .LVU73
 173:Core/Src/main.c ****   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
 295              		.loc 1 173 41 is_stmt 0 view .LVU74
 296 002c 4022     		movs	r2, #64
 297 002e 0992     		str	r2, [sp, #36]
 174:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 298              		.loc 1 174 3 is_stmt 1 view .LVU75
 174:Core/Src/main.c ****   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 299              		.loc 1 174 34 is_stmt 0 view .LVU76
 300 0030 0B93     		str	r3, [sp, #44]
 175:Core/Src/main.c ****   {
 301              		.loc 1 175 3 is_stmt 1 view .LVU77
 175:Core/Src/main.c ****   {
 302              		.loc 1 175 7 is_stmt 0 view .LVU78
 303 0032 04A8     		add	r0, sp, #16
 304 0034 FFF7FEFF 		bl	HAL_RCC_OscConfig
 305              	.LVL11:
 175:Core/Src/main.c ****   {
 306              		.loc 1 175 6 view .LVU79
 307 0038 0028     		cmp	r0, #0
 308 003a 0DD1     		bne	.L18
 181:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1;
 309              		.loc 1 181 3 is_stmt 1 view .LVU80
 181:Core/Src/main.c ****                               |RCC_CLOCKTYPE_PCLK1;
 310              		.loc 1 181 31 is_stmt 0 view .LVU81
 311 003c 0723     		movs	r3, #7
 312 003e 0093     		str	r3, [sp]
 183:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 313              		.loc 1 183 3 is_stmt 1 view .LVU82
 183:Core/Src/main.c ****   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 314              		.loc 1 183 34 is_stmt 0 view .LVU83
 315 0040 0023     		movs	r3, #0
 316 0042 0193     		str	r3, [sp, #4]
 184:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 317              		.loc 1 184 3 is_stmt 1 view .LVU84
 184:Core/Src/main.c ****   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 318              		.loc 1 184 35 is_stmt 0 view .LVU85
 319 0044 0293     		str	r3, [sp, #8]
 185:Core/Src/main.c **** 
ARM GAS  /tmp/ccCxCgQe.s 			page 16


 320              		.loc 1 185 3 is_stmt 1 view .LVU86
 185:Core/Src/main.c **** 
 321              		.loc 1 185 36 is_stmt 0 view .LVU87
 322 0046 0393     		str	r3, [sp, #12]
 187:Core/Src/main.c ****   {
 323              		.loc 1 187 3 is_stmt 1 view .LVU88
 187:Core/Src/main.c ****   {
 324              		.loc 1 187 7 is_stmt 0 view .LVU89
 325 0048 0021     		movs	r1, #0
 326 004a 6846     		mov	r0, sp
 327 004c FFF7FEFF 		bl	HAL_RCC_ClockConfig
 328              	.LVL12:
 187:Core/Src/main.c ****   {
 329              		.loc 1 187 6 view .LVU90
 330 0050 0028     		cmp	r0, #0
 331 0052 03D1     		bne	.L19
 191:Core/Src/main.c **** 
 332              		.loc 1 191 1 view .LVU91
 333 0054 13B0     		add	sp, sp, #76
 334              		@ sp needed
 335 0056 00BD     		pop	{pc}
 336              	.L18:
 177:Core/Src/main.c ****   }
 337              		.loc 1 177 5 is_stmt 1 view .LVU92
 338 0058 FFF7FEFF 		bl	Error_Handler
 339              	.LVL13:
 340              	.L19:
 189:Core/Src/main.c ****   }
 341              		.loc 1 189 5 view .LVU93
 342 005c FFF7FEFF 		bl	Error_Handler
 343              	.LVL14:
 344              		.cfi_endproc
 345              	.LFE298:
 347              		.section	.text.main,"ax",%progbits
 348              		.align	1
 349              		.global	main
 350              		.syntax unified
 351              		.code	16
 352              		.thumb_func
 353              		.fpu softvfp
 355              	main:
 356              	.LFB297:
  69:Core/Src/main.c ****   /* USER CODE BEGIN 1 */
 357              		.loc 1 69 1 view -0
 358              		.cfi_startproc
 359              		@ Volatile: function does not return.
 360              		@ args = 0, pretend = 0, frame = 0
 361              		@ frame_needed = 0, uses_anonymous_args = 0
 362 0000 10B5     		push	{r4, lr}
 363              	.LCFI5:
 364              		.cfi_def_cfa_offset 8
 365              		.cfi_offset 4, -8
 366              		.cfi_offset 14, -4
  77:Core/Src/main.c **** 
 367              		.loc 1 77 3 view .LVU95
 368 0002 FFF7FEFF 		bl	HAL_Init
 369              	.LVL15:
ARM GAS  /tmp/ccCxCgQe.s 			page 17


  84:Core/Src/main.c **** 
 370              		.loc 1 84 3 view .LVU96
 371 0006 FFF7FEFF 		bl	SystemClock_Config
 372              	.LVL16:
  91:Core/Src/main.c ****   MX_I2C2_Init();
 373              		.loc 1 91 3 view .LVU97
 374 000a FFF7FEFF 		bl	MX_GPIO_Init
 375              	.LVL17:
  92:Core/Src/main.c ****   /* USER CODE BEGIN 2 */
 376              		.loc 1 92 3 view .LVU98
 377 000e FFF7FEFF 		bl	MX_I2C2_Init
 378              	.LVL18:
  94:Core/Src/main.c **** 	HAL_Delay(100);
 379              		.loc 1 94 4 view .LVU99
  94:Core/Src/main.c **** 	HAL_Delay(100);
 380              		.loc 1 94 14 is_stmt 0 view .LVU100
 381 0012 174C     		ldr	r4, .L24
 382 0014 174B     		ldr	r3, .L24+4
 383 0016 2360     		str	r3, [r4]
  95:Core/Src/main.c **** 	si5351_Init();
 384              		.loc 1 95 2 is_stmt 1 view .LVU101
 385 0018 6420     		movs	r0, #100
 386 001a FFF7FEFF 		bl	HAL_Delay
 387              	.LVL19:
  96:Core/Src/main.c **** 	HAL_Delay(500);
 388              		.loc 1 96 2 view .LVU102
 389 001e FFF7FEFF 		bl	si5351_Init
 390              	.LVL20:
  97:Core/Src/main.c **** 	CalcRegisters(frequenza);
 391              		.loc 1 97 2 view .LVU103
 392 0022 FA20     		movs	r0, #250
 393 0024 4000     		lsls	r0, r0, #1
 394 0026 FFF7FEFF 		bl	HAL_Delay
 395              	.LVL21:
  98:Core/Src/main.c ****   /* USER CODE END 2 */
 396              		.loc 1 98 2 view .LVU104
 397 002a 2068     		ldr	r0, [r4]
 398 002c FFF7FEFF 		bl	CalcRegisters
 399              	.LVL22:
 400 0030 09E0     		b	.L23
 401              	.L22:
 136:Core/Src/main.c **** 	}
 402              		.loc 1 136 3 view .LVU105
 403 0032 0F4B     		ldr	r3, .L24
 404 0034 1868     		ldr	r0, [r3]
 405 0036 FFF7FEFF 		bl	CalcRegisters
 406              	.LVL23:
 407              	.L21:
 148:Core/Src/main.c **** 	HAL_Delay(100);
 408              		.loc 1 148 2 view .LVU106
 409 003a FF20     		movs	r0, #255
 410 003c FFF7FEFF 		bl	si5351_enableOutputs
 411              	.LVL24:
 149:Core/Src/main.c **** 
 412              		.loc 1 149 2 view .LVU107
 413 0040 6420     		movs	r0, #100
 414 0042 FFF7FEFF 		bl	HAL_Delay
ARM GAS  /tmp/ccCxCgQe.s 			page 18


 415              	.LVL25:
 103:Core/Src/main.c ****   {
 416              		.loc 1 103 9 view .LVU108
 417              	.L23:
 103:Core/Src/main.c ****   {
 418              		.loc 1 103 3 view .LVU109
 133:Core/Src/main.c **** 		frequenza += 9000;
 419              		.loc 1 133 2 view .LVU110
 133:Core/Src/main.c **** 		frequenza += 9000;
 420              		.loc 1 133 5 is_stmt 0 view .LVU111
 421 0046 8021     		movs	r1, #128
 422 0048 C901     		lsls	r1, r1, #7
 423 004a 0B48     		ldr	r0, .L24+8
 424 004c FFF7FEFF 		bl	HAL_GPIO_ReadPin
 425              	.LVL26:
 133:Core/Src/main.c **** 		frequenza += 9000;
 426              		.loc 1 133 4 view .LVU112
 427 0050 0028     		cmp	r0, #0
 428 0052 F2D0     		beq	.L21
 134:Core/Src/main.c **** 		if(frequenza > 1800000) frequenza = 585000;
 429              		.loc 1 134 3 is_stmt 1 view .LVU113
 134:Core/Src/main.c **** 		if(frequenza > 1800000) frequenza = 585000;
 430              		.loc 1 134 13 is_stmt 0 view .LVU114
 431 0054 064A     		ldr	r2, .L24
 432 0056 1368     		ldr	r3, [r2]
 433 0058 0849     		ldr	r1, .L24+12
 434 005a 8C46     		mov	ip, r1
 435 005c 6344     		add	r3, r3, ip
 436 005e 1360     		str	r3, [r2]
 135:Core/Src/main.c **** 		CalcRegisters(frequenza);
 437              		.loc 1 135 3 is_stmt 1 view .LVU115
 135:Core/Src/main.c **** 		CalcRegisters(frequenza);
 438              		.loc 1 135 5 is_stmt 0 view .LVU116
 439 0060 074A     		ldr	r2, .L24+16
 440 0062 9342     		cmp	r3, r2
 441 0064 E5D9     		bls	.L22
 135:Core/Src/main.c **** 		CalcRegisters(frequenza);
 442              		.loc 1 135 27 is_stmt 1 discriminator 1 view .LVU117
 135:Core/Src/main.c **** 		CalcRegisters(frequenza);
 443              		.loc 1 135 37 is_stmt 0 discriminator 1 view .LVU118
 444 0066 024B     		ldr	r3, .L24
 445 0068 064A     		ldr	r2, .L24+20
 446 006a 1A60     		str	r2, [r3]
 447 006c E1E7     		b	.L22
 448              	.L25:
 449 006e C046     		.align	2
 450              	.L24:
 451 0070 00000000 		.word	.LANCHOR1
 452 0074 98BC1400 		.word	1359000
 453 0078 00080050 		.word	1342179328
 454 007c 28230000 		.word	9000
 455 0080 40771B00 		.word	1800000
 456 0084 28ED0800 		.word	585000
 457              		.cfi_endproc
 458              	.LFE297:
 460              		.section	.text.assert_failed,"ax",%progbits
 461              		.align	1
ARM GAS  /tmp/ccCxCgQe.s 			page 19


 462              		.global	assert_failed
 463              		.syntax unified
 464              		.code	16
 465              		.thumb_func
 466              		.fpu softvfp
 468              	assert_failed:
 469              	.LVL27:
 470              	.LFB302:
 276:Core/Src/main.c ****   /* USER CODE END Error_Handler_Debug */
 277:Core/Src/main.c **** }
 278:Core/Src/main.c **** 
 279:Core/Src/main.c **** #ifdef  USE_FULL_ASSERT
 280:Core/Src/main.c **** /**
 281:Core/Src/main.c ****   * @brief  Reports the name of the source file and the source line number
 282:Core/Src/main.c ****   *         where the assert_param error has occurred.
 283:Core/Src/main.c ****   * @param  file: pointer to the source file name
 284:Core/Src/main.c ****   * @param  line: assert_param error line source number
 285:Core/Src/main.c ****   * @retval None
 286:Core/Src/main.c ****   */
 287:Core/Src/main.c **** void assert_failed(uint8_t *file, uint32_t line)
 288:Core/Src/main.c **** {
 471              		.loc 1 288 1 is_stmt 1 view -0
 472              		.cfi_startproc
 473              		@ args = 0, pretend = 0, frame = 0
 474              		@ frame_needed = 0, uses_anonymous_args = 0
 475              		@ link register save eliminated.
 289:Core/Src/main.c ****   /* USER CODE BEGIN 6 */
 290:Core/Src/main.c ****   /* User can add his own implementation to report the file name and line number,
 291:Core/Src/main.c ****      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
 292:Core/Src/main.c ****   /* USER CODE END 6 */
 293:Core/Src/main.c **** }
 476              		.loc 1 293 1 view .LVU120
 477              		@ sp needed
 478 0000 7047     		bx	lr
 479              		.cfi_endproc
 480              	.LFE302:
 482              		.global	frequenza
 483              		.global	hi2c2
 484              		.section	.bss.frequenza,"aw",%nobits
 485              		.align	2
 486              		.set	.LANCHOR1,. + 0
 489              	frequenza:
 490 0000 00000000 		.space	4
 491              		.section	.bss.hi2c2,"aw",%nobits
 492              		.align	2
 493              		.set	.LANCHOR0,. + 0
 496              	hi2c2:
 497 0000 00000000 		.space	76
 497      00000000 
 497      00000000 
 497      00000000 
 497      00000000 
 498              		.text
 499              	.Letext0:
 500              		.file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
 501              		.file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h"
 502              		.file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h"
ARM GAS  /tmp/ccCxCgQe.s 			page 20


 503              		.file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h"
 504              		.file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h"
 505              		.file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h"
 506              		.file 9 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h"
 507              		.file 10 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h"
 508              		.file 11 "Core/Inc/si5351.h"
 509              		.file 12 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h"
 510              		.file 13 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h"
 511              		.file 14 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h"
 512              		.file 15 "<built-in>"
ARM GAS  /tmp/ccCxCgQe.s 			page 21


DEFINED SYMBOLS
                            *ABS*:0000000000000000 main.c
     /tmp/ccCxCgQe.s:16     .text.MX_GPIO_Init:0000000000000000 $t
     /tmp/ccCxCgQe.s:23     .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init
     /tmp/ccCxCgQe.s:99     .text.MX_GPIO_Init:0000000000000048 $d
     /tmp/ccCxCgQe.s:105    .text.Error_Handler:0000000000000000 $t
     /tmp/ccCxCgQe.s:112    .text.Error_Handler:0000000000000000 Error_Handler
     /tmp/ccCxCgQe.s:144    .text.MX_I2C2_Init:0000000000000000 $t
     /tmp/ccCxCgQe.s:150    .text.MX_I2C2_Init:0000000000000000 MX_I2C2_Init
     /tmp/ccCxCgQe.s:236    .text.MX_I2C2_Init:000000000000004c $d
     /tmp/ccCxCgQe.s:243    .text.SystemClock_Config:0000000000000000 $t
     /tmp/ccCxCgQe.s:250    .text.SystemClock_Config:0000000000000000 SystemClock_Config
     /tmp/ccCxCgQe.s:348    .text.main:0000000000000000 $t
     /tmp/ccCxCgQe.s:355    .text.main:0000000000000000 main
     /tmp/ccCxCgQe.s:451    .text.main:0000000000000070 $d
     /tmp/ccCxCgQe.s:461    .text.assert_failed:0000000000000000 $t
     /tmp/ccCxCgQe.s:468    .text.assert_failed:0000000000000000 assert_failed
     /tmp/ccCxCgQe.s:489    .bss.frequenza:0000000000000000 frequenza
     /tmp/ccCxCgQe.s:496    .bss.hi2c2:0000000000000000 hi2c2
     /tmp/ccCxCgQe.s:485    .bss.frequenza:0000000000000000 $d
     /tmp/ccCxCgQe.s:492    .bss.hi2c2:0000000000000000 $d

UNDEFINED SYMBOLS
memset
HAL_GPIO_Init
HAL_I2C_Init
HAL_I2CEx_ConfigAnalogFilter
HAL_I2CEx_ConfigDigitalFilter
HAL_PWREx_ControlVoltageScaling
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
HAL_Init
HAL_Delay
si5351_Init
CalcRegisters
si5351_enableOutputs
HAL_GPIO_ReadPin
