ARM GAS  /tmp/ccDIilRR.s 			page 1


   1              		.cpu cortex-m0plus
   2              		.eabi_attribute 20, 1
   3              		.eabi_attribute 21, 1
   4              		.eabi_attribute 23, 3
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 1
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"stm32g0xx_hal_pwr.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.section	.text.HAL_PWR_DeInit,"ax",%progbits
  16              		.align	1
  17              		.global	HAL_PWR_DeInit
  18              		.arch armv6s-m
  19              		.syntax unified
  20              		.code	16
  21              		.thumb_func
  22              		.fpu softvfp
  24              	HAL_PWR_DeInit:
  25              	.LFB297:
  26              		.file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c"
   1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
   2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   ******************************************************************************
   3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @file    stm32g0xx_hal_pwr.c
   4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @author  MCD Application Team
   5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief   PWR HAL module driver.
   6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *          This file provides firmware functions to manage the following
   7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *          functionalities of the Power Controller (PWR) peripheral:
   8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           + Initialization/de-initialization functions
   9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           + Peripheral Control functions
  10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *
  11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   ******************************************************************************
  12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @attention
  13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *
  14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
  15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * All rights reserved.</center></h2>
  16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *
  17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * This software component is licensed by ST under BSD 3-Clause license,
  18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * the "License"; You may not use this file except in compliance with the
  19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * License. You may obtain a copy of the License at:
  20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                        opensource.org/licenses/BSD-3-Clause
  21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *
  22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   ******************************************************************************
  23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
  26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #include "stm32g0xx_hal.h"
  27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup STM32G0xx_HAL_Driver
  29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @{
  30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR
ARM GAS  /tmp/ccDIilRR.s 			page 2


  33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @{
  34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
  37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
  39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
  40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @defgroup PWR_Private_Defines PWR Private Defines
  41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @{
  42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
  45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @}
  46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
  49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
  50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
  51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Exported functions --------------------------------------------------------*/
  52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions  PWR Exported Functions
  53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @{
  54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
  57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Initialization and de-initialization functions
  58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *
  59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @verbatim
  60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****  ===============================================================================
  61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****               ##### Initialization and de-initialization functions #####
  62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****  ===============================================================================
  63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
  64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @endverbatim
  66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @{
  67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
  70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
  71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****             values.
  72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
  73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
  75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
  27              		.loc 1 75 1 view -0
  28              		.cfi_startproc
  29              		@ args = 0, pretend = 0, frame = 0
  30              		@ frame_needed = 0, uses_anonymous_args = 0
  31              		@ link register save eliminated.
  76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   __HAL_RCC_PWR_FORCE_RESET();
  32              		.loc 1 76 3 view .LVU1
  33 0000 054B     		ldr	r3, .L2
  34 0002 D96A     		ldr	r1, [r3, #44]
  35 0004 8022     		movs	r2, #128
  36 0006 5205     		lsls	r2, r2, #21
  37 0008 0A43     		orrs	r2, r1
  38 000a DA62     		str	r2, [r3, #44]
  77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   __HAL_RCC_PWR_RELEASE_RESET();
ARM GAS  /tmp/ccDIilRR.s 			page 3


  39              		.loc 1 77 3 view .LVU2
  40 000c DA6A     		ldr	r2, [r3, #44]
  41 000e 0349     		ldr	r1, .L2+4
  42 0010 0A40     		ands	r2, r1
  43 0012 DA62     		str	r2, [r3, #44]
  78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
  44              		.loc 1 78 1 is_stmt 0 view .LVU3
  45              		@ sp needed
  46 0014 7047     		bx	lr
  47              	.L3:
  48 0016 C046     		.align	2
  49              	.L2:
  50 0018 00100240 		.word	1073876992
  51 001c FFFFFFEF 		.word	-268435457
  52              		.cfi_endproc
  53              	.LFE297:
  55              		.section	.text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
  56              		.align	1
  57              		.global	HAL_PWR_EnableBkUpAccess
  58              		.syntax unified
  59              		.code	16
  60              		.thumb_func
  61              		.fpu softvfp
  63              	HAL_PWR_EnableBkUpAccess:
  64              	.LFB298:
  79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
  81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @}
  82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
  83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group2  Peripheral Control functions
  85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *  @brief Low Power modes configuration functions
  86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *
  87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @verbatim
  88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****  ===============================================================================
  90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                  ##### Peripheral Control functions #####
  91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****  ===============================================================================
  92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
  93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
  94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     *** WakeUp pin configuration ***
  95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     ================================
  96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
  97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) WakeUp pins are used to wakeup the system from Standby mode or
  98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           Shutdown mode. WakeUp pins polarity can be set to configure event
  99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           detection on high level (rising edge) or low level (falling edge).
 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     *** Low Power mode configuration ***
 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     =====================================
 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       The devices feature 7 low-power modes:
 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Low-power run mode: core and peripherals are running at low frequency.
 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           Regulator is in low power mode.
 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           regulator is main mode.
 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running
 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           and regulator in low power mode.
ARM GAS  /tmp/ccDIilRR.s 			page 4


 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****            main mode.
 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           off, low power regulator on.
 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is
 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           disable.
 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Shutdown mode: all clocks are stopped except LSE, regulator is
 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           disable.
 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    *** Low-power run mode ***
 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    ==========================
 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Entry: (from main run mode)
 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after
 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                having decreased the system clock below 2 MHz.
 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Exit:
 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) clear LPR bit then wait for REGLPF bit to be reset with
 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                HAL_PWREx_DisableLowPowerRunMode() API. Only then can the
 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                system clock frequency be increased above 2 MHz.
 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    *** Sleep mode / Low-power sleep mode ***
 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    =========================================
 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Entry:
 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           The Sleep & Low-power Sleep modes are entered through
 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator
 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           is forced to low-power mode and if exit is interrupt or event
 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           triggered.
 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low
 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                power mode). In this case, the system clock frequency must have
 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                been decreased below 2 MHz beforehand.
 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) WFI Exit:
 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****         (++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) WFE Exit:
 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****         (++) Any wakeup event if cortex is configured with SEVONPEND = 0
 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****         (++) Interrupt even when disabled in NVIC if cortex is configured with
 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****              SEVONPEND = 1
 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]  When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event,
 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           the MCU is in Low-power Run mode.
 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    *** Stop 0 & Stop 1 modes ***
 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    =============================
 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Entry:
 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           The Stop modes are entered through the following APIs:
 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) HAL_PWR_EnterSTOPMode() with following settings:
 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****               (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****               (+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode.
 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) WFI Exit:
 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) Any EXTI line (internal or external) configured in interrupt mode
 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                with corresponding interrupt enable in NVIC
ARM GAS  /tmp/ccDIilRR.s 			page 5


 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) WFE Exit:
 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) Any EXTI line (internal or external) configured in event mode if
 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                cortex is configured with SEVONPEND = 0
 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) Any EXTI line configured in interrupt mode (even if the
 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                corresponding EXTI Interrupt vector is disabled in the NVIC) if
 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                cortex is configured with SEVONPEND = 0. The interrupt source can
 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                be external interrupts or peripherals with wakeup capability.
 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]  When exiting Stop, the MCU is either in Run mode or in Low-power Run mode
 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           depending on the LPR bit setting.
 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    *** Standby mode ***
 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    ====================
 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..] In Standby mode, it is possible to keep backup SRAM content (defined as
 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          full SRAM) keeping low power regulator on. This is achievable by setting
 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases
 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          power consumption.
 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          Its also possible to define I/O states using APIs:
 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown &
 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          HAL_PWREx_EnablePullUpPullDownConfig
 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Entry:
 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by
 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                setting SLEEPDEEP in Cortex control register.
 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Exit:
 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                tamper event (internal & external), LSE CSS detection, reset on
 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                NRST pin, IWDG reset & BOR reset.
 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..] Exiting Standby generates a power reset: Cortex is reset and execute
 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          Reset handler vector, all registers in the Vcore domain are set to
 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG,
 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          and Standby/Shutdown modes control) are not impacted.
 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     *** Shutdown mode ***
 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****    ======================
 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..]
 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       In Shutdown mode,
 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****         voltage regulator is disabled, all clocks are off except LSE, RRS bit is
 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****         cleared. SRAM and registers contents are lost except for backup domain
 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****         registers.
 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Entry:
 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API,
 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                by setting SLEEPDEEP in Cortex control register.
 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       (+) Exit:
 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****           (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                tamper event (internal & external), LSE CSS detection, reset on
 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****                NRST pin.
 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute
 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          Reset handler vector, all registers are set to their reset value but ones
 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****          in backup domain.
 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @endverbatim
 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @{
 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Enable access to the backup domain
 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         (RTC & TAMP registers, backup registers, RCC BDCR register).
 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   After reset, the backup domain is protected against
ARM GAS  /tmp/ccDIilRR.s 			page 6


 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         possible unwanted write accesses. All RTC & TAMP registers (backup
 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         registers included) and RCC BDCR register are concerned.
 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
  65              		.loc 1 230 1 is_stmt 1 view -0
  66              		.cfi_startproc
  67              		@ args = 0, pretend = 0, frame = 0
  68              		@ frame_needed = 0, uses_anonymous_args = 0
  69              		@ link register save eliminated.
 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   SET_BIT(PWR->CR1, PWR_CR1_DBP);
  70              		.loc 1 231 3 view .LVU5
  71 0000 034A     		ldr	r2, .L5
  72 0002 1168     		ldr	r1, [r2]
  73 0004 8023     		movs	r3, #128
  74 0006 5B00     		lsls	r3, r3, #1
  75 0008 0B43     		orrs	r3, r1
  76 000a 1360     		str	r3, [r2]
 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
  77              		.loc 1 232 1 is_stmt 0 view .LVU6
  78              		@ sp needed
  79 000c 7047     		bx	lr
  80              	.L6:
  81 000e C046     		.align	2
  82              	.L5:
  83 0010 00700040 		.word	1073770496
  84              		.cfi_endproc
  85              	.LFE298:
  87              		.section	.text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
  88              		.align	1
  89              		.global	HAL_PWR_DisableBkUpAccess
  90              		.syntax unified
  91              		.code	16
  92              		.thumb_func
  93              		.fpu softvfp
  95              	HAL_PWR_DisableBkUpAccess:
  96              	.LFB299:
 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Disable access to the backup domain
 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
  97              		.loc 1 240 1 is_stmt 1 view -0
  98              		.cfi_startproc
  99              		@ args = 0, pretend = 0, frame = 0
 100              		@ frame_needed = 0, uses_anonymous_args = 0
 101              		@ link register save eliminated.
 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
 102              		.loc 1 241 3 view .LVU8
 103 0000 024A     		ldr	r2, .L8
 104 0002 1368     		ldr	r3, [r2]
 105 0004 0249     		ldr	r1, .L8+4
 106 0006 0B40     		ands	r3, r1
ARM GAS  /tmp/ccDIilRR.s 			page 7


 107 0008 1360     		str	r3, [r2]
 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 108              		.loc 1 242 1 is_stmt 0 view .LVU9
 109              		@ sp needed
 110 000a 7047     		bx	lr
 111              	.L9:
 112              		.align	2
 113              	.L8:
 114 000c 00700040 		.word	1073770496
 115 0010 FFFEFFFF 		.word	-257
 116              		.cfi_endproc
 117              	.LFE299:
 119              		.section	.text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
 120              		.align	1
 121              		.global	HAL_PWR_EnableWakeUpPin
 122              		.syntax unified
 123              		.code	16
 124              		.thumb_func
 125              		.fpu softvfp
 127              	HAL_PWR_EnableWakeUpPin:
 128              	.LVL0:
 129              	.LFB300:
 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Enable the WakeUp PINx functionality.
 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @param  WakeUpPinPolarity Specifies which Wake-Up pin to enable.
 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         This parameter can be one of the following legacy values which set
 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         the default polarity i.e. detection on high level (rising edge):
 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*),
 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                     PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         or one of the following value where the user can explicitly specify
 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         the enabled pin and the chosen polarity:
 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*)
 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*)
 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note (*) availability depends on devices
 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 130              		.loc 1 264 1 is_stmt 1 view -0
 131              		.cfi_startproc
 132              		@ args = 0, pretend = 0, frame = 0
 133              		@ frame_needed = 0, uses_anonymous_args = 0
 134              		@ link register save eliminated.
 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
 135              		.loc 1 265 3 view .LVU11
 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Specifies the Wake-Up pin polarity for the event detection
 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     (rising or falling edge) */
 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHI
 136              		.loc 1 269 3 view .LVU12
 137 0000 0549     		ldr	r1, .L11
ARM GAS  /tmp/ccDIilRR.s 			page 8


 138 0002 CA68     		ldr	r2, [r1, #12]
 139 0004 2B23     		movs	r3, #43
 140 0006 0340     		ands	r3, r0
 141 0008 9A43     		bics	r2, r3
 142 000a 000A     		lsrs	r0, r0, #8
 143              	.LVL1:
 144              		.loc 1 269 3 is_stmt 0 view .LVU13
 145 000c 1043     		orrs	r0, r2
 146 000e C860     		str	r0, [r1, #12]
 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Enable wake-up pin */
 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
 147              		.loc 1 272 3 is_stmt 1 view .LVU14
 148 0010 8A68     		ldr	r2, [r1, #8]
 149 0012 1343     		orrs	r3, r2
 150 0014 8B60     		str	r3, [r1, #8]
 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 151              		.loc 1 273 1 is_stmt 0 view .LVU15
 152              		@ sp needed
 153 0016 7047     		bx	lr
 154              	.L12:
 155              		.align	2
 156              	.L11:
 157 0018 00700040 		.word	1073770496
 158              		.cfi_endproc
 159              	.LFE300:
 161              		.section	.text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
 162              		.align	1
 163              		.global	HAL_PWR_DisableWakeUpPin
 164              		.syntax unified
 165              		.code	16
 166              		.thumb_func
 167              		.fpu softvfp
 169              	HAL_PWR_DisableWakeUpPin:
 170              	.LVL2:
 171              	.LFB301:
 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Disable the WakeUp PINx functionality.
 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @param  WakeUpPinx Specifies the Power Wake-Up pin to disable.
 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         This parameter can be one of the following values:
 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*),
 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                     PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note (*) availability depends on devices
 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 172              		.loc 1 286 1 is_stmt 1 view -0
 173              		.cfi_startproc
 174              		@ args = 0, pretend = 0, frame = 0
 175              		@ frame_needed = 0, uses_anonymous_args = 0
 176              		@ link register save eliminated.
 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
 177              		.loc 1 287 3 view .LVU17
 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
ARM GAS  /tmp/ccDIilRR.s 			page 9


 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
 178              		.loc 1 289 3 view .LVU18
 179 0000 0349     		ldr	r1, .L14
 180 0002 8B68     		ldr	r3, [r1, #8]
 181 0004 2B22     		movs	r2, #43
 182 0006 0240     		ands	r2, r0
 183 0008 9343     		bics	r3, r2
 184 000a 8B60     		str	r3, [r1, #8]
 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 185              		.loc 1 290 1 is_stmt 0 view .LVU19
 186              		@ sp needed
 187 000c 7047     		bx	lr
 188              	.L15:
 189 000e C046     		.align	2
 190              	.L14:
 191 0010 00700040 		.word	1073770496
 192              		.cfi_endproc
 193              	.LFE301:
 195              		.section	.text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
 196              		.align	1
 197              		.global	HAL_PWR_EnterSLEEPMode
 198              		.syntax unified
 199              		.code	16
 200              		.thumb_func
 201              		.fpu softvfp
 203              	HAL_PWR_EnterSLEEPMode:
 204              	.LVL3:
 205              	.LFB302:
 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Enter Sleep or Low-power Sleep mode.
 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   In Sleep/Low-power Sleep mode, all I/O pins keep the same state as
 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         in Run mode.
 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @param  Regulator Specifies the regulator state in Sleep/Low-power Sleep
 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         mode. This parameter can be one of the following values:
 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator
 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                     in low-power mode)
 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   Low-power Sleep mode is entered from Low-power Run mode only. In
 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         case Regulator parameter is set to Low Power but MCU is in Run mode,
 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         we will first enter in Low-power Run mode. Therefore, user should
 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         take care that HCLK frequency is less than 2 MHz.
 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   When exiting Low-power Sleep mode, the MCU is in Low-power Run mode.
 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         To switch back to Run mode, user must call
 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         HAL_PWREx_DisableLowPowerRunMode() API.
 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @param  SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE
 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         instruction. This parameter can be one of the following values:
 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep
 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                     mode with WFI instruction
 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *           @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep
 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                     mode with WFE instruction
 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   When WFI entry is used, tick interrupt have to be disabled if not
 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         desired as the interrupt wake up source.
 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
ARM GAS  /tmp/ccDIilRR.s 			page 10


 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 206              		.loc 1 320 1 is_stmt 1 view -0
 207              		.cfi_startproc
 208              		@ args = 0, pretend = 0, frame = 0
 209              		@ frame_needed = 0, uses_anonymous_args = 0
 210              		.loc 1 320 1 is_stmt 0 view .LVU21
 211 0000 10B5     		push	{r4, lr}
 212              	.LCFI0:
 213              		.cfi_def_cfa_offset 8
 214              		.cfi_offset 4, -8
 215              		.cfi_offset 14, -4
 216 0002 0C00     		movs	r4, r1
 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Check the parameters */
 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   assert_param(IS_PWR_REGULATOR(Regulator));
 217              		.loc 1 322 3 is_stmt 1 view .LVU22
 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
 218              		.loc 1 323 3 view .LVU23
 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Set Regulator parameter */
 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   if (Regulator != PWR_MAINREGULATOR_ON)
 219              		.loc 1 326 3 view .LVU24
 220              		.loc 1 326 6 is_stmt 0 view .LVU25
 221 0004 0028     		cmp	r0, #0
 222 0006 11D0     		beq	.L17
 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* If in run mode, first move to low-power run mode.
 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****        The system clock frequency must be below 2 MHz at this point. */
 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     if ((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u)
 223              		.loc 1 330 5 is_stmt 1 view .LVU26
 224              		.loc 1 330 13 is_stmt 0 view .LVU27
 225 0008 0E4B     		ldr	r3, .L23
 226 000a 5B69     		ldr	r3, [r3, #20]
 227              		.loc 1 330 8 view .LVU28
 228 000c 9B05     		lsls	r3, r3, #22
 229 000e 0AD5     		bpl	.L21
 230              	.LVL4:
 231              	.L18:
 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     {
 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       HAL_PWREx_EnableLowPowerRunMode();
 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     }
 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   else
 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* If in low-power run mode at this point, exit it */
 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     if ((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u)
 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     {
 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       {
 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****         return ;
 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       }
 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     }
 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Clear SLEEPDEEP bit of Cortex System Control Register */
 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 232              		.loc 1 348 3 is_stmt 1 view .LVU29
 233 0010 0D4A     		ldr	r2, .L23+4
ARM GAS  /tmp/ccDIilRR.s 			page 11


 234 0012 1369     		ldr	r3, [r2, #16]
 235 0014 0421     		movs	r1, #4
 236 0016 8B43     		bics	r3, r1
 237 0018 1361     		str	r3, [r2, #16]
 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Select SLEEP mode entry -------------------------------------------------*/
 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
 238              		.loc 1 351 3 view .LVU30
 239              		.loc 1 351 6 is_stmt 0 view .LVU31
 240 001a 012C     		cmp	r4, #1
 241 001c 0FD0     		beq	.L22
 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* Request Wait For Interrupt */
 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __WFI();
 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   else
 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* Request Wait For Event */
 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __SEV();
 242              		.loc 1 359 5 is_stmt 1 view .LVU32
 243              		.syntax divided
 244              	@ 359 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 245 001e 40BF     		sev
 246              	@ 0 "" 2
 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __WFE();
 247              		.loc 1 360 5 view .LVU33
 248              	@ 360 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 249 0020 20BF     		wfe
 250              	@ 0 "" 2
 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __WFE();
 251              		.loc 1 361 5 view .LVU34
 252              	@ 361 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 253 0022 20BF     		wfe
 254              	@ 0 "" 2
 255              		.thumb
 256              		.syntax unified
 257              	.L16:
 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 258              		.loc 1 363 1 is_stmt 0 view .LVU35
 259              		@ sp needed
 260 0024 10BD     		pop	{r4, pc}
 261              	.LVL5:
 262              	.L21:
 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     }
 263              		.loc 1 332 7 is_stmt 1 view .LVU36
 264 0026 FFF7FEFF 		bl	HAL_PWREx_EnableLowPowerRunMode
 265              	.LVL6:
 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     }
 266              		.loc 1 332 7 is_stmt 0 view .LVU37
 267 002a F1E7     		b	.L18
 268              	.LVL7:
 269              	.L17:
 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     {
 270              		.loc 1 338 5 is_stmt 1 view .LVU38
 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     {
 271              		.loc 1 338 13 is_stmt 0 view .LVU39
ARM GAS  /tmp/ccDIilRR.s 			page 12


 272 002c 054B     		ldr	r3, .L23
 273 002e 5B69     		ldr	r3, [r3, #20]
 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     {
 274              		.loc 1 338 8 view .LVU40
 275 0030 9B05     		lsls	r3, r3, #22
 276 0032 EDD5     		bpl	.L18
 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       {
 277              		.loc 1 340 7 is_stmt 1 view .LVU41
 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       {
 278              		.loc 1 340 11 is_stmt 0 view .LVU42
 279 0034 FFF7FEFF 		bl	HAL_PWREx_DisableLowPowerRunMode
 280              	.LVL8:
 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****       {
 281              		.loc 1 340 10 view .LVU43
 282 0038 0028     		cmp	r0, #0
 283 003a E9D0     		beq	.L18
 284 003c F2E7     		b	.L16
 285              	.L22:
 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 286              		.loc 1 354 5 is_stmt 1 view .LVU44
 287              		.syntax divided
 288              	@ 354 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 289 003e 30BF     		wfi
 290              	@ 0 "" 2
 291              		.thumb
 292              		.syntax unified
 293 0040 F0E7     		b	.L16
 294              	.L24:
 295 0042 C046     		.align	2
 296              	.L23:
 297 0044 00700040 		.word	1073770496
 298 0048 00ED00E0 		.word	-536810240
 299              		.cfi_endproc
 300              	.LFE302:
 302              		.section	.text.HAL_PWR_EnterSTOPMode,"ax",%progbits
 303              		.align	1
 304              		.global	HAL_PWR_EnterSTOPMode
 305              		.syntax unified
 306              		.code	16
 307              		.thumb_func
 308              		.fpu softvfp
 310              	HAL_PWR_EnterSTOPMode:
 311              	.LVL9:
 312              	.LFB303:
 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Enter Stop mode
 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         legacy code running on devices where only "Stop mode" is mentioned
 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         with main or low power regulator ON.
 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   All clocks in the VCORE domain are stopped; the PLL, the HSI and the
 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         HSE oscillators are disabled. Some peripherals with the wakeup
 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         capability can switch on the HSI to receive a frame, and switch off
 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         the HSI after receiving the frame if it is not a wakeup frame.
 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         SRAM and register contents are preserved.
ARM GAS  /tmp/ccDIilRR.s 			page 13


 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         The BOR is available.
 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         The voltage regulator can be configured either in normal (Stop 0) or
 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         low-power mode (Stop 1).
 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a
 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         wakeup event, the HSI RC oscillator is selected as system clock
 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   When the voltage regulator operates in low power mode (Stop 1),
 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         an additional startup delay is incurred when waking up. By keeping
 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         the internal regulator ON during Stop mode (Stop 0), the consumption
 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         is higher although the startup time is reduced.
 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @param  Regulator Specifies the regulator state in Stop mode
 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         This parameter can be one of the following values:
 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power
 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                                                regulator ON)
 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @param  STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or
 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         WFE instruction. This parameter can be one of the following values:
 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI
 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                                         instruction.
 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE
 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *                                         instruction.
 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 313              		.loc 1 400 1 view -0
 314              		.cfi_startproc
 315              		@ args = 0, pretend = 0, frame = 0
 316              		@ frame_needed = 0, uses_anonymous_args = 0
 317              		@ link register save eliminated.
 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Check the parameters */
 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   assert_param(IS_PWR_REGULATOR(Regulator));
 318              		.loc 1 402 3 view .LVU46
 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
 319              		.loc 1 403 3 view .LVU47
 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   if (Regulator != PWR_MAINREGULATOR_ON)
 320              		.loc 1 405 3 view .LVU48
 321              		.loc 1 405 6 is_stmt 0 view .LVU49
 322 0000 0028     		cmp	r0, #0
 323 0002 16D0     		beq	.L26
 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* Stop mode with Low-Power Regulator */
 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1);
 324              		.loc 1 408 5 is_stmt 1 view .LVU50
 325 0004 0F4A     		ldr	r2, .L31
 326 0006 1368     		ldr	r3, [r2]
 327 0008 0720     		movs	r0, #7
 328              	.LVL10:
 329              		.loc 1 408 5 is_stmt 0 view .LVU51
 330 000a 8343     		bics	r3, r0
 331 000c 0638     		subs	r0, r0, #6
 332 000e 0343     		orrs	r3, r0
 333 0010 1360     		str	r3, [r2]
 334              	.L27:
 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   else
 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
ARM GAS  /tmp/ccDIilRR.s 			page 14


 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* Stop mode with Main Regulator */
 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 335              		.loc 1 417 3 is_stmt 1 view .LVU52
 336 0012 0D4A     		ldr	r2, .L31+4
 337 0014 1369     		ldr	r3, [r2, #16]
 338 0016 0420     		movs	r0, #4
 339 0018 0343     		orrs	r3, r0
 340 001a 1361     		str	r3, [r2, #16]
 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Select Stop mode entry --------------------------------------------------*/
 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   if (STOPEntry == PWR_STOPENTRY_WFI)
 341              		.loc 1 420 3 view .LVU53
 342              		.loc 1 420 6 is_stmt 0 view .LVU54
 343 001c 0129     		cmp	r1, #1
 344 001e 0ED0     		beq	.L30
 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* Request Wait For Interrupt */
 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __WFI();
 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   else
 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   {
 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     /* Request Wait For Event */
 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __SEV();
 345              		.loc 1 428 5 is_stmt 1 view .LVU55
 346              		.syntax divided
 347              	@ 428 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 348 0020 40BF     		sev
 349              	@ 0 "" 2
 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __WFE();
 350              		.loc 1 429 5 view .LVU56
 351              	@ 429 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 352 0022 20BF     		wfe
 353              	@ 0 "" 2
 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****     __WFE();
 354              		.loc 1 430 5 view .LVU57
 355              	@ 430 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 356 0024 20BF     		wfe
 357              	@ 0 "" 2
 358              		.thumb
 359              		.syntax unified
 360              	.L29:
 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 361              		.loc 1 434 3 view .LVU58
 362 0026 084A     		ldr	r2, .L31+4
 363 0028 1369     		ldr	r3, [r2, #16]
 364 002a 0421     		movs	r1, #4
 365              	.LVL11:
 366              		.loc 1 434 3 is_stmt 0 view .LVU59
 367 002c 8B43     		bics	r3, r1
 368 002e 1361     		str	r3, [r2, #16]
ARM GAS  /tmp/ccDIilRR.s 			page 15


 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 369              		.loc 1 435 1 view .LVU60
 370              		@ sp needed
 371 0030 7047     		bx	lr
 372              	.LVL12:
 373              	.L26:
 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 374              		.loc 1 413 5 is_stmt 1 view .LVU61
 375 0032 044A     		ldr	r2, .L31
 376 0034 1368     		ldr	r3, [r2]
 377 0036 0720     		movs	r0, #7
 378              	.LVL13:
 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 379              		.loc 1 413 5 is_stmt 0 view .LVU62
 380 0038 8343     		bics	r3, r0
 381 003a 1360     		str	r3, [r2]
 382 003c E9E7     		b	.L27
 383              	.L30:
 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   }
 384              		.loc 1 423 5 is_stmt 1 view .LVU63
 385              		.syntax divided
 386              	@ 423 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 387 003e 30BF     		wfi
 388              	@ 0 "" 2
 389              		.thumb
 390              		.syntax unified
 391 0040 F1E7     		b	.L29
 392              	.L32:
 393 0042 C046     		.align	2
 394              	.L31:
 395 0044 00700040 		.word	1073770496
 396 0048 00ED00E0 		.word	-536810240
 397              		.cfi_endproc
 398              	.LFE303:
 400              		.section	.text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
 401              		.align	1
 402              		.global	HAL_PWR_EnterSTANDBYMode
 403              		.syntax unified
 404              		.code	16
 405              		.thumb_func
 406              		.fpu softvfp
 408              	HAL_PWR_EnterSTANDBYMode:
 409              	.LFB304:
 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Enter Standby mode.
 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   In Standby mode, the PLL, the HSI and the HSE oscillators are
 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         switched off. The voltage regulator is disabled. SRAM and register
 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         contents are lost except for registers in the Backup domain and
 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         Standby circuitry. BOR is available.
 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   The I/Os can be configured either with a pull-up or pull-down or can
 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         be kept in analog state.
 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         respectively enable Pull Up and PullDown state.
 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         disable the same. These states are effective in Standby mode only if
ARM GAS  /tmp/ccDIilRR.s 			page 16


 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention()
 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 410              		.loc 1 455 1 view -0
 411              		.cfi_startproc
 412              		@ args = 0, pretend = 0, frame = 0
 413              		@ frame_needed = 0, uses_anonymous_args = 0
 414              		@ link register save eliminated.
 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Set Stand-by mode */
 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
 415              		.loc 1 457 3 view .LVU65
 416 0000 064A     		ldr	r2, .L34
 417 0002 1368     		ldr	r3, [r2]
 418 0004 0721     		movs	r1, #7
 419 0006 8B43     		bics	r3, r1
 420 0008 0439     		subs	r1, r1, #4
 421 000a 0B43     		orrs	r3, r1
 422 000c 1360     		str	r3, [r2]
 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 423              		.loc 1 460 3 view .LVU66
 424 000e 044A     		ldr	r2, .L34+4
 425 0010 1369     		ldr	r3, [r2, #16]
 426 0012 0131     		adds	r1, r1, #1
 427 0014 0B43     		orrs	r3, r1
 428 0016 1361     		str	r3, [r2, #16]
 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* This option is used to ensure that store operations are completed */
 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #if defined ( __CC_ARM)
 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   __force_stores();
 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #endif /* __CC_ARM */
 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Request Wait For Interrupt */
 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   __WFI();
 429              		.loc 1 468 3 view .LVU67
 430              		.syntax divided
 431              	@ 468 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1
 432 0018 30BF     		wfi
 433              	@ 0 "" 2
 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 434              		.loc 1 469 1 is_stmt 0 view .LVU68
 435              		.thumb
 436              		.syntax unified
 437              		@ sp needed
 438 001a 7047     		bx	lr
 439              	.L35:
 440              		.align	2
 441              	.L34:
 442 001c 00700040 		.word	1073770496
 443 0020 00ED00E0 		.word	-536810240
 444              		.cfi_endproc
 445              	.LFE304:
 447              		.section	.text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
ARM GAS  /tmp/ccDIilRR.s 			page 17


 448              		.align	1
 449              		.global	HAL_PWR_EnableSleepOnExit
 450              		.syntax unified
 451              		.code	16
 452              		.thumb_func
 453              		.fpu softvfp
 455              	HAL_PWR_EnableSleepOnExit:
 456              	.LFB305:
 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Enable Sleep-On-Exit Cortex feature
 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         processor enters SLEEP or DEEPSLEEP mode when an interruption
 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         handling is over returning to thread mode. Setting this bit is
 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         useful when the processor is expected to run only on interruptions
 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         handling.
 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 457              		.loc 1 482 1 is_stmt 1 view -0
 458              		.cfi_startproc
 459              		@ args = 0, pretend = 0, frame = 0
 460              		@ frame_needed = 0, uses_anonymous_args = 0
 461              		@ link register save eliminated.
 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Set SLEEPONEXIT bit of Cortex System Control Register */
 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 462              		.loc 1 484 3 view .LVU70
 463 0000 024A     		ldr	r2, .L37
 464 0002 1369     		ldr	r3, [r2, #16]
 465 0004 0221     		movs	r1, #2
 466 0006 0B43     		orrs	r3, r1
 467 0008 1361     		str	r3, [r2, #16]
 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 468              		.loc 1 485 1 is_stmt 0 view .LVU71
 469              		@ sp needed
 470 000a 7047     		bx	lr
 471              	.L38:
 472              		.align	2
 473              	.L37:
 474 000c 00ED00E0 		.word	-536810240
 475              		.cfi_endproc
 476              	.LFE305:
 478              		.section	.text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
 479              		.align	1
 480              		.global	HAL_PWR_DisableSleepOnExit
 481              		.syntax unified
 482              		.code	16
 483              		.thumb_func
 484              		.fpu softvfp
 486              	HAL_PWR_DisableSleepOnExit:
 487              	.LFB306:
 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Disable Sleep-On-Exit Cortex feature
ARM GAS  /tmp/ccDIilRR.s 			page 18


 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         processor enters SLEEP or DEEPSLEEP mode when an interruption
 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         handling is over.
 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 488              		.loc 1 496 1 is_stmt 1 view -0
 489              		.cfi_startproc
 490              		@ args = 0, pretend = 0, frame = 0
 491              		@ frame_needed = 0, uses_anonymous_args = 0
 492              		@ link register save eliminated.
 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 493              		.loc 1 498 3 view .LVU73
 494 0000 024A     		ldr	r2, .L40
 495 0002 1369     		ldr	r3, [r2, #16]
 496 0004 0221     		movs	r1, #2
 497 0006 8B43     		bics	r3, r1
 498 0008 1361     		str	r3, [r2, #16]
 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 499              		.loc 1 499 1 is_stmt 0 view .LVU74
 500              		@ sp needed
 501 000a 7047     		bx	lr
 502              	.L41:
 503              		.align	2
 504              	.L40:
 505 000c 00ED00E0 		.word	-536810240
 506              		.cfi_endproc
 507              	.LFE306:
 509              		.section	.text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
 510              		.align	1
 511              		.global	HAL_PWR_EnableSEVOnPend
 512              		.syntax unified
 513              		.code	16
 514              		.thumb_func
 515              		.fpu softvfp
 517              	HAL_PWR_EnableSEVOnPend:
 518              	.LFB307:
 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Enable Cortex Sev On Pending feature.
 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   Set SEVONPEND bit of SCR register. When this bit is set, enabled
 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         events and all interrupts, including disabled ones can wakeup
 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         processor from WFE.
 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 519              		.loc 1 510 1 is_stmt 1 view -0
 520              		.cfi_startproc
 521              		@ args = 0, pretend = 0, frame = 0
 522              		@ frame_needed = 0, uses_anonymous_args = 0
 523              		@ link register save eliminated.
 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Set SEVONPEND bit of Cortex System Control Register */
 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
ARM GAS  /tmp/ccDIilRR.s 			page 19


 524              		.loc 1 512 3 view .LVU76
 525 0000 024A     		ldr	r2, .L43
 526 0002 1369     		ldr	r3, [r2, #16]
 527 0004 1021     		movs	r1, #16
 528 0006 0B43     		orrs	r3, r1
 529 0008 1361     		str	r3, [r2, #16]
 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 530              		.loc 1 513 1 is_stmt 0 view .LVU77
 531              		@ sp needed
 532 000a 7047     		bx	lr
 533              	.L44:
 534              		.align	2
 535              	.L43:
 536 000c 00ED00E0 		.word	-536810240
 537              		.cfi_endproc
 538              	.LFE307:
 540              		.section	.text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
 541              		.align	1
 542              		.global	HAL_PWR_DisableSEVOnPend
 543              		.syntax unified
 544              		.code	16
 545              		.thumb_func
 546              		.fpu softvfp
 548              	HAL_PWR_DisableSEVOnPend:
 549              	.LFB308:
 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** 
 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /**
 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @brief  Disable Cortex Sev On Pending feature.
 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @note   Clear SEVONPEND bit of SCR register. When this bit is clear, only
 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   *         enable interrupts or events can wakeup processor from WFE
 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   * @retval None
 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   */
 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** {
 550              		.loc 1 523 1 is_stmt 1 view -0
 551              		.cfi_startproc
 552              		@ args = 0, pretend = 0, frame = 0
 553              		@ frame_needed = 0, uses_anonymous_args = 0
 554              		@ link register save eliminated.
 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   /* Clear SEVONPEND bit of Cortex System Control Register */
 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 555              		.loc 1 525 3 view .LVU79
 556 0000 024A     		ldr	r2, .L46
 557 0002 1369     		ldr	r3, [r2, #16]
 558 0004 1021     		movs	r1, #16
 559 0006 8B43     		bics	r3, r1
 560 0008 1361     		str	r3, [r2, #16]
 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** }
 561              		.loc 1 526 1 is_stmt 0 view .LVU80
 562              		@ sp needed
 563 000a 7047     		bx	lr
 564              	.L47:
 565              		.align	2
 566              	.L46:
 567 000c 00ED00E0 		.word	-536810240
 568              		.cfi_endproc
ARM GAS  /tmp/ccDIilRR.s 			page 20


 569              	.LFE308:
 571              		.text
 572              	.Letext0:
 573              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
 574              		.file 3 "Drivers/CMSIS/Include/core_cm0plus.h"
 575              		.file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h"
 576              		.file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h"
 577              		.file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h"
 578              		.file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h"
ARM GAS  /tmp/ccDIilRR.s 			page 21


DEFINED SYMBOLS
                            *ABS*:0000000000000000 stm32g0xx_hal_pwr.c
     /tmp/ccDIilRR.s:16     .text.HAL_PWR_DeInit:0000000000000000 $t
     /tmp/ccDIilRR.s:24     .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit
     /tmp/ccDIilRR.s:50     .text.HAL_PWR_DeInit:0000000000000018 $d
     /tmp/ccDIilRR.s:56     .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t
     /tmp/ccDIilRR.s:63     .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess
     /tmp/ccDIilRR.s:83     .text.HAL_PWR_EnableBkUpAccess:0000000000000010 $d
     /tmp/ccDIilRR.s:88     .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t
     /tmp/ccDIilRR.s:95     .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess
     /tmp/ccDIilRR.s:114    .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d
     /tmp/ccDIilRR.s:120    .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t
     /tmp/ccDIilRR.s:127    .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin
     /tmp/ccDIilRR.s:157    .text.HAL_PWR_EnableWakeUpPin:0000000000000018 $d
     /tmp/ccDIilRR.s:162    .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t
     /tmp/ccDIilRR.s:169    .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin
     /tmp/ccDIilRR.s:191    .text.HAL_PWR_DisableWakeUpPin:0000000000000010 $d
     /tmp/ccDIilRR.s:196    .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t
     /tmp/ccDIilRR.s:203    .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode
     /tmp/ccDIilRR.s:297    .text.HAL_PWR_EnterSLEEPMode:0000000000000044 $d
     /tmp/ccDIilRR.s:303    .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t
     /tmp/ccDIilRR.s:310    .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode
     /tmp/ccDIilRR.s:395    .text.HAL_PWR_EnterSTOPMode:0000000000000044 $d
     /tmp/ccDIilRR.s:401    .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t
     /tmp/ccDIilRR.s:408    .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode
     /tmp/ccDIilRR.s:442    .text.HAL_PWR_EnterSTANDBYMode:000000000000001c $d
     /tmp/ccDIilRR.s:448    .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t
     /tmp/ccDIilRR.s:455    .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit
     /tmp/ccDIilRR.s:474    .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d
     /tmp/ccDIilRR.s:479    .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t
     /tmp/ccDIilRR.s:486    .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit
     /tmp/ccDIilRR.s:505    .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d
     /tmp/ccDIilRR.s:510    .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t
     /tmp/ccDIilRR.s:517    .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend
     /tmp/ccDIilRR.s:536    .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d
     /tmp/ccDIilRR.s:541    .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t
     /tmp/ccDIilRR.s:548    .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend
     /tmp/ccDIilRR.s:567    .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d

UNDEFINED SYMBOLS
HAL_PWREx_EnableLowPowerRunMode
HAL_PWREx_DisableLowPowerRunMode
