ARM GAS  /tmp/cc5M7qsZ.s 			page 1


   1              		.cpu cortex-m0plus
   2              		.eabi_attribute 20, 1
   3              		.eabi_attribute 21, 1
   4              		.eabi_attribute 23, 3
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 1
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"stm32g0xx_hal_cortex.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.section	.text.HAL_NVIC_SetPriority,"ax",%progbits
  16              		.align	1
  17              		.global	HAL_NVIC_SetPriority
  18              		.arch armv6s-m
  19              		.syntax unified
  20              		.code	16
  21              		.thumb_func
  22              		.fpu softvfp
  24              	HAL_NVIC_SetPriority:
  25              	.LVL0:
  26              	.LFB297:
  27              		.file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c"
   1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
   2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ******************************************************************************
   3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @file    stm32g0xx_hal_cortex.c
   4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @author  MCD Application Team
   5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief   CORTEX HAL module driver.
   6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *          This file provides firmware functions to manage the following
   7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *          functionalities of the CORTEX:
   8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *           + Initialization and Configuration functions
   9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *           + Peripheral Control functions
  10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *
  11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   @verbatim
  12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ==============================================================================
  13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                         ##### How to use this driver #####
  14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ==============================================================================
  15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     [..]
  16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     *** How to configure Interrupts using CORTEX HAL driver ***
  17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     ===========================================================
  18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     [..]
  19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     This section provides functions allowing to configure the NVIC interrupts (IRQ).
  20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     The Cortex M0+ exceptions are managed by CMSIS functions.
  21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       (#) Enable and Configure the priority of the selected IRQ Channels.
  22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****              The priority can be 0..3.
  23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         -@- Lower priority values gives higher priority.
  25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         -@- Priority Order:
  26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****             (#@) Lowest priority.
  27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****             (#@) Lowest hardware priority (IRQn position).
  28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
  30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
ARM GAS  /tmp/cc5M7qsZ.s 			page 2


  32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       -@-  Negative value of IRQn_Type are not allowed.
  34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     *** How to configure Systick using CORTEX HAL driver ***
  36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     ========================================================
  37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     [..]
  38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     Setup SysTick Timer for time base.
  39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
  41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        is a CMSIS function that:
  42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         (++) Configures the SysTick Reload register with value passed as function parameter.
  43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         (++) Configures the SysTick IRQ priority to the lowest value (0x03).
  44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         (++) Resets the SysTick Counter register.
  45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
  46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         (++) Enables the SysTick Interrupt.
  47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****         (++) Starts the SysTick Counter.
  48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
  50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
  51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
  52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        inside the stm32g0xx_hal_cortex.h file.
  53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****    (+) You can change the SysTick IRQ priority by calling the
  55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
  56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
  57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****    (+) To adjust the SysTick time base, use the following formula:
  59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
  61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
  62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****        (++) Reload Value should not exceed 0xFFFFFF
  63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   @endverbatim
  65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ******************************************************************************
  66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @attention
  67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *
  68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
  69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * All rights reserved.</center></h2>
  70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *
  71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * This software component is licensed by ST under BSD 3-Clause license,
  72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * the "License"; You may not use this file except in compliance with the 
  73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * License. You may obtain a copy of the License at:
  74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *                        opensource.org/licenses/BSD-3-Clause
  75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *
  76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ******************************************************************************
  77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
  78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
  80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** #include "stm32g0xx_hal.h"
  81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup STM32G0xx_HAL_Driver
  83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @{
  84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
  85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX
  87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @{
  88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
ARM GAS  /tmp/cc5M7qsZ.s 			page 3


  89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
  91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/
  93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
  94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/
  95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/
  96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private function prototypes -----------------------------------------------*/
  97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/
  98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
  99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions
 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @{
 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group1
 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****  *  @brief    Initialization and Configuration functions
 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****  *
 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @verbatim
 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ==============================================================================
 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****               ##### Initialization and Configuration functions #####
 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ==============================================================================
 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     [..]
 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       Systick functionalities
 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @endverbatim
 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @{
 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief Sets the priority of an interrupt.
 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param IRQn External interrupt number .
 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32g0xx.h file)
 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param PreemptPriority The preemption priority for the IRQn channel.
 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be a value between 0 and 3.
 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         A lower priority value indicates a higher priority
 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param SubPriority the subpriority level for the IRQ channel.
 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         no subpriority supported in Cortex M0+ based products.
 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
  28              		.loc 1 133 1 view -0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		.loc 1 133 1 is_stmt 0 view .LVU1
  33 0000 70B5     		push	{r4, r5, r6, lr}
  34              	.LCFI0:
  35              		.cfi_def_cfa_offset 16
  36              		.cfi_offset 4, -16
  37              		.cfi_offset 5, -12
  38              		.cfi_offset 6, -8
  39              		.cfi_offset 14, -4
ARM GAS  /tmp/cc5M7qsZ.s 			page 4


 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  40              		.loc 1 135 3 is_stmt 1 view .LVU2
 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   NVIC_SetPriority(IRQn,PreemptPriority);
  41              		.loc 1 136 3 view .LVU3
  42              	.LVL1:
  43              	.LBB34:
  44              	.LBI34:
  45              		.file 2 "Drivers/CMSIS/Include/core_cm0plus.h"
   1:Drivers/CMSIS/Include/core_cm0plus.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/core_cm0plus.h ****  * @file     core_cm0plus.h
   3:Drivers/CMSIS/Include/core_cm0plus.h ****  * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
   4:Drivers/CMSIS/Include/core_cm0plus.h ****  * @version  V5.0.7
   5:Drivers/CMSIS/Include/core_cm0plus.h ****  * @date     13. March 2019
   6:Drivers/CMSIS/Include/core_cm0plus.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/core_cm0plus.h **** /*
   8:Drivers/CMSIS/Include/core_cm0plus.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/core_cm0plus.h ****  *
  10:Drivers/CMSIS/Include/core_cm0plus.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/core_cm0plus.h ****  *
  12:Drivers/CMSIS/Include/core_cm0plus.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/core_cm0plus.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/core_cm0plus.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/core_cm0plus.h ****  *
  16:Drivers/CMSIS/Include/core_cm0plus.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/core_cm0plus.h ****  *
  18:Drivers/CMSIS/Include/core_cm0plus.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/core_cm0plus.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/core_cm0plus.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/core_cm0plus.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/core_cm0plus.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/core_cm0plus.h ****  */
  24:Drivers/CMSIS/Include/core_cm0plus.h **** 
  25:Drivers/CMSIS/Include/core_cm0plus.h **** #if   defined ( __ICCARM__ )
  26:Drivers/CMSIS/Include/core_cm0plus.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
  27:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined (__clang__)
  28:Drivers/CMSIS/Include/core_cm0plus.h ****   #pragma clang system_header   /* treat file as system include file */
  29:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
  30:Drivers/CMSIS/Include/core_cm0plus.h **** 
  31:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_GENERIC
  32:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_GENERIC
  33:Drivers/CMSIS/Include/core_cm0plus.h **** 
  34:Drivers/CMSIS/Include/core_cm0plus.h **** #include <stdint.h>
  35:Drivers/CMSIS/Include/core_cm0plus.h **** 
  36:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
  37:Drivers/CMSIS/Include/core_cm0plus.h ****  extern "C" {
  38:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
  39:Drivers/CMSIS/Include/core_cm0plus.h **** 
  40:Drivers/CMSIS/Include/core_cm0plus.h **** /**
  41:Drivers/CMSIS/Include/core_cm0plus.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  42:Drivers/CMSIS/Include/core_cm0plus.h ****   CMSIS violates the following MISRA-C:2004 rules:
  43:Drivers/CMSIS/Include/core_cm0plus.h **** 
  44:Drivers/CMSIS/Include/core_cm0plus.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  45:Drivers/CMSIS/Include/core_cm0plus.h ****      Function definitions in header files are used to allow 'inlining'.
  46:Drivers/CMSIS/Include/core_cm0plus.h **** 
  47:Drivers/CMSIS/Include/core_cm0plus.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  48:Drivers/CMSIS/Include/core_cm0plus.h ****      Unions are used for effective representation of core registers.
ARM GAS  /tmp/cc5M7qsZ.s 			page 5


  49:Drivers/CMSIS/Include/core_cm0plus.h **** 
  50:Drivers/CMSIS/Include/core_cm0plus.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  51:Drivers/CMSIS/Include/core_cm0plus.h ****      Function-like macros are used to allow more efficient code.
  52:Drivers/CMSIS/Include/core_cm0plus.h ****  */
  53:Drivers/CMSIS/Include/core_cm0plus.h **** 
  54:Drivers/CMSIS/Include/core_cm0plus.h **** 
  55:Drivers/CMSIS/Include/core_cm0plus.h **** /*******************************************************************************
  56:Drivers/CMSIS/Include/core_cm0plus.h ****  *                 CMSIS definitions
  57:Drivers/CMSIS/Include/core_cm0plus.h ****  ******************************************************************************/
  58:Drivers/CMSIS/Include/core_cm0plus.h **** /**
  59:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup Cortex-M0+
  60:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
  61:Drivers/CMSIS/Include/core_cm0plus.h ****  */
  62:Drivers/CMSIS/Include/core_cm0plus.h **** 
  63:Drivers/CMSIS/Include/core_cm0plus.h **** #include "cmsis_version.h"
  64:Drivers/CMSIS/Include/core_cm0plus.h ****  
  65:Drivers/CMSIS/Include/core_cm0plus.h **** /*  CMSIS CM0+ definitions */
  66:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [3
  67:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [1
  68:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
  69:Drivers/CMSIS/Include/core_cm0plus.h ****                                        __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CM
  70:Drivers/CMSIS/Include/core_cm0plus.h **** 
  71:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core 
  72:Drivers/CMSIS/Include/core_cm0plus.h **** 
  73:Drivers/CMSIS/Include/core_cm0plus.h **** /** __FPU_USED indicates whether an FPU is used or not.
  74:Drivers/CMSIS/Include/core_cm0plus.h ****     This core does not support an FPU at all
  75:Drivers/CMSIS/Include/core_cm0plus.h **** */
  76:Drivers/CMSIS/Include/core_cm0plus.h **** #define __FPU_USED       0U
  77:Drivers/CMSIS/Include/core_cm0plus.h **** 
  78:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __CC_ARM )
  79:Drivers/CMSIS/Include/core_cm0plus.h ****   #if defined __TARGET_FPU_VFP
  80:Drivers/CMSIS/Include/core_cm0plus.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  81:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
  82:Drivers/CMSIS/Include/core_cm0plus.h **** 
  83:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  84:Drivers/CMSIS/Include/core_cm0plus.h ****   #if defined __ARM_FP
  85:Drivers/CMSIS/Include/core_cm0plus.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  86:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
  87:Drivers/CMSIS/Include/core_cm0plus.h **** 
  88:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __GNUC__ )
  89:Drivers/CMSIS/Include/core_cm0plus.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  90:Drivers/CMSIS/Include/core_cm0plus.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  91:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
  92:Drivers/CMSIS/Include/core_cm0plus.h **** 
  93:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __ICCARM__ )
  94:Drivers/CMSIS/Include/core_cm0plus.h ****   #if defined __ARMVFP__
  95:Drivers/CMSIS/Include/core_cm0plus.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  96:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
  97:Drivers/CMSIS/Include/core_cm0plus.h **** 
  98:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TI_ARM__ )
  99:Drivers/CMSIS/Include/core_cm0plus.h ****   #if defined __TI_VFP_SUPPORT__
 100:Drivers/CMSIS/Include/core_cm0plus.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 101:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 102:Drivers/CMSIS/Include/core_cm0plus.h **** 
 103:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TASKING__ )
 104:Drivers/CMSIS/Include/core_cm0plus.h ****   #if defined __FPU_VFP__
 105:Drivers/CMSIS/Include/core_cm0plus.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ARM GAS  /tmp/cc5M7qsZ.s 			page 6


 106:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 107:Drivers/CMSIS/Include/core_cm0plus.h **** 
 108:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __CSMC__ )
 109:Drivers/CMSIS/Include/core_cm0plus.h ****   #if ( __CSMC__ & 0x400U)
 110:Drivers/CMSIS/Include/core_cm0plus.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 111:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 112:Drivers/CMSIS/Include/core_cm0plus.h **** 
 113:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 114:Drivers/CMSIS/Include/core_cm0plus.h **** 
 115:Drivers/CMSIS/Include/core_cm0plus.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
 116:Drivers/CMSIS/Include/core_cm0plus.h **** 
 117:Drivers/CMSIS/Include/core_cm0plus.h **** 
 118:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
 119:Drivers/CMSIS/Include/core_cm0plus.h **** }
 120:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 121:Drivers/CMSIS/Include/core_cm0plus.h **** 
 122:Drivers/CMSIS/Include/core_cm0plus.h **** #endif /* __CORE_CM0PLUS_H_GENERIC */
 123:Drivers/CMSIS/Include/core_cm0plus.h **** 
 124:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CMSIS_GENERIC
 125:Drivers/CMSIS/Include/core_cm0plus.h **** 
 126:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_DEPENDANT
 127:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_DEPENDANT
 128:Drivers/CMSIS/Include/core_cm0plus.h **** 
 129:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
 130:Drivers/CMSIS/Include/core_cm0plus.h ****  extern "C" {
 131:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 132:Drivers/CMSIS/Include/core_cm0plus.h **** 
 133:Drivers/CMSIS/Include/core_cm0plus.h **** /* check device defines and use defaults */
 134:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __CHECK_DEVICE_DEFINES
 135:Drivers/CMSIS/Include/core_cm0plus.h ****   #ifndef __CM0PLUS_REV
 136:Drivers/CMSIS/Include/core_cm0plus.h ****     #define __CM0PLUS_REV             0x0000U
 137:Drivers/CMSIS/Include/core_cm0plus.h ****     #warning "__CM0PLUS_REV not defined in device header file; using default!"
 138:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 139:Drivers/CMSIS/Include/core_cm0plus.h **** 
 140:Drivers/CMSIS/Include/core_cm0plus.h ****   #ifndef __MPU_PRESENT
 141:Drivers/CMSIS/Include/core_cm0plus.h ****     #define __MPU_PRESENT             0U
 142:Drivers/CMSIS/Include/core_cm0plus.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
 143:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 144:Drivers/CMSIS/Include/core_cm0plus.h **** 
 145:Drivers/CMSIS/Include/core_cm0plus.h ****   #ifndef __VTOR_PRESENT
 146:Drivers/CMSIS/Include/core_cm0plus.h ****     #define __VTOR_PRESENT            0U
 147:Drivers/CMSIS/Include/core_cm0plus.h ****     #warning "__VTOR_PRESENT not defined in device header file; using default!"
 148:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 149:Drivers/CMSIS/Include/core_cm0plus.h **** 
 150:Drivers/CMSIS/Include/core_cm0plus.h ****   #ifndef __NVIC_PRIO_BITS
 151:Drivers/CMSIS/Include/core_cm0plus.h ****     #define __NVIC_PRIO_BITS          2U
 152:Drivers/CMSIS/Include/core_cm0plus.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 153:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 154:Drivers/CMSIS/Include/core_cm0plus.h **** 
 155:Drivers/CMSIS/Include/core_cm0plus.h ****   #ifndef __Vendor_SysTickConfig
 156:Drivers/CMSIS/Include/core_cm0plus.h ****     #define __Vendor_SysTickConfig    0U
 157:Drivers/CMSIS/Include/core_cm0plus.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 158:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 159:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 160:Drivers/CMSIS/Include/core_cm0plus.h **** 
 161:Drivers/CMSIS/Include/core_cm0plus.h **** /* IO definitions (access restrictions to peripheral registers) */
 162:Drivers/CMSIS/Include/core_cm0plus.h **** /**
ARM GAS  /tmp/cc5M7qsZ.s 			page 7


 163:Drivers/CMSIS/Include/core_cm0plus.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 164:Drivers/CMSIS/Include/core_cm0plus.h **** 
 165:Drivers/CMSIS/Include/core_cm0plus.h ****     <strong>IO Type Qualifiers</strong> are used
 166:Drivers/CMSIS/Include/core_cm0plus.h ****     \li to specify the access to peripheral variables.
 167:Drivers/CMSIS/Include/core_cm0plus.h ****     \li for automatic generation of peripheral register debug information.
 168:Drivers/CMSIS/Include/core_cm0plus.h **** */
 169:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
 170:Drivers/CMSIS/Include/core_cm0plus.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 171:Drivers/CMSIS/Include/core_cm0plus.h **** #else
 172:Drivers/CMSIS/Include/core_cm0plus.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 173:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 174:Drivers/CMSIS/Include/core_cm0plus.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 175:Drivers/CMSIS/Include/core_cm0plus.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 176:Drivers/CMSIS/Include/core_cm0plus.h **** 
 177:Drivers/CMSIS/Include/core_cm0plus.h **** /* following defines should be used for structure members */
 178:Drivers/CMSIS/Include/core_cm0plus.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 179:Drivers/CMSIS/Include/core_cm0plus.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 180:Drivers/CMSIS/Include/core_cm0plus.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 181:Drivers/CMSIS/Include/core_cm0plus.h **** 
 182:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group Cortex-M0+ */
 183:Drivers/CMSIS/Include/core_cm0plus.h **** 
 184:Drivers/CMSIS/Include/core_cm0plus.h **** 
 185:Drivers/CMSIS/Include/core_cm0plus.h **** 
 186:Drivers/CMSIS/Include/core_cm0plus.h **** /*******************************************************************************
 187:Drivers/CMSIS/Include/core_cm0plus.h ****  *                 Register Abstraction
 188:Drivers/CMSIS/Include/core_cm0plus.h ****   Core Register contain:
 189:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core Register
 190:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core NVIC Register
 191:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core SCB Register
 192:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core SysTick Register
 193:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core MPU Register
 194:Drivers/CMSIS/Include/core_cm0plus.h ****  ******************************************************************************/
 195:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 196:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 197:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 198:Drivers/CMSIS/Include/core_cm0plus.h **** */
 199:Drivers/CMSIS/Include/core_cm0plus.h **** 
 200:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 201:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup    CMSIS_core_register
 202:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 203:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief      Core Register type definitions.
 204:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 205:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 206:Drivers/CMSIS/Include/core_cm0plus.h **** 
 207:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 208:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 209:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 210:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
 211:Drivers/CMSIS/Include/core_cm0plus.h **** {
 212:Drivers/CMSIS/Include/core_cm0plus.h ****   struct
 213:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 214:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
 215:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 216:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 217:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 218:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 219:Drivers/CMSIS/Include/core_cm0plus.h ****   } b;                                   /*!< Structure used for bit  access */
ARM GAS  /tmp/cc5M7qsZ.s 			page 8


 220:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t w;                            /*!< Type      used for word access */
 221:Drivers/CMSIS/Include/core_cm0plus.h **** } APSR_Type;
 222:Drivers/CMSIS/Include/core_cm0plus.h **** 
 223:Drivers/CMSIS/Include/core_cm0plus.h **** /* APSR Register Definitions */
 224:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 225:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 226:Drivers/CMSIS/Include/core_cm0plus.h **** 
 227:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 228:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 229:Drivers/CMSIS/Include/core_cm0plus.h **** 
 230:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 231:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 232:Drivers/CMSIS/Include/core_cm0plus.h **** 
 233:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 234:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 235:Drivers/CMSIS/Include/core_cm0plus.h **** 
 236:Drivers/CMSIS/Include/core_cm0plus.h **** 
 237:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 238:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 239:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 240:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
 241:Drivers/CMSIS/Include/core_cm0plus.h **** {
 242:Drivers/CMSIS/Include/core_cm0plus.h ****   struct
 243:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 244:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 245:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 246:Drivers/CMSIS/Include/core_cm0plus.h ****   } b;                                   /*!< Structure used for bit  access */
 247:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t w;                            /*!< Type      used for word access */
 248:Drivers/CMSIS/Include/core_cm0plus.h **** } IPSR_Type;
 249:Drivers/CMSIS/Include/core_cm0plus.h **** 
 250:Drivers/CMSIS/Include/core_cm0plus.h **** /* IPSR Register Definitions */
 251:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 252:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 253:Drivers/CMSIS/Include/core_cm0plus.h **** 
 254:Drivers/CMSIS/Include/core_cm0plus.h **** 
 255:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 256:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 257:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 258:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
 259:Drivers/CMSIS/Include/core_cm0plus.h **** {
 260:Drivers/CMSIS/Include/core_cm0plus.h ****   struct
 261:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 262:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 263:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
 264:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 265:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
 266:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 267:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 268:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 269:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 270:Drivers/CMSIS/Include/core_cm0plus.h ****   } b;                                   /*!< Structure used for bit  access */
 271:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t w;                            /*!< Type      used for word access */
 272:Drivers/CMSIS/Include/core_cm0plus.h **** } xPSR_Type;
 273:Drivers/CMSIS/Include/core_cm0plus.h **** 
 274:Drivers/CMSIS/Include/core_cm0plus.h **** /* xPSR Register Definitions */
 275:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 276:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
ARM GAS  /tmp/cc5M7qsZ.s 			page 9


 277:Drivers/CMSIS/Include/core_cm0plus.h **** 
 278:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 279:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 280:Drivers/CMSIS/Include/core_cm0plus.h **** 
 281:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 282:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 283:Drivers/CMSIS/Include/core_cm0plus.h **** 
 284:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 285:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 286:Drivers/CMSIS/Include/core_cm0plus.h **** 
 287:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 288:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 289:Drivers/CMSIS/Include/core_cm0plus.h **** 
 290:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 291:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 292:Drivers/CMSIS/Include/core_cm0plus.h **** 
 293:Drivers/CMSIS/Include/core_cm0plus.h **** 
 294:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 295:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Union type to access the Control Registers (CONTROL).
 296:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 297:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
 298:Drivers/CMSIS/Include/core_cm0plus.h **** {
 299:Drivers/CMSIS/Include/core_cm0plus.h ****   struct
 300:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 301:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
 302:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 303:Drivers/CMSIS/Include/core_cm0plus.h ****     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
 304:Drivers/CMSIS/Include/core_cm0plus.h ****   } b;                                   /*!< Structure used for bit  access */
 305:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t w;                            /*!< Type      used for word access */
 306:Drivers/CMSIS/Include/core_cm0plus.h **** } CONTROL_Type;
 307:Drivers/CMSIS/Include/core_cm0plus.h **** 
 308:Drivers/CMSIS/Include/core_cm0plus.h **** /* CONTROL Register Definitions */
 309:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 310:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 311:Drivers/CMSIS/Include/core_cm0plus.h **** 
 312:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
 313:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
 314:Drivers/CMSIS/Include/core_cm0plus.h **** 
 315:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CORE */
 316:Drivers/CMSIS/Include/core_cm0plus.h **** 
 317:Drivers/CMSIS/Include/core_cm0plus.h **** 
 318:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 319:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup    CMSIS_core_register
 320:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 321:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief      Type definitions for the NVIC Registers
 322:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 323:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 324:Drivers/CMSIS/Include/core_cm0plus.h **** 
 325:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 326:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 327:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 328:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
 329:Drivers/CMSIS/Include/core_cm0plus.h **** {
 330:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 331:Drivers/CMSIS/Include/core_cm0plus.h ****         uint32_t RESERVED0[31U];
 332:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 333:Drivers/CMSIS/Include/core_cm0plus.h ****         uint32_t RESERVED1[31U];
ARM GAS  /tmp/cc5M7qsZ.s 			page 10


 334:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 335:Drivers/CMSIS/Include/core_cm0plus.h ****         uint32_t RESERVED2[31U];
 336:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 337:Drivers/CMSIS/Include/core_cm0plus.h ****         uint32_t RESERVED3[31U];
 338:Drivers/CMSIS/Include/core_cm0plus.h ****         uint32_t RESERVED4[64U];
 339:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 340:Drivers/CMSIS/Include/core_cm0plus.h **** }  NVIC_Type;
 341:Drivers/CMSIS/Include/core_cm0plus.h **** 
 342:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_NVIC */
 343:Drivers/CMSIS/Include/core_cm0plus.h **** 
 344:Drivers/CMSIS/Include/core_cm0plus.h **** 
 345:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 346:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup  CMSIS_core_register
 347:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 348:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief    Type definitions for the System Control Block Registers
 349:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 350:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 351:Drivers/CMSIS/Include/core_cm0plus.h **** 
 352:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 353:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Structure type to access the System Control Block (SCB).
 354:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 355:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
 356:Drivers/CMSIS/Include/core_cm0plus.h **** {
 357:Drivers/CMSIS/Include/core_cm0plus.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 358:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 359:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
 360:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 361:Drivers/CMSIS/Include/core_cm0plus.h **** #else
 362:Drivers/CMSIS/Include/core_cm0plus.h ****         uint32_t RESERVED0;
 363:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 364:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 365:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 366:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 367:Drivers/CMSIS/Include/core_cm0plus.h ****         uint32_t RESERVED1;
 368:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registe
 369:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 370:Drivers/CMSIS/Include/core_cm0plus.h **** } SCB_Type;
 371:Drivers/CMSIS/Include/core_cm0plus.h **** 
 372:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB CPUID Register Definitions */
 373:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 374:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 375:Drivers/CMSIS/Include/core_cm0plus.h **** 
 376:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 377:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 378:Drivers/CMSIS/Include/core_cm0plus.h **** 
 379:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 380:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 381:Drivers/CMSIS/Include/core_cm0plus.h **** 
 382:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 383:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 384:Drivers/CMSIS/Include/core_cm0plus.h **** 
 385:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 386:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 387:Drivers/CMSIS/Include/core_cm0plus.h **** 
 388:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */
 389:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 390:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
ARM GAS  /tmp/cc5M7qsZ.s 			page 11


 391:Drivers/CMSIS/Include/core_cm0plus.h **** 
 392:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 393:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 394:Drivers/CMSIS/Include/core_cm0plus.h **** 
 395:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 396:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 397:Drivers/CMSIS/Include/core_cm0plus.h **** 
 398:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 399:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 400:Drivers/CMSIS/Include/core_cm0plus.h **** 
 401:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 402:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 403:Drivers/CMSIS/Include/core_cm0plus.h **** 
 404:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 405:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 406:Drivers/CMSIS/Include/core_cm0plus.h **** 
 407:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 408:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 409:Drivers/CMSIS/Include/core_cm0plus.h **** 
 410:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 411:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 412:Drivers/CMSIS/Include/core_cm0plus.h **** 
 413:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 414:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 415:Drivers/CMSIS/Include/core_cm0plus.h **** 
 416:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
 417:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */
 418:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB 
 419:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB 
 420:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 421:Drivers/CMSIS/Include/core_cm0plus.h **** 
 422:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 423:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 424:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 425:Drivers/CMSIS/Include/core_cm0plus.h **** 
 426:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 427:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 428:Drivers/CMSIS/Include/core_cm0plus.h **** 
 429:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 430:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 431:Drivers/CMSIS/Include/core_cm0plus.h **** 
 432:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 433:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 434:Drivers/CMSIS/Include/core_cm0plus.h **** 
 435:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 436:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 437:Drivers/CMSIS/Include/core_cm0plus.h **** 
 438:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Control Register Definitions */
 439:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 440:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 441:Drivers/CMSIS/Include/core_cm0plus.h **** 
 442:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 443:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 444:Drivers/CMSIS/Include/core_cm0plus.h **** 
 445:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 446:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 447:Drivers/CMSIS/Include/core_cm0plus.h **** 
ARM GAS  /tmp/cc5M7qsZ.s 			page 12


 448:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Configuration Control Register Definitions */
 449:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 450:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 451:Drivers/CMSIS/Include/core_cm0plus.h **** 
 452:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 453:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 454:Drivers/CMSIS/Include/core_cm0plus.h **** 
 455:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Handler Control and State Register Definitions */
 456:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 457:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 458:Drivers/CMSIS/Include/core_cm0plus.h **** 
 459:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SCB */
 460:Drivers/CMSIS/Include/core_cm0plus.h **** 
 461:Drivers/CMSIS/Include/core_cm0plus.h **** 
 462:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 463:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup  CMSIS_core_register
 464:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 465:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief    Type definitions for the System Timer Registers.
 466:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 467:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 468:Drivers/CMSIS/Include/core_cm0plus.h **** 
 469:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 470:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Structure type to access the System Timer (SysTick).
 471:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 472:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
 473:Drivers/CMSIS/Include/core_cm0plus.h **** {
 474:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 475:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 476:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 477:Drivers/CMSIS/Include/core_cm0plus.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 478:Drivers/CMSIS/Include/core_cm0plus.h **** } SysTick_Type;
 479:Drivers/CMSIS/Include/core_cm0plus.h **** 
 480:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Control / Status Register Definitions */
 481:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 482:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 483:Drivers/CMSIS/Include/core_cm0plus.h **** 
 484:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 485:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 486:Drivers/CMSIS/Include/core_cm0plus.h **** 
 487:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 488:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 489:Drivers/CMSIS/Include/core_cm0plus.h **** 
 490:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 491:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 492:Drivers/CMSIS/Include/core_cm0plus.h **** 
 493:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Reload Register Definitions */
 494:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 495:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 496:Drivers/CMSIS/Include/core_cm0plus.h **** 
 497:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Current Register Definitions */
 498:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 499:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 500:Drivers/CMSIS/Include/core_cm0plus.h **** 
 501:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Calibration Register Definitions */
 502:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 503:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 504:Drivers/CMSIS/Include/core_cm0plus.h **** 
ARM GAS  /tmp/cc5M7qsZ.s 			page 13


 505:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 506:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 507:Drivers/CMSIS/Include/core_cm0plus.h **** 
 508:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 509:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 510:Drivers/CMSIS/Include/core_cm0plus.h **** 
 511:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SysTick */
 512:Drivers/CMSIS/Include/core_cm0plus.h **** 
 513:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 514:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 515:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup  CMSIS_core_register
 516:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
 517:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
 518:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 519:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 520:Drivers/CMSIS/Include/core_cm0plus.h **** 
 521:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 522:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
 523:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 524:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
 525:Drivers/CMSIS/Include/core_cm0plus.h **** {
 526:Drivers/CMSIS/Include/core_cm0plus.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
 527:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
 528:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
 529:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
 530:Drivers/CMSIS/Include/core_cm0plus.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
 531:Drivers/CMSIS/Include/core_cm0plus.h **** } MPU_Type;
 532:Drivers/CMSIS/Include/core_cm0plus.h **** 
 533:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_RALIASES                  1U
 534:Drivers/CMSIS/Include/core_cm0plus.h **** 
 535:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Type Register Definitions */
 536:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
 537:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
 538:Drivers/CMSIS/Include/core_cm0plus.h **** 
 539:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
 540:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
 541:Drivers/CMSIS/Include/core_cm0plus.h **** 
 542:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
 543:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
 544:Drivers/CMSIS/Include/core_cm0plus.h **** 
 545:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Control Register Definitions */
 546:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
 547:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
 548:Drivers/CMSIS/Include/core_cm0plus.h **** 
 549:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
 550:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
 551:Drivers/CMSIS/Include/core_cm0plus.h **** 
 552:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
 553:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
 554:Drivers/CMSIS/Include/core_cm0plus.h **** 
 555:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Number Register Definitions */
 556:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
 557:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
 558:Drivers/CMSIS/Include/core_cm0plus.h **** 
 559:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Base Address Register Definitions */
 560:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU 
 561:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU 
ARM GAS  /tmp/cc5M7qsZ.s 			page 14


 562:Drivers/CMSIS/Include/core_cm0plus.h **** 
 563:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
 564:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
 565:Drivers/CMSIS/Include/core_cm0plus.h **** 
 566:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
 567:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
 568:Drivers/CMSIS/Include/core_cm0plus.h **** 
 569:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Attribute and Size Register Definitions */
 570:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
 571:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
 572:Drivers/CMSIS/Include/core_cm0plus.h **** 
 573:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
 574:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
 575:Drivers/CMSIS/Include/core_cm0plus.h **** 
 576:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
 577:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
 578:Drivers/CMSIS/Include/core_cm0plus.h **** 
 579:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
 580:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
 581:Drivers/CMSIS/Include/core_cm0plus.h **** 
 582:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
 583:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
 584:Drivers/CMSIS/Include/core_cm0plus.h **** 
 585:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
 586:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
 587:Drivers/CMSIS/Include/core_cm0plus.h **** 
 588:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
 589:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
 590:Drivers/CMSIS/Include/core_cm0plus.h **** 
 591:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
 592:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
 593:Drivers/CMSIS/Include/core_cm0plus.h **** 
 594:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
 595:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
 596:Drivers/CMSIS/Include/core_cm0plus.h **** 
 597:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
 598:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
 599:Drivers/CMSIS/Include/core_cm0plus.h **** 
 600:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_MPU */
 601:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 602:Drivers/CMSIS/Include/core_cm0plus.h **** 
 603:Drivers/CMSIS/Include/core_cm0plus.h **** 
 604:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 605:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup  CMSIS_core_register
 606:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
 607:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ov
 608:Drivers/CMSIS/Include/core_cm0plus.h ****             Therefore they are not covered by the Cortex-M0+ header file.
 609:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 610:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 611:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CoreDebug */
 612:Drivers/CMSIS/Include/core_cm0plus.h **** 
 613:Drivers/CMSIS/Include/core_cm0plus.h **** 
 614:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 615:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup    CMSIS_core_register
 616:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
 617:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
 618:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
ARM GAS  /tmp/cc5M7qsZ.s 			page 15


 619:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 620:Drivers/CMSIS/Include/core_cm0plus.h **** 
 621:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 622:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
 623:Drivers/CMSIS/Include/core_cm0plus.h ****   \param[in] field  Name of the register bit field.
 624:Drivers/CMSIS/Include/core_cm0plus.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
 625:Drivers/CMSIS/Include/core_cm0plus.h ****   \return           Masked and shifted value.
 626:Drivers/CMSIS/Include/core_cm0plus.h **** */
 627:Drivers/CMSIS/Include/core_cm0plus.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 628:Drivers/CMSIS/Include/core_cm0plus.h **** 
 629:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 630:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief     Mask and shift a register value to extract a bit filed value.
 631:Drivers/CMSIS/Include/core_cm0plus.h ****   \param[in] field  Name of the register bit field.
 632:Drivers/CMSIS/Include/core_cm0plus.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
 633:Drivers/CMSIS/Include/core_cm0plus.h ****   \return           Masked and shifted bit field value.
 634:Drivers/CMSIS/Include/core_cm0plus.h **** */
 635:Drivers/CMSIS/Include/core_cm0plus.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 636:Drivers/CMSIS/Include/core_cm0plus.h **** 
 637:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_core_bitfield */
 638:Drivers/CMSIS/Include/core_cm0plus.h **** 
 639:Drivers/CMSIS/Include/core_cm0plus.h **** 
 640:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 641:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup    CMSIS_core_register
 642:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup   CMSIS_core_base     Core Definitions
 643:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief      Definitions for base addresses, unions, and structures.
 644:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 645:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 646:Drivers/CMSIS/Include/core_cm0plus.h **** 
 647:Drivers/CMSIS/Include/core_cm0plus.h **** /* Memory mapping of Core Hardware */
 648:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
 649:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 650:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 651:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
 652:Drivers/CMSIS/Include/core_cm0plus.h **** 
 653:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
 654:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
 655:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
 656:Drivers/CMSIS/Include/core_cm0plus.h **** 
 657:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 658:Drivers/CMSIS/Include/core_cm0plus.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
 659:Drivers/CMSIS/Include/core_cm0plus.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
 660:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 661:Drivers/CMSIS/Include/core_cm0plus.h **** 
 662:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} */
 663:Drivers/CMSIS/Include/core_cm0plus.h **** 
 664:Drivers/CMSIS/Include/core_cm0plus.h **** 
 665:Drivers/CMSIS/Include/core_cm0plus.h **** 
 666:Drivers/CMSIS/Include/core_cm0plus.h **** /*******************************************************************************
 667:Drivers/CMSIS/Include/core_cm0plus.h ****  *                Hardware Abstraction Layer
 668:Drivers/CMSIS/Include/core_cm0plus.h ****   Core Function Interface contains:
 669:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core NVIC Functions
 670:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core SysTick Functions
 671:Drivers/CMSIS/Include/core_cm0plus.h ****   - Core Register Access Functions
 672:Drivers/CMSIS/Include/core_cm0plus.h ****  ******************************************************************************/
 673:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 674:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 675:Drivers/CMSIS/Include/core_cm0plus.h **** */
ARM GAS  /tmp/cc5M7qsZ.s 			page 16


 676:Drivers/CMSIS/Include/core_cm0plus.h **** 
 677:Drivers/CMSIS/Include/core_cm0plus.h **** 
 678:Drivers/CMSIS/Include/core_cm0plus.h **** 
 679:Drivers/CMSIS/Include/core_cm0plus.h **** /* ##########################   NVIC functions  #################################### */
 680:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 681:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup  CMSIS_Core_FunctionInterface
 682:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
 683:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
 684:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
 685:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 686:Drivers/CMSIS/Include/core_cm0plus.h **** 
 687:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef CMSIS_NVIC_VIRTUAL
 688:Drivers/CMSIS/Include/core_cm0plus.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
 689:Drivers/CMSIS/Include/core_cm0plus.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
 690:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 691:Drivers/CMSIS/Include/core_cm0plus.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 692:Drivers/CMSIS/Include/core_cm0plus.h **** #else
 693:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
 694:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
 695:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
 696:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
 697:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
 698:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
 699:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
 700:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 701:Drivers/CMSIS/Include/core_cm0plus.h **** /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
 702:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
 703:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
 704:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
 705:Drivers/CMSIS/Include/core_cm0plus.h **** #endif /* CMSIS_NVIC_VIRTUAL */
 706:Drivers/CMSIS/Include/core_cm0plus.h **** 
 707:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef CMSIS_VECTAB_VIRTUAL
 708:Drivers/CMSIS/Include/core_cm0plus.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 709:Drivers/CMSIS/Include/core_cm0plus.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
 710:Drivers/CMSIS/Include/core_cm0plus.h ****   #endif
 711:Drivers/CMSIS/Include/core_cm0plus.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 712:Drivers/CMSIS/Include/core_cm0plus.h **** #else
 713:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_SetVector              __NVIC_SetVector
 714:Drivers/CMSIS/Include/core_cm0plus.h ****   #define NVIC_GetVector              __NVIC_GetVector
 715:Drivers/CMSIS/Include/core_cm0plus.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 716:Drivers/CMSIS/Include/core_cm0plus.h **** 
 717:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_USER_IRQ_OFFSET          16
 718:Drivers/CMSIS/Include/core_cm0plus.h **** 
 719:Drivers/CMSIS/Include/core_cm0plus.h **** 
 720:Drivers/CMSIS/Include/core_cm0plus.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
 721:Drivers/CMSIS/Include/core_cm0plus.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
 722:Drivers/CMSIS/Include/core_cm0plus.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
 723:Drivers/CMSIS/Include/core_cm0plus.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
 724:Drivers/CMSIS/Include/core_cm0plus.h **** 
 725:Drivers/CMSIS/Include/core_cm0plus.h **** 
 726:Drivers/CMSIS/Include/core_cm0plus.h **** /* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 727:Drivers/CMSIS/Include/core_cm0plus.h **** /* The following MACROS handle generation of the register offset and byte masks */
 728:Drivers/CMSIS/Include/core_cm0plus.h **** #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 729:Drivers/CMSIS/Include/core_cm0plus.h **** #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 730:Drivers/CMSIS/Include/core_cm0plus.h **** #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 731:Drivers/CMSIS/Include/core_cm0plus.h **** 
 732:Drivers/CMSIS/Include/core_cm0plus.h **** #define __NVIC_SetPriorityGrouping(X) (void)(X)
ARM GAS  /tmp/cc5M7qsZ.s 			page 17


 733:Drivers/CMSIS/Include/core_cm0plus.h **** #define __NVIC_GetPriorityGrouping()  (0U)
 734:Drivers/CMSIS/Include/core_cm0plus.h **** 
 735:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 736:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Enable Interrupt
 737:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
 738:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]      IRQn  Device specific interrupt number.
 739:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    IRQn must not be negative.
 740:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 741:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 742:Drivers/CMSIS/Include/core_cm0plus.h **** {
 743:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
 744:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 745:Drivers/CMSIS/Include/core_cm0plus.h ****     __COMPILER_BARRIER();
 746:Drivers/CMSIS/Include/core_cm0plus.h ****     NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 747:Drivers/CMSIS/Include/core_cm0plus.h ****     __COMPILER_BARRIER();
 748:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 749:Drivers/CMSIS/Include/core_cm0plus.h **** }
 750:Drivers/CMSIS/Include/core_cm0plus.h **** 
 751:Drivers/CMSIS/Include/core_cm0plus.h **** 
 752:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 753:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Get Interrupt Enable status
 754:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
 755:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]      IRQn  Device specific interrupt number.
 756:Drivers/CMSIS/Include/core_cm0plus.h ****   \return             0  Interrupt is not enabled.
 757:Drivers/CMSIS/Include/core_cm0plus.h ****   \return             1  Interrupt is enabled.
 758:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    IRQn must not be negative.
 759:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 760:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 761:Drivers/CMSIS/Include/core_cm0plus.h **** {
 762:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
 763:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 764:Drivers/CMSIS/Include/core_cm0plus.h ****     return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 765:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 766:Drivers/CMSIS/Include/core_cm0plus.h ****   else
 767:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 768:Drivers/CMSIS/Include/core_cm0plus.h ****     return(0U);
 769:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 770:Drivers/CMSIS/Include/core_cm0plus.h **** }
 771:Drivers/CMSIS/Include/core_cm0plus.h **** 
 772:Drivers/CMSIS/Include/core_cm0plus.h **** 
 773:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 774:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Disable Interrupt
 775:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
 776:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]      IRQn  Device specific interrupt number.
 777:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    IRQn must not be negative.
 778:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 779:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 780:Drivers/CMSIS/Include/core_cm0plus.h **** {
 781:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
 782:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 783:Drivers/CMSIS/Include/core_cm0plus.h ****     NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 784:Drivers/CMSIS/Include/core_cm0plus.h ****     __DSB();
 785:Drivers/CMSIS/Include/core_cm0plus.h ****     __ISB();
 786:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 787:Drivers/CMSIS/Include/core_cm0plus.h **** }
 788:Drivers/CMSIS/Include/core_cm0plus.h **** 
 789:Drivers/CMSIS/Include/core_cm0plus.h **** 
ARM GAS  /tmp/cc5M7qsZ.s 			page 18


 790:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 791:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Get Pending Interrupt
 792:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
 793:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]      IRQn  Device specific interrupt number.
 794:Drivers/CMSIS/Include/core_cm0plus.h ****   \return             0  Interrupt status is not pending.
 795:Drivers/CMSIS/Include/core_cm0plus.h ****   \return             1  Interrupt status is pending.
 796:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    IRQn must not be negative.
 797:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 798:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 799:Drivers/CMSIS/Include/core_cm0plus.h **** {
 800:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
 801:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 802:Drivers/CMSIS/Include/core_cm0plus.h ****     return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 803:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 804:Drivers/CMSIS/Include/core_cm0plus.h ****   else
 805:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 806:Drivers/CMSIS/Include/core_cm0plus.h ****     return(0U);
 807:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 808:Drivers/CMSIS/Include/core_cm0plus.h **** }
 809:Drivers/CMSIS/Include/core_cm0plus.h **** 
 810:Drivers/CMSIS/Include/core_cm0plus.h **** 
 811:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 812:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Set Pending Interrupt
 813:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
 814:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]      IRQn  Device specific interrupt number.
 815:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    IRQn must not be negative.
 816:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 817:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 818:Drivers/CMSIS/Include/core_cm0plus.h **** {
 819:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
 820:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 821:Drivers/CMSIS/Include/core_cm0plus.h ****     NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 822:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 823:Drivers/CMSIS/Include/core_cm0plus.h **** }
 824:Drivers/CMSIS/Include/core_cm0plus.h **** 
 825:Drivers/CMSIS/Include/core_cm0plus.h **** 
 826:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 827:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Clear Pending Interrupt
 828:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
 829:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]      IRQn  Device specific interrupt number.
 830:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    IRQn must not be negative.
 831:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 832:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 833:Drivers/CMSIS/Include/core_cm0plus.h **** {
 834:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
 835:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 836:Drivers/CMSIS/Include/core_cm0plus.h ****     NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 837:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 838:Drivers/CMSIS/Include/core_cm0plus.h **** }
 839:Drivers/CMSIS/Include/core_cm0plus.h **** 
 840:Drivers/CMSIS/Include/core_cm0plus.h **** 
 841:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 842:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Set Interrupt Priority
 843:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
 844:Drivers/CMSIS/Include/core_cm0plus.h ****            The interrupt number can be positive to specify a device specific interrupt,
 845:Drivers/CMSIS/Include/core_cm0plus.h ****            or negative to specify a processor exception.
 846:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]      IRQn  Interrupt number.
ARM GAS  /tmp/cc5M7qsZ.s 			page 19


 847:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]  priority  Priority to set.
 848:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    The priority cannot be set for every processor exception.
 849:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 850:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  46              		.loc 2 850 22 view .LVU4
  47              	.LBB35:
 851:Drivers/CMSIS/Include/core_cm0plus.h **** {
 852:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
  48              		.loc 2 852 3 view .LVU5
  49              		.loc 2 852 6 is_stmt 0 view .LVU6
  50 0002 0028     		cmp	r0, #0
  51 0004 11DB     		blt	.L2
 853:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 854:Drivers/CMSIS/Include/core_cm0plus.h ****     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))
  52              		.loc 2 854 5 is_stmt 1 view .LVU7
  53              		.loc 2 854 53 is_stmt 0 view .LVU8
  54 0006 8308     		lsrs	r3, r0, #2
  55              		.loc 2 854 52 view .LVU9
  56 0008 134E     		ldr	r6, .L4
  57 000a C033     		adds	r3, r3, #192
  58 000c 9B00     		lsls	r3, r3, #2
  59 000e 9D59     		ldr	r5, [r3, r6]
  60              		.loc 2 854 83 view .LVU10
  61 0010 0324     		movs	r4, #3
  62 0012 2040     		ands	r0, r4
  63              	.LVL2:
  64              		.loc 2 854 83 view .LVU11
  65 0014 C000     		lsls	r0, r0, #3
  66              		.loc 2 854 80 view .LVU12
  67 0016 FF22     		movs	r2, #255
  68              	.LVL3:
  69              		.loc 2 854 80 view .LVU13
  70 0018 1400     		movs	r4, r2
  71 001a 8440     		lsls	r4, r4, r0
  72              		.loc 2 854 33 view .LVU14
  73 001c A543     		bics	r5, r4
 855:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  74              		.loc 2 855 20 view .LVU15
  75 001e 8901     		lsls	r1, r1, #6
  76              	.LVL4:
  77              		.loc 2 855 48 view .LVU16
  78 0020 0A40     		ands	r2, r1
  79              		.loc 2 855 68 view .LVU17
  80 0022 8240     		lsls	r2, r2, r0
 854:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  81              		.loc 2 854 102 view .LVU18
  82 0024 2A43     		orrs	r2, r5
 854:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  83              		.loc 2 854 30 view .LVU19
  84 0026 9A51     		str	r2, [r3, r6]
  85              	.LVL5:
  86              	.L1:
 854:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  87              		.loc 2 854 30 view .LVU20
  88              	.LBE35:
  89              	.LBE34:
 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
ARM GAS  /tmp/cc5M7qsZ.s 			page 20


  90              		.loc 1 137 1 view .LVU21
  91              		@ sp needed
  92 0028 70BD     		pop	{r4, r5, r6, pc}
  93              	.LVL6:
  94              	.L2:
  95              	.LBB37:
  96              	.LBB36:
 856:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 857:Drivers/CMSIS/Include/core_cm0plus.h ****   else
 858:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 859:Drivers/CMSIS/Include/core_cm0plus.h ****     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))
  97              		.loc 2 859 5 is_stmt 1 view .LVU22
  98              		.loc 2 859 53 is_stmt 0 view .LVU23
  99 002a 0F23     		movs	r3, #15
 100 002c 0340     		ands	r3, r0
 101 002e 083B     		subs	r3, r3, #8
 102 0030 9B08     		lsrs	r3, r3, #2
 103              		.loc 2 859 52 view .LVU24
 104 0032 0633     		adds	r3, r3, #6
 105 0034 9B00     		lsls	r3, r3, #2
 106 0036 094A     		ldr	r2, .L4+4
 107              	.LVL7:
 108              		.loc 2 859 52 view .LVU25
 109 0038 9446     		mov	ip, r2
 110 003a 6344     		add	r3, r3, ip
 111 003c 5C68     		ldr	r4, [r3, #4]
 112              		.loc 2 859 83 view .LVU26
 113 003e 0322     		movs	r2, #3
 114 0040 1040     		ands	r0, r2
 115              	.LVL8:
 116              		.loc 2 859 83 view .LVU27
 117 0042 C000     		lsls	r0, r0, #3
 118              		.loc 2 859 80 view .LVU28
 119 0044 FC32     		adds	r2, r2, #252
 120 0046 1500     		movs	r5, r2
 121 0048 8540     		lsls	r5, r5, r0
 122              		.loc 2 859 33 view .LVU29
 123 004a AC43     		bics	r4, r5
 860:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 124              		.loc 2 860 20 view .LVU30
 125 004c 8901     		lsls	r1, r1, #6
 126              	.LVL9:
 127              		.loc 2 860 48 view .LVU31
 128 004e 0A40     		ands	r2, r1
 129              		.loc 2 860 68 view .LVU32
 130 0050 8240     		lsls	r2, r2, r0
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 131              		.loc 2 859 102 view .LVU33
 132 0052 2243     		orrs	r2, r4
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 133              		.loc 2 859 30 view .LVU34
 134 0054 5A60     		str	r2, [r3, #4]
 135              	.LVL10:
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 136              		.loc 2 859 30 view .LVU35
 137              	.LBE36:
 138              	.LBE37:
ARM GAS  /tmp/cc5M7qsZ.s 			page 21


 139              		.loc 1 137 1 view .LVU36
 140 0056 E7E7     		b	.L1
 141              	.L5:
 142              		.align	2
 143              	.L4:
 144 0058 00E100E0 		.word	-536813312
 145 005c 00ED00E0 		.word	-536810240
 146              		.cfi_endproc
 147              	.LFE297:
 149              		.section	.text.HAL_NVIC_EnableIRQ,"ax",%progbits
 150              		.align	1
 151              		.global	HAL_NVIC_EnableIRQ
 152              		.syntax unified
 153              		.code	16
 154              		.thumb_func
 155              		.fpu softvfp
 157              	HAL_NVIC_EnableIRQ:
 158              	.LVL11:
 159              	.LFB298:
 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 160              		.loc 1 147 1 is_stmt 1 view -0
 161              		.cfi_startproc
 162              		@ args = 0, pretend = 0, frame = 0
 163              		@ frame_needed = 0, uses_anonymous_args = 0
 164              		@ link register save eliminated.
 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 165              		.loc 1 149 3 view .LVU38
 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Enable interrupt */
 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   NVIC_EnableIRQ(IRQn);
 166              		.loc 1 152 3 view .LVU39
 167              	.LBB38:
 168              	.LBI38:
 741:Drivers/CMSIS/Include/core_cm0plus.h **** {
 169              		.loc 2 741 22 view .LVU40
 170              	.LBB39:
 743:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 171              		.loc 2 743 3 view .LVU41
 743:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 172              		.loc 2 743 6 is_stmt 0 view .LVU42
 173 0000 0028     		cmp	r0, #0
 174 0002 05DB     		blt	.L6
 745:Drivers/CMSIS/Include/core_cm0plus.h ****     NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 175              		.loc 2 745 5 is_stmt 1 view .LVU43
 746:Drivers/CMSIS/Include/core_cm0plus.h ****     __COMPILER_BARRIER();
 176              		.loc 2 746 5 view .LVU44
 746:Drivers/CMSIS/Include/core_cm0plus.h ****     __COMPILER_BARRIER();
ARM GAS  /tmp/cc5M7qsZ.s 			page 22


 177              		.loc 2 746 58 is_stmt 0 view .LVU45
 178 0004 1F23     		movs	r3, #31
 179 0006 1840     		ands	r0, r3
 180              	.LVL12:
 746:Drivers/CMSIS/Include/core_cm0plus.h ****     __COMPILER_BARRIER();
 181              		.loc 2 746 22 view .LVU46
 182 0008 1E3B     		subs	r3, r3, #30
 183 000a 8340     		lsls	r3, r3, r0
 746:Drivers/CMSIS/Include/core_cm0plus.h ****     __COMPILER_BARRIER();
 184              		.loc 2 746 20 view .LVU47
 185 000c 014A     		ldr	r2, .L8
 186 000e 1360     		str	r3, [r2]
 747:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 187              		.loc 2 747 5 is_stmt 1 view .LVU48
 188              	.LVL13:
 189              	.L6:
 747:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 190              		.loc 2 747 5 is_stmt 0 view .LVU49
 191              	.LBE39:
 192              	.LBE38:
 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 193              		.loc 1 153 1 view .LVU50
 194              		@ sp needed
 195 0010 7047     		bx	lr
 196              	.L9:
 197 0012 C046     		.align	2
 198              	.L8:
 199 0014 00E100E0 		.word	-536813312
 200              		.cfi_endproc
 201              	.LFE298:
 203              		.section	.text.HAL_NVIC_DisableIRQ,"ax",%progbits
 204              		.align	1
 205              		.global	HAL_NVIC_DisableIRQ
 206              		.syntax unified
 207              		.code	16
 208              		.thumb_func
 209              		.fpu softvfp
 211              	HAL_NVIC_DisableIRQ:
 212              	.LVL14:
 213              	.LFB299:
 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 214              		.loc 1 163 1 is_stmt 1 view -0
 215              		.cfi_startproc
 216              		@ args = 0, pretend = 0, frame = 0
 217              		@ frame_needed = 0, uses_anonymous_args = 0
 218              		@ link register save eliminated.
 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
ARM GAS  /tmp/cc5M7qsZ.s 			page 23


 219              		.loc 1 165 3 view .LVU52
 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Disable interrupt */
 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   NVIC_DisableIRQ(IRQn);
 220              		.loc 1 168 3 view .LVU53
 221              	.LBB40:
 222              	.LBI40:
 779:Drivers/CMSIS/Include/core_cm0plus.h **** {
 223              		.loc 2 779 22 view .LVU54
 224              	.LBB41:
 781:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 225              		.loc 2 781 3 view .LVU55
 781:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 226              		.loc 2 781 6 is_stmt 0 view .LVU56
 227 0000 0028     		cmp	r0, #0
 228 0002 0ADB     		blt	.L10
 783:Drivers/CMSIS/Include/core_cm0plus.h ****     __DSB();
 229              		.loc 2 783 5 is_stmt 1 view .LVU57
 783:Drivers/CMSIS/Include/core_cm0plus.h ****     __DSB();
 230              		.loc 2 783 58 is_stmt 0 view .LVU58
 231 0004 1F23     		movs	r3, #31
 232 0006 1840     		ands	r0, r3
 233              	.LVL15:
 783:Drivers/CMSIS/Include/core_cm0plus.h ****     __DSB();
 234              		.loc 2 783 22 view .LVU59
 235 0008 1E3B     		subs	r3, r3, #30
 236 000a 8340     		lsls	r3, r3, r0
 783:Drivers/CMSIS/Include/core_cm0plus.h ****     __DSB();
 237              		.loc 2 783 20 view .LVU60
 238 000c 0349     		ldr	r1, .L12
 239 000e 8022     		movs	r2, #128
 240 0010 8B50     		str	r3, [r1, r2]
 784:Drivers/CMSIS/Include/core_cm0plus.h ****     __ISB();
 241              		.loc 2 784 5 is_stmt 1 view .LVU61
 242              	.LBB42:
 243              	.LBI42:
 244              		.file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ARM GAS  /tmp/cc5M7qsZ.s 			page 24


  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS  /tmp/cc5M7qsZ.s 			page 25


  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
ARM GAS  /tmp/cc5M7qsZ.s 			page 26


 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS  /tmp/cc5M7qsZ.s 			page 27


 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
ARM GAS  /tmp/cc5M7qsZ.s 			page 28


 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
ARM GAS  /tmp/cc5M7qsZ.s 			page 29


 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/cc5M7qsZ.s 			page 30


 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
ARM GAS  /tmp/cc5M7qsZ.s 			page 31


 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
ARM GAS  /tmp/cc5M7qsZ.s 			page 32


 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
ARM GAS  /tmp/cc5M7qsZ.s 			page 33


 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
ARM GAS  /tmp/cc5M7qsZ.s 			page 34


 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
ARM GAS  /tmp/cc5M7qsZ.s 			page 35


 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
ARM GAS  /tmp/cc5M7qsZ.s 			page 36


 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS  /tmp/cc5M7qsZ.s 			page 37


 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
ARM GAS  /tmp/cc5M7qsZ.s 			page 38


 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  /tmp/cc5M7qsZ.s 			page 39


 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
ARM GAS  /tmp/cc5M7qsZ.s 			page 40


 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 245              		.loc 3 944 27 view .LVU62
 246              	.LBB43:
 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 247              		.loc 3 946 3 view .LVU63
 248              		.syntax divided
 249              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 250 0012 BFF34F8F 		dsb 0xF
 251              	@ 0 "" 2
 252              		.thumb
 253              		.syntax unified
 254              	.LBE43:
 255              	.LBE42:
 785:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 256              		.loc 2 785 5 view .LVU64
 257              	.LBB44:
 258              	.LBI44:
 933:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 259              		.loc 3 933 27 view .LVU65
 260              	.LBB45:
 935:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 261              		.loc 3 935 3 view .LVU66
 262              		.syntax divided
 263              	@ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 264 0016 BFF36F8F 		isb 0xF
 265              	@ 0 "" 2
 266              	.LVL16:
 267              		.thumb
 268              		.syntax unified
 269              	.L10:
 935:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 270              		.loc 3 935 3 is_stmt 0 view .LVU67
 271              	.LBE45:
 272              	.LBE44:
 273              	.LBE41:
 274              	.LBE40:
 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 275              		.loc 1 169 1 view .LVU68
 276              		@ sp needed
 277 001a 7047     		bx	lr
 278              	.L13:
 279              		.align	2
 280              	.L12:
 281 001c 00E100E0 		.word	-536813312
 282              		.cfi_endproc
ARM GAS  /tmp/cc5M7qsZ.s 			page 41


 283              	.LFE299:
 285              		.section	.text.HAL_NVIC_SystemReset,"ax",%progbits
 286              		.align	1
 287              		.global	HAL_NVIC_SystemReset
 288              		.syntax unified
 289              		.code	16
 290              		.thumb_func
 291              		.fpu softvfp
 293              	HAL_NVIC_SystemReset:
 294              	.LFB300:
 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Initiate a system reset request to reset the MCU.
 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 295              		.loc 1 176 1 is_stmt 1 view -0
 296              		.cfi_startproc
 297              		@ Volatile: function does not return.
 298              		@ args = 0, pretend = 0, frame = 0
 299              		@ frame_needed = 0, uses_anonymous_args = 0
 300              		@ link register save eliminated.
 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* System Reset */
 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   NVIC_SystemReset();
 301              		.loc 1 178 3 view .LVU70
 302              	.LBB52:
 303              	.LBI52:
 861:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 862:Drivers/CMSIS/Include/core_cm0plus.h **** }
 863:Drivers/CMSIS/Include/core_cm0plus.h **** 
 864:Drivers/CMSIS/Include/core_cm0plus.h **** 
 865:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 866:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Get Interrupt Priority
 867:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
 868:Drivers/CMSIS/Include/core_cm0plus.h ****            The interrupt number can be positive to specify a device specific interrupt,
 869:Drivers/CMSIS/Include/core_cm0plus.h ****            or negative to specify a processor exception.
 870:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]   IRQn  Interrupt number.
 871:Drivers/CMSIS/Include/core_cm0plus.h ****   \return             Interrupt Priority.
 872:Drivers/CMSIS/Include/core_cm0plus.h ****                       Value is aligned automatically to the implemented priority bits of the microc
 873:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 874:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 875:Drivers/CMSIS/Include/core_cm0plus.h **** {
 876:Drivers/CMSIS/Include/core_cm0plus.h **** 
 877:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((int32_t)(IRQn) >= 0)
 878:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 879:Drivers/CMSIS/Include/core_cm0plus.h ****     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 880:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 881:Drivers/CMSIS/Include/core_cm0plus.h ****   else
 882:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 883:Drivers/CMSIS/Include/core_cm0plus.h ****     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 884:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 885:Drivers/CMSIS/Include/core_cm0plus.h **** }
 886:Drivers/CMSIS/Include/core_cm0plus.h **** 
 887:Drivers/CMSIS/Include/core_cm0plus.h **** 
 888:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 889:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Encode Priority
ARM GAS  /tmp/cc5M7qsZ.s 			page 42


 890:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Encodes the priority for an interrupt with the given priority group,
 891:Drivers/CMSIS/Include/core_cm0plus.h ****            preemptive priority value, and subpriority value.
 892:Drivers/CMSIS/Include/core_cm0plus.h ****            In case of a conflict between priority grouping and available
 893:Drivers/CMSIS/Include/core_cm0plus.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 894:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]     PriorityGroup  Used priority group.
 895:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
 896:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
 897:Drivers/CMSIS/Include/core_cm0plus.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
 898:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 899:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
 900:Drivers/CMSIS/Include/core_cm0plus.h **** {
 901:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 902:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t PreemptPriorityBits;
 903:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t SubPriorityBits;
 904:Drivers/CMSIS/Include/core_cm0plus.h **** 
 905:Drivers/CMSIS/Include/core_cm0plus.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 906:Drivers/CMSIS/Include/core_cm0plus.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 907:Drivers/CMSIS/Include/core_cm0plus.h **** 
 908:Drivers/CMSIS/Include/core_cm0plus.h ****   return (
 909:Drivers/CMSIS/Include/core_cm0plus.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 910:Drivers/CMSIS/Include/core_cm0plus.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 911:Drivers/CMSIS/Include/core_cm0plus.h ****          );
 912:Drivers/CMSIS/Include/core_cm0plus.h **** }
 913:Drivers/CMSIS/Include/core_cm0plus.h **** 
 914:Drivers/CMSIS/Include/core_cm0plus.h **** 
 915:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 916:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Decode Priority
 917:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Decodes an interrupt priority value with a given priority group to
 918:Drivers/CMSIS/Include/core_cm0plus.h ****            preemptive priority value and subpriority value.
 919:Drivers/CMSIS/Include/core_cm0plus.h ****            In case of a conflict between priority grouping and available
 920:Drivers/CMSIS/Include/core_cm0plus.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
 921:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
 922:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]     PriorityGroup  Used priority group.
 923:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
 924:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
 925:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 926:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
 927:Drivers/CMSIS/Include/core_cm0plus.h **** {
 928:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 929:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t PreemptPriorityBits;
 930:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t SubPriorityBits;
 931:Drivers/CMSIS/Include/core_cm0plus.h **** 
 932:Drivers/CMSIS/Include/core_cm0plus.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 933:Drivers/CMSIS/Include/core_cm0plus.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 934:Drivers/CMSIS/Include/core_cm0plus.h **** 
 935:Drivers/CMSIS/Include/core_cm0plus.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
 936:Drivers/CMSIS/Include/core_cm0plus.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 937:Drivers/CMSIS/Include/core_cm0plus.h **** }
 938:Drivers/CMSIS/Include/core_cm0plus.h **** 
 939:Drivers/CMSIS/Include/core_cm0plus.h **** 
 940:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 941:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Set Interrupt Vector
 942:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
 943:Drivers/CMSIS/Include/core_cm0plus.h ****            The interrupt number can be positive to specify a device specific interrupt,
 944:Drivers/CMSIS/Include/core_cm0plus.h ****            or negative to specify a processor exception.
 945:Drivers/CMSIS/Include/core_cm0plus.h ****            VTOR must been relocated to SRAM before.
 946:Drivers/CMSIS/Include/core_cm0plus.h ****            If VTOR is not present address 0 must be mapped to SRAM.
ARM GAS  /tmp/cc5M7qsZ.s 			page 43


 947:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]   IRQn      Interrupt number
 948:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]   vector    Address of interrupt handler function
 949:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 950:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 951:Drivers/CMSIS/Include/core_cm0plus.h **** {
 952:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
 953:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t vectors = SCB->VTOR;
 954:Drivers/CMSIS/Include/core_cm0plus.h **** #else
 955:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t vectors = 0x0U;
 956:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 957:Drivers/CMSIS/Include/core_cm0plus.h ****   (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
 958:Drivers/CMSIS/Include/core_cm0plus.h ****   /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
 959:Drivers/CMSIS/Include/core_cm0plus.h **** }
 960:Drivers/CMSIS/Include/core_cm0plus.h **** 
 961:Drivers/CMSIS/Include/core_cm0plus.h **** 
 962:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 963:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   Get Interrupt Vector
 964:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Reads an interrupt vector from interrupt vector table.
 965:Drivers/CMSIS/Include/core_cm0plus.h ****            The interrupt number can be positive to specify a device specific interrupt,
 966:Drivers/CMSIS/Include/core_cm0plus.h ****            or negative to specify a processor exception.
 967:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]   IRQn      Interrupt number.
 968:Drivers/CMSIS/Include/core_cm0plus.h ****   \return                 Address of interrupt handler function
 969:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 970:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 971:Drivers/CMSIS/Include/core_cm0plus.h **** {
 972:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
 973:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t vectors = SCB->VTOR;
 974:Drivers/CMSIS/Include/core_cm0plus.h **** #else
 975:Drivers/CMSIS/Include/core_cm0plus.h ****   uint32_t vectors = 0x0U;
 976:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
 977:Drivers/CMSIS/Include/core_cm0plus.h ****   return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
 978:Drivers/CMSIS/Include/core_cm0plus.h **** }
 979:Drivers/CMSIS/Include/core_cm0plus.h **** 
 980:Drivers/CMSIS/Include/core_cm0plus.h **** 
 981:Drivers/CMSIS/Include/core_cm0plus.h **** /**
 982:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   System Reset
 983:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Initiates a system reset request to reset the MCU.
 984:Drivers/CMSIS/Include/core_cm0plus.h ****  */
 985:Drivers/CMSIS/Include/core_cm0plus.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 304              		.loc 2 985 34 view .LVU71
 305              	.LBB53:
 986:Drivers/CMSIS/Include/core_cm0plus.h **** {
 987:Drivers/CMSIS/Include/core_cm0plus.h ****   __DSB();                                                          /* Ensure all outstanding memor
 306              		.loc 2 987 3 view .LVU72
 307              	.LBB54:
 308              	.LBI54:
 944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 309              		.loc 3 944 27 view .LVU73
 310              	.LBB55:
 311              		.loc 3 946 3 view .LVU74
 312              		.syntax divided
 313              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 314 0000 BFF34F8F 		dsb 0xF
 315              	@ 0 "" 2
 316              		.thumb
 317              		.syntax unified
 318              	.LBE55:
ARM GAS  /tmp/cc5M7qsZ.s 			page 44


 319              	.LBE54:
 988:Drivers/CMSIS/Include/core_cm0plus.h ****                                                                        buffered write are completed
 989:Drivers/CMSIS/Include/core_cm0plus.h ****   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 320              		.loc 2 989 3 view .LVU75
 321              		.loc 2 989 15 is_stmt 0 view .LVU76
 322 0004 034B     		ldr	r3, .L16
 323 0006 044A     		ldr	r2, .L16+4
 324 0008 DA60     		str	r2, [r3, #12]
 990:Drivers/CMSIS/Include/core_cm0plus.h ****                  SCB_AIRCR_SYSRESETREQ_Msk);
 991:Drivers/CMSIS/Include/core_cm0plus.h ****   __DSB();                                                          /* Ensure completion of memory 
 325              		.loc 2 991 3 is_stmt 1 view .LVU77
 326              	.LBB56:
 327              	.LBI56:
 944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 328              		.loc 3 944 27 view .LVU78
 329              	.LBB57:
 330              		.loc 3 946 3 view .LVU79
 331              		.syntax divided
 332              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 333 000a BFF34F8F 		dsb 0xF
 334              	@ 0 "" 2
 335              		.thumb
 336              		.syntax unified
 337              	.L15:
 338              	.LBE57:
 339              	.LBE56:
 992:Drivers/CMSIS/Include/core_cm0plus.h **** 
 993:Drivers/CMSIS/Include/core_cm0plus.h ****   for(;;)                                                           /* wait until reset */
 340              		.loc 2 993 3 view .LVU80
 994:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 995:Drivers/CMSIS/Include/core_cm0plus.h ****     __NOP();
 341              		.loc 2 995 5 view .LVU81
 342              		.syntax divided
 343              	@ 995 "Drivers/CMSIS/Include/core_cm0plus.h" 1
 344 000e C046     		nop
 345              	@ 0 "" 2
 993:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 346              		.loc 2 993 8 view .LVU82
 347              		.thumb
 348              		.syntax unified
 349 0010 FDE7     		b	.L15
 350              	.L17:
 351 0012 C046     		.align	2
 352              	.L16:
 353 0014 00ED00E0 		.word	-536810240
 354 0018 0400FA05 		.word	100270084
 355              	.LBE53:
 356              	.LBE52:
 357              		.cfi_endproc
 358              	.LFE300:
 360              		.section	.text.HAL_SYSTICK_Config,"ax",%progbits
 361              		.align	1
 362              		.global	HAL_SYSTICK_Config
 363              		.syntax unified
 364              		.code	16
 365              		.thumb_func
 366              		.fpu softvfp
ARM GAS  /tmp/cc5M7qsZ.s 			page 45


 368              	HAL_SYSTICK_Config:
 369              	.LVL17:
 370              	.LFB301:
 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (Sys
 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         Counter is in free running mode to generate periodic interrupts.
 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval status:  - 0  Function succeeded.
 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *                  - 1  Function failed.
 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 371              		.loc 1 189 1 view -0
 372              		.cfi_startproc
 373              		@ args = 0, pretend = 0, frame = 0
 374              		@ frame_needed = 0, uses_anonymous_args = 0
 375              		@ link register save eliminated.
 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   return SysTick_Config(TicksNumb);
 376              		.loc 1 190 3 view .LVU84
 377              	.LBB62:
 378              	.LBI62:
 996:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 997:Drivers/CMSIS/Include/core_cm0plus.h **** }
 998:Drivers/CMSIS/Include/core_cm0plus.h **** 
 999:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of CMSIS_Core_NVICFunctions */
1000:Drivers/CMSIS/Include/core_cm0plus.h **** 
1001:Drivers/CMSIS/Include/core_cm0plus.h **** /* ##########################  MPU functions  #################################### */
1002:Drivers/CMSIS/Include/core_cm0plus.h **** 
1003:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1004:Drivers/CMSIS/Include/core_cm0plus.h **** 
1005:Drivers/CMSIS/Include/core_cm0plus.h **** #include "mpu_armv7.h"
1006:Drivers/CMSIS/Include/core_cm0plus.h **** 
1007:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
1008:Drivers/CMSIS/Include/core_cm0plus.h **** 
1009:Drivers/CMSIS/Include/core_cm0plus.h **** /* ##########################  FPU functions  #################################### */
1010:Drivers/CMSIS/Include/core_cm0plus.h **** /**
1011:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup  CMSIS_Core_FunctionInterface
1012:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_Core_FpuFunctions FPU Functions
1013:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief    Function that provides FPU type.
1014:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
1015:Drivers/CMSIS/Include/core_cm0plus.h ****  */
1016:Drivers/CMSIS/Include/core_cm0plus.h **** 
1017:Drivers/CMSIS/Include/core_cm0plus.h **** /**
1018:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   get FPU type
1019:Drivers/CMSIS/Include/core_cm0plus.h ****   \details returns the FPU type
1020:Drivers/CMSIS/Include/core_cm0plus.h ****   \returns
1021:Drivers/CMSIS/Include/core_cm0plus.h ****    - \b  0: No FPU
1022:Drivers/CMSIS/Include/core_cm0plus.h ****    - \b  1: Single precision FPU
1023:Drivers/CMSIS/Include/core_cm0plus.h ****    - \b  2: Double + Single precision FPU
1024:Drivers/CMSIS/Include/core_cm0plus.h ****  */
1025:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1026:Drivers/CMSIS/Include/core_cm0plus.h **** {
1027:Drivers/CMSIS/Include/core_cm0plus.h ****     return 0U;           /* No FPU */
1028:Drivers/CMSIS/Include/core_cm0plus.h **** }
1029:Drivers/CMSIS/Include/core_cm0plus.h **** 
ARM GAS  /tmp/cc5M7qsZ.s 			page 46


1030:Drivers/CMSIS/Include/core_cm0plus.h **** 
1031:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of CMSIS_Core_FpuFunctions */
1032:Drivers/CMSIS/Include/core_cm0plus.h **** 
1033:Drivers/CMSIS/Include/core_cm0plus.h **** 
1034:Drivers/CMSIS/Include/core_cm0plus.h **** 
1035:Drivers/CMSIS/Include/core_cm0plus.h **** /* ##################################    SysTick function  ########################################
1036:Drivers/CMSIS/Include/core_cm0plus.h **** /**
1037:Drivers/CMSIS/Include/core_cm0plus.h ****   \ingroup  CMSIS_Core_FunctionInterface
1038:Drivers/CMSIS/Include/core_cm0plus.h ****   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1039:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief    Functions that configure the System.
1040:Drivers/CMSIS/Include/core_cm0plus.h ****   @{
1041:Drivers/CMSIS/Include/core_cm0plus.h ****  */
1042:Drivers/CMSIS/Include/core_cm0plus.h **** 
1043:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1044:Drivers/CMSIS/Include/core_cm0plus.h **** 
1045:Drivers/CMSIS/Include/core_cm0plus.h **** /**
1046:Drivers/CMSIS/Include/core_cm0plus.h ****   \brief   System Tick Configuration
1047:Drivers/CMSIS/Include/core_cm0plus.h ****   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1048:Drivers/CMSIS/Include/core_cm0plus.h ****            Counter is in free running mode to generate periodic interrupts.
1049:Drivers/CMSIS/Include/core_cm0plus.h ****   \param [in]  ticks  Number of ticks between two interrupts.
1050:Drivers/CMSIS/Include/core_cm0plus.h ****   \return          0  Function succeeded.
1051:Drivers/CMSIS/Include/core_cm0plus.h ****   \return          1  Function failed.
1052:Drivers/CMSIS/Include/core_cm0plus.h ****   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1053:Drivers/CMSIS/Include/core_cm0plus.h ****            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
1054:Drivers/CMSIS/Include/core_cm0plus.h ****            must contain a vendor-specific implementation of this function.
1055:Drivers/CMSIS/Include/core_cm0plus.h ****  */
1056:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 379              		.loc 2 1056 26 view .LVU85
 380              	.LBB63:
1057:Drivers/CMSIS/Include/core_cm0plus.h **** {
1058:Drivers/CMSIS/Include/core_cm0plus.h ****   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 381              		.loc 2 1058 3 view .LVU86
 382              		.loc 2 1058 14 is_stmt 0 view .LVU87
 383 0000 0138     		subs	r0, r0, #1
 384              	.LVL18:
 385              		.loc 2 1058 6 view .LVU88
 386 0002 8023     		movs	r3, #128
 387 0004 5B04     		lsls	r3, r3, #17
 388 0006 9842     		cmp	r0, r3
 389 0008 0FD2     		bcs	.L20
1059:Drivers/CMSIS/Include/core_cm0plus.h ****   {
1060:Drivers/CMSIS/Include/core_cm0plus.h ****     return (1UL);                                                   /* Reload value impossible */
1061:Drivers/CMSIS/Include/core_cm0plus.h ****   }
1062:Drivers/CMSIS/Include/core_cm0plus.h **** 
1063:Drivers/CMSIS/Include/core_cm0plus.h ****   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 390              		.loc 2 1063 3 is_stmt 1 view .LVU89
 391              		.loc 2 1063 18 is_stmt 0 view .LVU90
 392 000a 094A     		ldr	r2, .L21
 393 000c 5060     		str	r0, [r2, #4]
1064:Drivers/CMSIS/Include/core_cm0plus.h ****   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
 394              		.loc 2 1064 3 is_stmt 1 view .LVU91
 395              	.LVL19:
 396              	.LBB64:
 397              	.LBI64:
 850:Drivers/CMSIS/Include/core_cm0plus.h **** {
 398              		.loc 2 850 22 view .LVU92
 399              	.LBB65:
ARM GAS  /tmp/cc5M7qsZ.s 			page 47


 852:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 400              		.loc 2 852 3 view .LVU93
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 401              		.loc 2 859 5 view .LVU94
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 402              		.loc 2 859 52 is_stmt 0 view .LVU95
 403 000e 0948     		ldr	r0, .L21+4
 404              	.LVL20:
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 405              		.loc 2 859 52 view .LVU96
 406 0010 036A     		ldr	r3, [r0, #32]
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 407              		.loc 2 859 33 view .LVU97
 408 0012 1B02     		lsls	r3, r3, #8
 409 0014 1B0A     		lsrs	r3, r3, #8
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 410              		.loc 2 859 102 view .LVU98
 411 0016 C021     		movs	r1, #192
 412 0018 0906     		lsls	r1, r1, #24
 413 001a 0B43     		orrs	r3, r1
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 414              		.loc 2 859 30 view .LVU99
 415 001c 0362     		str	r3, [r0, #32]
 416              	.LVL21:
 859:Drivers/CMSIS/Include/core_cm0plus.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 417              		.loc 2 859 30 view .LVU100
 418              	.LBE65:
 419              	.LBE64:
1065:Drivers/CMSIS/Include/core_cm0plus.h ****   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Val
 420              		.loc 2 1065 3 is_stmt 1 view .LVU101
 421              		.loc 2 1065 18 is_stmt 0 view .LVU102
 422 001e 0023     		movs	r3, #0
 423 0020 9360     		str	r3, [r2, #8]
1066:Drivers/CMSIS/Include/core_cm0plus.h ****   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 424              		.loc 2 1066 3 is_stmt 1 view .LVU103
 425              		.loc 2 1066 18 is_stmt 0 view .LVU104
 426 0022 0733     		adds	r3, r3, #7
 427 0024 1360     		str	r3, [r2]
1067:Drivers/CMSIS/Include/core_cm0plus.h ****                    SysTick_CTRL_TICKINT_Msk   |
1068:Drivers/CMSIS/Include/core_cm0plus.h ****                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTi
1069:Drivers/CMSIS/Include/core_cm0plus.h ****   return (0UL);                                                     /* Function successful */
 428              		.loc 2 1069 3 is_stmt 1 view .LVU105
 429              		.loc 2 1069 10 is_stmt 0 view .LVU106
 430 0026 0020     		movs	r0, #0
 431              	.LVL22:
 432              	.L18:
 433              		.loc 2 1069 10 view .LVU107
 434              	.LBE63:
 435              	.LBE62:
 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 436              		.loc 1 191 1 view .LVU108
 437              		@ sp needed
 438 0028 7047     		bx	lr
 439              	.LVL23:
 440              	.L20:
 441              	.LBB67:
 442              	.LBB66:
ARM GAS  /tmp/cc5M7qsZ.s 			page 48


1060:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 443              		.loc 2 1060 12 view .LVU109
 444 002a 0120     		movs	r0, #1
 445              	.LVL24:
1060:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 446              		.loc 2 1060 12 view .LVU110
 447              	.LBE66:
 448              	.LBE67:
 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 449              		.loc 1 190 10 view .LVU111
 450 002c FCE7     		b	.L18
 451              	.L22:
 452 002e C046     		.align	2
 453              	.L21:
 454 0030 10E000E0 		.word	-536813552
 455 0034 00ED00E0 		.word	-536810240
 456              		.cfi_endproc
 457              	.LFE301:
 459              		.section	.text.HAL_NVIC_GetPriority,"ax",%progbits
 460              		.align	1
 461              		.global	HAL_NVIC_GetPriority
 462              		.syntax unified
 463              		.code	16
 464              		.thumb_func
 465              		.fpu softvfp
 467              	HAL_NVIC_GetPriority:
 468              	.LVL25:
 469              	.LFB302:
 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @}
 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group2
 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****  *  @brief   Cortex control functions
 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****  *
 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @verbatim
 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ==============================================================================
 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                       ##### Peripheral Control functions #####
 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   ==============================================================================
 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     [..]
 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       This subsection provides a set of functions allowing to control the CORTEX
 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****       (NVIC, SYSTICK, MPU) functionalities.
 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @endverbatim
 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @{
 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Get the priority of an interrupt.
 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
ARM GAS  /tmp/cc5M7qsZ.s 			page 49


 470              		.loc 1 220 1 is_stmt 1 view -0
 471              		.cfi_startproc
 472              		@ args = 0, pretend = 0, frame = 0
 473              		@ frame_needed = 0, uses_anonymous_args = 0
 474              		@ link register save eliminated.
 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Get priority for Cortex-M system or device specific interrupts */
 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   return NVIC_GetPriority(IRQn);
 475              		.loc 1 222 3 view .LVU113
 476              	.LBB70:
 477              	.LBI70:
 874:Drivers/CMSIS/Include/core_cm0plus.h **** {
 478              		.loc 2 874 26 view .LVU114
 479              	.LBB71:
 877:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 480              		.loc 2 877 3 view .LVU115
 877:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 481              		.loc 2 877 6 is_stmt 0 view .LVU116
 482 0000 0028     		cmp	r0, #0
 483 0002 0CDB     		blt	.L24
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 484              		.loc 2 879 5 is_stmt 1 view .LVU117
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 485              		.loc 2 879 35 is_stmt 0 view .LVU118
 486 0004 8308     		lsrs	r3, r0, #2
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 487              		.loc 2 879 33 view .LVU119
 488 0006 C033     		adds	r3, r3, #192
 489 0008 9B00     		lsls	r3, r3, #2
 490 000a 0E4A     		ldr	r2, .L26
 491 000c 9B58     		ldr	r3, [r3, r2]
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 492              		.loc 2 879 53 view .LVU120
 493 000e 0322     		movs	r2, #3
 494 0010 1040     		ands	r0, r2
 495              	.LVL26:
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 496              		.loc 2 879 53 view .LVU121
 497 0012 C000     		lsls	r0, r0, #3
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 498              		.loc 2 879 50 view .LVU122
 499 0014 C340     		lsrs	r3, r3, r0
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 500              		.loc 2 879 12 view .LVU123
 501 0016 9B09     		lsrs	r3, r3, #6
 502 0018 0320     		movs	r0, #3
 503 001a 1840     		ands	r0, r3
 504              	.LVL27:
 505              	.L23:
 879:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 506              		.loc 2 879 12 view .LVU124
 507              	.LBE71:
 508              	.LBE70:
 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 509              		.loc 1 223 1 view .LVU125
 510              		@ sp needed
 511 001c 7047     		bx	lr
 512              	.LVL28:
ARM GAS  /tmp/cc5M7qsZ.s 			page 50


 513              	.L24:
 514              	.LBB73:
 515              	.LBB72:
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 516              		.loc 2 883 5 is_stmt 1 view .LVU126
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 517              		.loc 2 883 34 is_stmt 0 view .LVU127
 518 001e 0F23     		movs	r3, #15
 519 0020 0340     		ands	r3, r0
 520 0022 083B     		subs	r3, r3, #8
 521 0024 9B08     		lsrs	r3, r3, #2
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 522              		.loc 2 883 33 view .LVU128
 523 0026 0633     		adds	r3, r3, #6
 524 0028 9B00     		lsls	r3, r3, #2
 525 002a 074A     		ldr	r2, .L26+4
 526 002c 9446     		mov	ip, r2
 527 002e 6344     		add	r3, r3, ip
 528 0030 5B68     		ldr	r3, [r3, #4]
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 529              		.loc 2 883 53 view .LVU129
 530 0032 0322     		movs	r2, #3
 531 0034 1040     		ands	r0, r2
 532              	.LVL29:
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 533              		.loc 2 883 53 view .LVU130
 534 0036 C000     		lsls	r0, r0, #3
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 535              		.loc 2 883 50 view .LVU131
 536 0038 C340     		lsrs	r3, r3, r0
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 537              		.loc 2 883 12 view .LVU132
 538 003a 9B09     		lsrs	r3, r3, #6
 539 003c 0320     		movs	r0, #3
 540 003e 1840     		ands	r0, r3
 541              	.LVL30:
 883:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 542              		.loc 2 883 12 view .LVU133
 543              	.LBE72:
 544              	.LBE73:
 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 545              		.loc 1 222 10 view .LVU134
 546 0040 ECE7     		b	.L23
 547              	.L27:
 548 0042 C046     		.align	2
 549              	.L26:
 550 0044 00E100E0 		.word	-536813312
 551 0048 00ED00E0 		.word	-536810240
 552              		.cfi_endproc
 553              	.LFE302:
 555              		.section	.text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
 556              		.align	1
 557              		.global	HAL_NVIC_SetPendingIRQ
 558              		.syntax unified
 559              		.code	16
 560              		.thumb_func
 561              		.fpu softvfp
ARM GAS  /tmp/cc5M7qsZ.s 			page 51


 563              	HAL_NVIC_SetPendingIRQ:
 564              	.LVL31:
 565              	.LFB303:
 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Set Pending bit of an external interrupt.
 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  IRQn External interrupt number
 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 566              		.loc 1 233 1 is_stmt 1 view -0
 567              		.cfi_startproc
 568              		@ args = 0, pretend = 0, frame = 0
 569              		@ frame_needed = 0, uses_anonymous_args = 0
 570              		@ link register save eliminated.
 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 571              		.loc 1 235 3 view .LVU136
 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Set interrupt pending */
 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   NVIC_SetPendingIRQ(IRQn);
 572              		.loc 1 238 3 view .LVU137
 573              	.LBB74:
 574              	.LBI74:
 817:Drivers/CMSIS/Include/core_cm0plus.h **** {
 575              		.loc 2 817 22 view .LVU138
 576              	.LBB75:
 819:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 577              		.loc 2 819 3 view .LVU139
 819:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 578              		.loc 2 819 6 is_stmt 0 view .LVU140
 579 0000 0028     		cmp	r0, #0
 580 0002 07DB     		blt	.L28
 821:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 581              		.loc 2 821 5 is_stmt 1 view .LVU141
 821:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 582              		.loc 2 821 58 is_stmt 0 view .LVU142
 583 0004 1F23     		movs	r3, #31
 584 0006 1840     		ands	r0, r3
 585              	.LVL32:
 821:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 586              		.loc 2 821 22 view .LVU143
 587 0008 1E3B     		subs	r3, r3, #30
 588 000a 8340     		lsls	r3, r3, r0
 821:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 589              		.loc 2 821 20 view .LVU144
 590 000c 0249     		ldr	r1, .L30
 591 000e 8022     		movs	r2, #128
 592 0010 5200     		lsls	r2, r2, #1
 593 0012 8B50     		str	r3, [r1, r2]
 594              	.LVL33:
 595              	.L28:
 821:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 596              		.loc 2 821 20 view .LVU145
ARM GAS  /tmp/cc5M7qsZ.s 			page 52


 597              	.LBE75:
 598              	.LBE74:
 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 599              		.loc 1 239 1 view .LVU146
 600              		@ sp needed
 601 0014 7047     		bx	lr
 602              	.L31:
 603 0016 C046     		.align	2
 604              	.L30:
 605 0018 00E100E0 		.word	-536813312
 606              		.cfi_endproc
 607              	.LFE303:
 609              		.section	.text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
 610              		.align	1
 611              		.global	HAL_NVIC_GetPendingIRQ
 612              		.syntax unified
 613              		.code	16
 614              		.thumb_func
 615              		.fpu softvfp
 617              	HAL_NVIC_GetPendingIRQ:
 618              	.LVL34:
 619              	.LFB304:
 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Get Pending Interrupt (read the pending register in the NVIC
 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         and return the pending bit for the specified interrupt).
 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval status: - 0  Interrupt status is not pending.
 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *                 - 1  Interrupt status is pending.
 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 620              		.loc 1 251 1 is_stmt 1 view -0
 621              		.cfi_startproc
 622              		@ args = 0, pretend = 0, frame = 0
 623              		@ frame_needed = 0, uses_anonymous_args = 0
 624              		@ link register save eliminated.
 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 625              		.loc 1 253 3 view .LVU148
 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Return 1 if pending else 0 */
 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   return NVIC_GetPendingIRQ(IRQn);
 626              		.loc 1 256 3 view .LVU149
 627              	.LBB76:
 628              	.LBI76:
 798:Drivers/CMSIS/Include/core_cm0plus.h **** {
 629              		.loc 2 798 26 view .LVU150
 630              	.LBB77:
 800:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 631              		.loc 2 800 3 view .LVU151
 800:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 632              		.loc 2 800 6 is_stmt 0 view .LVU152
 633 0000 0028     		cmp	r0, #0
 634 0002 09DB     		blt	.L34
ARM GAS  /tmp/cc5M7qsZ.s 			page 53


 802:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 635              		.loc 2 802 5 is_stmt 1 view .LVU153
 802:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 636              		.loc 2 802 35 is_stmt 0 view .LVU154
 637 0004 054A     		ldr	r2, .L35
 638 0006 8023     		movs	r3, #128
 639 0008 5B00     		lsls	r3, r3, #1
 640 000a D358     		ldr	r3, [r2, r3]
 802:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 641              		.loc 2 802 68 view .LVU155
 642 000c 1F22     		movs	r2, #31
 643 000e 1040     		ands	r0, r2
 644              	.LVL35:
 802:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 645              		.loc 2 802 80 view .LVU156
 646 0010 C340     		lsrs	r3, r3, r0
 802:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 647              		.loc 2 802 12 view .LVU157
 648 0012 0120     		movs	r0, #1
 649 0014 1840     		ands	r0, r3
 650              	.LVL36:
 651              	.L32:
 802:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 652              		.loc 2 802 12 view .LVU158
 653              	.LBE77:
 654              	.LBE76:
 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 655              		.loc 1 257 1 view .LVU159
 656              		@ sp needed
 657 0016 7047     		bx	lr
 658              	.LVL37:
 659              	.L34:
 660              	.LBB79:
 661              	.LBB78:
 806:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 662              		.loc 2 806 11 view .LVU160
 663 0018 0020     		movs	r0, #0
 664              	.LVL38:
 806:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 665              		.loc 2 806 11 view .LVU161
 666              	.LBE78:
 667              	.LBE79:
 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 668              		.loc 1 256 10 view .LVU162
 669 001a FCE7     		b	.L32
 670              	.L36:
 671              		.align	2
 672              	.L35:
 673 001c 00E100E0 		.word	-536813312
 674              		.cfi_endproc
 675              	.LFE304:
 677              		.section	.text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
 678              		.align	1
 679              		.global	HAL_NVIC_ClearPendingIRQ
 680              		.syntax unified
 681              		.code	16
 682              		.thumb_func
ARM GAS  /tmp/cc5M7qsZ.s 			page 54


 683              		.fpu softvfp
 685              	HAL_NVIC_ClearPendingIRQ:
 686              	.LVL39:
 687              	.LFB305:
 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Clear the pending bit of an external interrupt.
 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  IRQn External interrupt number.
 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be an enumerator of IRQn_Type enumeration
 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 688              		.loc 1 267 1 is_stmt 1 view -0
 689              		.cfi_startproc
 690              		@ args = 0, pretend = 0, frame = 0
 691              		@ frame_needed = 0, uses_anonymous_args = 0
 692              		@ link register save eliminated.
 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 693              		.loc 1 269 3 view .LVU164
 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Clear pending interrupt */
 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   NVIC_ClearPendingIRQ(IRQn);
 694              		.loc 1 272 3 view .LVU165
 695              	.LBB80:
 696              	.LBI80:
 832:Drivers/CMSIS/Include/core_cm0plus.h **** {
 697              		.loc 2 832 22 view .LVU166
 698              	.LBB81:
 834:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 699              		.loc 2 834 3 view .LVU167
 834:Drivers/CMSIS/Include/core_cm0plus.h ****   {
 700              		.loc 2 834 6 is_stmt 0 view .LVU168
 701 0000 0028     		cmp	r0, #0
 702 0002 07DB     		blt	.L37
 836:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 703              		.loc 2 836 5 is_stmt 1 view .LVU169
 836:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 704              		.loc 2 836 58 is_stmt 0 view .LVU170
 705 0004 1F23     		movs	r3, #31
 706 0006 1840     		ands	r0, r3
 707              	.LVL40:
 836:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 708              		.loc 2 836 22 view .LVU171
 709 0008 1E3B     		subs	r3, r3, #30
 710 000a 8340     		lsls	r3, r3, r0
 836:Drivers/CMSIS/Include/core_cm0plus.h ****   }
 711              		.loc 2 836 20 view .LVU172
 712 000c 0249     		ldr	r1, .L39
 713 000e C022     		movs	r2, #192
 714 0010 5200     		lsls	r2, r2, #1
 715 0012 8B50     		str	r3, [r1, r2]
 716              	.LVL41:
 717              	.L37:
 836:Drivers/CMSIS/Include/core_cm0plus.h ****   }
ARM GAS  /tmp/cc5M7qsZ.s 			page 55


 718              		.loc 2 836 20 view .LVU173
 719              	.LBE81:
 720              	.LBE80:
 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 721              		.loc 1 273 1 view .LVU174
 722              		@ sp needed
 723 0014 7047     		bx	lr
 724              	.L40:
 725 0016 C046     		.align	2
 726              	.L39:
 727 0018 00E100E0 		.word	-536813312
 728              		.cfi_endproc
 729              	.LFE305:
 731              		.section	.text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
 732              		.align	1
 733              		.global	HAL_SYSTICK_CLKSourceConfig
 734              		.syntax unified
 735              		.code	16
 736              		.thumb_func
 737              		.fpu softvfp
 739              	HAL_SYSTICK_CLKSourceConfig:
 740              	.LVL42:
 741              	.LFB306:
 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Configure the SysTick clock source.
 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param CLKSource specifies the SysTick clock source.
 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *         This parameter can be one of the following values:
 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 
 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 742              		.loc 1 284 1 is_stmt 1 view -0
 743              		.cfi_startproc
 744              		@ args = 0, pretend = 0, frame = 0
 745              		@ frame_needed = 0, uses_anonymous_args = 0
 746              		@ link register save eliminated.
 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
 747              		.loc 1 286 3 view .LVU176
 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
 748              		.loc 1 287 3 view .LVU177
 749              		.loc 1 287 6 is_stmt 0 view .LVU178
 750 0000 0428     		cmp	r0, #4
 751 0002 05D0     		beq	.L44
 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   {
 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   else
 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   {
 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
 752              		.loc 1 293 5 is_stmt 1 view .LVU179
 753              		.loc 1 293 19 is_stmt 0 view .LVU180
 754 0004 054A     		ldr	r2, .L45
 755 0006 1368     		ldr	r3, [r2]
ARM GAS  /tmp/cc5M7qsZ.s 			page 56


 756 0008 0421     		movs	r1, #4
 757 000a 8B43     		bics	r3, r1
 758 000c 1360     		str	r3, [r2]
 759              	.L41:
 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 760              		.loc 1 295 1 view .LVU181
 761              		@ sp needed
 762 000e 7047     		bx	lr
 763              	.L44:
 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 764              		.loc 1 289 5 is_stmt 1 view .LVU182
 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 765              		.loc 1 289 19 is_stmt 0 view .LVU183
 766 0010 024A     		ldr	r2, .L45
 767 0012 1368     		ldr	r3, [r2]
 768 0014 0421     		movs	r1, #4
 769 0016 0B43     		orrs	r3, r1
 770 0018 1360     		str	r3, [r2]
 771 001a F8E7     		b	.L41
 772              	.L46:
 773              		.align	2
 774              	.L45:
 775 001c 10E000E0 		.word	-536813552
 776              		.cfi_endproc
 777              	.LFE306:
 779              		.section	.text.HAL_SYSTICK_Callback,"ax",%progbits
 780              		.align	1
 781              		.weak	HAL_SYSTICK_Callback
 782              		.syntax unified
 783              		.code	16
 784              		.thumb_func
 785              		.fpu softvfp
 787              	HAL_SYSTICK_Callback:
 788              	.LFB308:
 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Handle SYSTICK interrupt request.
 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  SYSTICK callback.
 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 789              		.loc 1 311 1 is_stmt 1 view -0
 790              		.cfi_startproc
 791              		@ args = 0, pretend = 0, frame = 0
 792              		@ frame_needed = 0, uses_anonymous_args = 0
 793              		@ link register save eliminated.
 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
ARM GAS  /tmp/cc5M7qsZ.s 			page 57


 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****             the HAL_SYSTICK_Callback could be implemented in the user file
 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****    */
 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 794              		.loc 1 315 1 view .LVU185
 795              		@ sp needed
 796 0000 7047     		bx	lr
 797              		.cfi_endproc
 798              	.LFE308:
 800              		.section	.text.HAL_SYSTICK_IRQHandler,"ax",%progbits
 801              		.align	1
 802              		.global	HAL_SYSTICK_IRQHandler
 803              		.syntax unified
 804              		.code	16
 805              		.thumb_func
 806              		.fpu softvfp
 808              	HAL_SYSTICK_IRQHandler:
 809              	.LFB307:
 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   HAL_SYSTICK_Callback();
 810              		.loc 1 302 1 view -0
 811              		.cfi_startproc
 812              		@ args = 0, pretend = 0, frame = 0
 813              		@ frame_needed = 0, uses_anonymous_args = 0
 814 0000 10B5     		push	{r4, lr}
 815              	.LCFI1:
 816              		.cfi_def_cfa_offset 8
 817              		.cfi_offset 4, -8
 818              		.cfi_offset 14, -4
 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 819              		.loc 1 303 3 view .LVU187
 820 0002 FFF7FEFF 		bl	HAL_SYSTICK_Callback
 821              	.LVL43:
 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 822              		.loc 1 304 1 is_stmt 0 view .LVU188
 823              		@ sp needed
 824 0006 10BD     		pop	{r4, pc}
 825              		.cfi_endproc
 826              	.LFE307:
 828              		.section	.text.HAL_MPU_Enable,"ax",%progbits
 829              		.align	1
 830              		.global	HAL_MPU_Enable
 831              		.syntax unified
 832              		.code	16
 833              		.thumb_func
 834              		.fpu softvfp
 836              	HAL_MPU_Enable:
 837              	.LVL44:
 838              	.LFB309:
 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U)
 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Enable the MPU.
 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *          NMI, FAULTMASK and privileged access to the default memory
 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *          This parameter can be one of the following values:
 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF_NONE
 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *            @arg MPU_HARDFAULT_NMI
 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *            @arg MPU_PRIVILEGED_DEFAULT
ARM GAS  /tmp/cc5M7qsZ.s 			page 58


 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *            @arg MPU_HFNMI_PRIVDEF
 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control)
 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 839              		.loc 1 330 1 is_stmt 1 view -0
 840              		.cfi_startproc
 841              		@ args = 0, pretend = 0, frame = 0
 842              		@ frame_needed = 0, uses_anonymous_args = 0
 843              		@ link register save eliminated.
 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Enable the MPU */
 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
 844              		.loc 1 332 3 view .LVU190
 845              		.loc 1 332 28 is_stmt 0 view .LVU191
 846 0000 0123     		movs	r3, #1
 847 0002 1843     		orrs	r0, r3
 848              	.LVL45:
 849              		.loc 1 332 13 view .LVU192
 850 0004 034B     		ldr	r3, .L50
 851 0006 5860     		str	r0, [r3, #4]
 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Ensure MPU setting take effects */
 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   __DSB();
 852              		.loc 1 335 3 is_stmt 1 view .LVU193
 853              	.LBB82:
 854              	.LBI82:
 944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 855              		.loc 3 944 27 view .LVU194
 856              	.LBB83:
 857              		.loc 3 946 3 view .LVU195
 858              		.syntax divided
 859              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 860 0008 BFF34F8F 		dsb 0xF
 861              	@ 0 "" 2
 862              		.thumb
 863              		.syntax unified
 864              	.LBE83:
 865              	.LBE82:
 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   __ISB();
 866              		.loc 1 336 3 view .LVU196
 867              	.LBB84:
 868              	.LBI84:
 933:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 869              		.loc 3 933 27 view .LVU197
 870              	.LBB85:
 935:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 871              		.loc 3 935 3 view .LVU198
 872              		.syntax divided
 873              	@ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 874 000c BFF36F8F 		isb 0xF
 875              	@ 0 "" 2
 876              		.thumb
 877              		.syntax unified
 878              	.LBE85:
 879              	.LBE84:
 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 880              		.loc 1 337 1 is_stmt 0 view .LVU199
ARM GAS  /tmp/cc5M7qsZ.s 			page 59


 881              		@ sp needed
 882 0010 7047     		bx	lr
 883              	.L51:
 884 0012 C046     		.align	2
 885              	.L50:
 886 0014 90ED00E0 		.word	-536810096
 887              		.cfi_endproc
 888              	.LFE309:
 890              		.section	.text.HAL_MPU_Disable,"ax",%progbits
 891              		.align	1
 892              		.global	HAL_MPU_Disable
 893              		.syntax unified
 894              		.code	16
 895              		.thumb_func
 896              		.fpu softvfp
 898              	HAL_MPU_Disable:
 899              	.LFB310:
 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Disable the MPU.
 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_MPU_Disable(void)
 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 900              		.loc 1 345 1 is_stmt 1 view -0
 901              		.cfi_startproc
 902              		@ args = 0, pretend = 0, frame = 0
 903              		@ frame_needed = 0, uses_anonymous_args = 0
 904              		@ link register save eliminated.
 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Make sure outstanding transfers are done */
 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   __DMB();
 905              		.loc 1 347 3 view .LVU201
 906              	.LBB86:
 907              	.LBI86:
 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 908              		.loc 3 955 27 view .LVU202
 909              	.LBB87:
 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 910              		.loc 3 957 3 view .LVU203
 911              		.syntax divided
 912              	@ 957 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 913 0000 BFF35F8F 		dmb 0xF
 914              	@ 0 "" 2
 915              		.thumb
 916              		.syntax unified
 917              	.LBE87:
 918              	.LBE86:
ARM GAS  /tmp/cc5M7qsZ.s 			page 60


 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Disable the MPU and clear the control register*/
 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   MPU->CTRL  = 0;
 919              		.loc 1 350 3 view .LVU204
 920              		.loc 1 350 14 is_stmt 0 view .LVU205
 921 0004 014B     		ldr	r3, .L53
 922 0006 0022     		movs	r2, #0
 923 0008 5A60     		str	r2, [r3, #4]
 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 924              		.loc 1 351 1 view .LVU206
 925              		@ sp needed
 926 000a 7047     		bx	lr
 927              	.L54:
 928              		.align	2
 929              	.L53:
 930 000c 90ED00E0 		.word	-536810096
 931              		.cfi_endproc
 932              	.LFE310:
 934              		.section	.text.HAL_MPU_ConfigRegion,"ax",%progbits
 935              		.align	1
 936              		.global	HAL_MPU_ConfigRegion
 937              		.syntax unified
 938              		.code	16
 939              		.thumb_func
 940              		.fpu softvfp
 942              	HAL_MPU_ConfigRegion:
 943              	.LVL46:
 944              	.LFB311:
 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /**
 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @brief  Initialize and configure the Region and the memory to be protected.
 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   *                the initialization and configuration information.
 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   * @retval None
 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   */
 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** {
 945              		.loc 1 361 1 is_stmt 1 view -0
 946              		.cfi_startproc
 947              		@ args = 0, pretend = 0, frame = 0
 948              		@ frame_needed = 0, uses_anonymous_args = 0
 949              		@ link register save eliminated.
 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Check the parameters */
 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
 950              		.loc 1 363 3 view .LVU208
 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
 951              		.loc 1 364 3 view .LVU209
 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   /* Set the Region number */
 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   MPU->RNR = MPU_Init->Number;
 952              		.loc 1 367 3 view .LVU210
 953              		.loc 1 367 22 is_stmt 0 view .LVU211
 954 0000 4278     		ldrb	r2, [r0, #1]
 955              		.loc 1 367 12 view .LVU212
 956 0002 144B     		ldr	r3, .L58
 957 0004 9A60     		str	r2, [r3, #8]
ARM GAS  /tmp/cc5M7qsZ.s 			page 61


 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   if ((MPU_Init->Enable) != 0U)
 958              		.loc 1 369 3 is_stmt 1 view .LVU213
 959              		.loc 1 369 16 is_stmt 0 view .LVU214
 960 0006 0378     		ldrb	r3, [r0]
 961              		.loc 1 369 6 view .LVU215
 962 0008 002B     		cmp	r3, #0
 963 000a 1DD0     		beq	.L56
 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   {
 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     /* Check the parameters */
 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
 964              		.loc 1 372 5 is_stmt 1 view .LVU216
 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
 965              		.loc 1 373 5 view .LVU217
 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
 966              		.loc 1 374 5 view .LVU218
 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
 967              		.loc 1 375 5 view .LVU219
 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
 968              		.loc 1 376 5 view .LVU220
 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
 969              		.loc 1 377 5 view .LVU221
 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
 970              		.loc 1 378 5 view .LVU222
 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
 971              		.loc 1 379 5 view .LVU223
 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** 
 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     MPU->RBAR = MPU_Init->BaseAddress;
 972              		.loc 1 381 5 view .LVU224
 973              		.loc 1 381 15 is_stmt 0 view .LVU225
 974 000c 1149     		ldr	r1, .L58
 975 000e 4368     		ldr	r3, [r0, #4]
 976 0010 CB60     		str	r3, [r1, #12]
 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 977              		.loc 1 382 5 is_stmt 1 view .LVU226
 978              		.loc 1 382 36 is_stmt 0 view .LVU227
 979 0012 037B     		ldrb	r3, [r0, #12]
 980              		.loc 1 382 62 view .LVU228
 981 0014 1B07     		lsls	r3, r3, #28
 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 982              		.loc 1 383 36 view .LVU229
 983 0016 C27A     		ldrb	r2, [r0, #11]
 984              		.loc 1 383 62 view .LVU230
 985 0018 1206     		lsls	r2, r2, #24
 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
 986              		.loc 1 382 84 view .LVU231
 987 001a 1343     		orrs	r3, r2
 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 988              		.loc 1 384 36 view .LVU232
 989 001c 827A     		ldrb	r2, [r0, #10]
 990              		.loc 1 384 62 view .LVU233
 991 001e D204     		lsls	r2, r2, #19
 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 992              		.loc 1 383 84 view .LVU234
 993 0020 1343     		orrs	r3, r2
 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 994              		.loc 1 385 36 view .LVU235
ARM GAS  /tmp/cc5M7qsZ.s 			page 62


 995 0022 427B     		ldrb	r2, [r0, #13]
 996              		.loc 1 385 62 view .LVU236
 997 0024 9204     		lsls	r2, r2, #18
 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
 998              		.loc 1 384 84 view .LVU237
 999 0026 1343     		orrs	r3, r2
 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 1000              		.loc 1 386 36 view .LVU238
 1001 0028 827B     		ldrb	r2, [r0, #14]
 1002              		.loc 1 386 62 view .LVU239
 1003 002a 5204     		lsls	r2, r2, #17
 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
 1004              		.loc 1 385 84 view .LVU240
 1005 002c 1343     		orrs	r3, r2
 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 1006              		.loc 1 387 36 view .LVU241
 1007 002e C27B     		ldrb	r2, [r0, #15]
 1008              		.loc 1 387 62 view .LVU242
 1009 0030 1204     		lsls	r2, r2, #16
 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
 1010              		.loc 1 386 84 view .LVU243
 1011 0032 1343     		orrs	r3, r2
 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 1012              		.loc 1 388 36 view .LVU244
 1013 0034 427A     		ldrb	r2, [r0, #9]
 1014              		.loc 1 388 62 view .LVU245
 1015 0036 1202     		lsls	r2, r2, #8
 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
 1016              		.loc 1 387 84 view .LVU246
 1017 0038 1343     		orrs	r3, r2
 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 1018              		.loc 1 389 36 view .LVU247
 1019 003a 027A     		ldrb	r2, [r0, #8]
 1020              		.loc 1 389 62 view .LVU248
 1021 003c 5200     		lsls	r2, r2, #1
 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
 1022              		.loc 1 388 84 view .LVU249
 1023 003e 1343     		orrs	r3, r2
 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
 1024              		.loc 1 390 36 view .LVU250
 1025 0040 0278     		ldrb	r2, [r0]
 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
 1026              		.loc 1 389 84 view .LVU251
 1027 0042 1343     		orrs	r3, r2
 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
 1028              		.loc 1 382 15 view .LVU252
 1029 0044 0B61     		str	r3, [r1, #16]
 1030              	.L55:
 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   else
 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   {
 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     MPU->RBAR = 0x00U;
 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     MPU->RASR = 0x00U;
 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** }
 1031              		.loc 1 397 1 view .LVU253
 1032              		@ sp needed
ARM GAS  /tmp/cc5M7qsZ.s 			page 63


 1033 0046 7047     		bx	lr
 1034              	.L56:
 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     MPU->RASR = 0x00U;
 1035              		.loc 1 394 5 is_stmt 1 view .LVU254
 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****     MPU->RASR = 0x00U;
 1036              		.loc 1 394 15 is_stmt 0 view .LVU255
 1037 0048 024B     		ldr	r3, .L58
 1038 004a 0022     		movs	r2, #0
 1039 004c DA60     		str	r2, [r3, #12]
 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 1040              		.loc 1 395 5 is_stmt 1 view .LVU256
 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c ****   }
 1041              		.loc 1 395 15 is_stmt 0 view .LVU257
 1042 004e 1A61     		str	r2, [r3, #16]
 1043              		.loc 1 397 1 view .LVU258
 1044 0050 F9E7     		b	.L55
 1045              	.L59:
 1046 0052 C046     		.align	2
 1047              	.L58:
 1048 0054 90ED00E0 		.word	-536810096
 1049              		.cfi_endproc
 1050              	.LFE311:
 1052              		.text
 1053              	.Letext0:
 1054              		.file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h"
 1055              		.file 5 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
 1056              		.file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h"
 1057              		.file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h"
ARM GAS  /tmp/cc5M7qsZ.s 			page 64


DEFINED SYMBOLS
                            *ABS*:0000000000000000 stm32g0xx_hal_cortex.c
     /tmp/cc5M7qsZ.s:16     .text.HAL_NVIC_SetPriority:0000000000000000 $t
     /tmp/cc5M7qsZ.s:24     .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
     /tmp/cc5M7qsZ.s:144    .text.HAL_NVIC_SetPriority:0000000000000058 $d
     /tmp/cc5M7qsZ.s:150    .text.HAL_NVIC_EnableIRQ:0000000000000000 $t
     /tmp/cc5M7qsZ.s:157    .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ
     /tmp/cc5M7qsZ.s:199    .text.HAL_NVIC_EnableIRQ:0000000000000014 $d
     /tmp/cc5M7qsZ.s:204    .text.HAL_NVIC_DisableIRQ:0000000000000000 $t
     /tmp/cc5M7qsZ.s:211    .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ
     /tmp/cc5M7qsZ.s:281    .text.HAL_NVIC_DisableIRQ:000000000000001c $d
     /tmp/cc5M7qsZ.s:286    .text.HAL_NVIC_SystemReset:0000000000000000 $t
     /tmp/cc5M7qsZ.s:293    .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset
     /tmp/cc5M7qsZ.s:353    .text.HAL_NVIC_SystemReset:0000000000000014 $d
     /tmp/cc5M7qsZ.s:361    .text.HAL_SYSTICK_Config:0000000000000000 $t
     /tmp/cc5M7qsZ.s:368    .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config
     /tmp/cc5M7qsZ.s:454    .text.HAL_SYSTICK_Config:0000000000000030 $d
     /tmp/cc5M7qsZ.s:460    .text.HAL_NVIC_GetPriority:0000000000000000 $t
     /tmp/cc5M7qsZ.s:467    .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority
     /tmp/cc5M7qsZ.s:550    .text.HAL_NVIC_GetPriority:0000000000000044 $d
     /tmp/cc5M7qsZ.s:556    .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t
     /tmp/cc5M7qsZ.s:563    .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ
     /tmp/cc5M7qsZ.s:605    .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d
     /tmp/cc5M7qsZ.s:610    .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t
     /tmp/cc5M7qsZ.s:617    .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ
     /tmp/cc5M7qsZ.s:673    .text.HAL_NVIC_GetPendingIRQ:000000000000001c $d
     /tmp/cc5M7qsZ.s:678    .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t
     /tmp/cc5M7qsZ.s:685    .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ
     /tmp/cc5M7qsZ.s:727    .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d
     /tmp/cc5M7qsZ.s:732    .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t
     /tmp/cc5M7qsZ.s:739    .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig
     /tmp/cc5M7qsZ.s:775    .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d
     /tmp/cc5M7qsZ.s:780    .text.HAL_SYSTICK_Callback:0000000000000000 $t
     /tmp/cc5M7qsZ.s:787    .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback
     /tmp/cc5M7qsZ.s:801    .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t
     /tmp/cc5M7qsZ.s:808    .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler
     /tmp/cc5M7qsZ.s:829    .text.HAL_MPU_Enable:0000000000000000 $t
     /tmp/cc5M7qsZ.s:836    .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable
     /tmp/cc5M7qsZ.s:886    .text.HAL_MPU_Enable:0000000000000014 $d
     /tmp/cc5M7qsZ.s:891    .text.HAL_MPU_Disable:0000000000000000 $t
     /tmp/cc5M7qsZ.s:898    .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable
     /tmp/cc5M7qsZ.s:930    .text.HAL_MPU_Disable:000000000000000c $d
     /tmp/cc5M7qsZ.s:935    .text.HAL_MPU_ConfigRegion:0000000000000000 $t
     /tmp/cc5M7qsZ.s:942    .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion
     /tmp/cc5M7qsZ.s:1048   .text.HAL_MPU_ConfigRegion:0000000000000054 $d

NO UNDEFINED SYMBOLS
