ARM GAS  /tmp/ccacA7RR.s 			page 1


   1              		.cpu cortex-m0plus
   2              		.eabi_attribute 20, 1
   3              		.eabi_attribute 21, 1
   4              		.eabi_attribute 23, 3
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 1
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"stm32g0xx_it.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.section	.text.NMI_Handler,"ax",%progbits
  16              		.align	1
  17              		.global	NMI_Handler
  18              		.arch armv6s-m
  19              		.syntax unified
  20              		.code	16
  21              		.thumb_func
  22              		.fpu softvfp
  24              	NMI_Handler:
  25              	.LFB297:
  26              		.file 1 "Core/Src/stm32g0xx_it.c"
   1:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN Header */
   2:Core/Src/stm32g0xx_it.c **** /**
   3:Core/Src/stm32g0xx_it.c ****   ******************************************************************************
   4:Core/Src/stm32g0xx_it.c ****   * @file    stm32g0xx_it.c
   5:Core/Src/stm32g0xx_it.c ****   * @brief   Interrupt Service Routines.
   6:Core/Src/stm32g0xx_it.c ****   ******************************************************************************
   7:Core/Src/stm32g0xx_it.c ****   * @attention
   8:Core/Src/stm32g0xx_it.c ****   *
   9:Core/Src/stm32g0xx_it.c ****   * Copyright (c) 2021 STMicroelectronics.
  10:Core/Src/stm32g0xx_it.c ****   * All rights reserved.
  11:Core/Src/stm32g0xx_it.c ****   *
  12:Core/Src/stm32g0xx_it.c ****   * This software is licensed under terms that can be found in the LICENSE file
  13:Core/Src/stm32g0xx_it.c ****   * in the root directory of this software component.
  14:Core/Src/stm32g0xx_it.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  15:Core/Src/stm32g0xx_it.c ****   *
  16:Core/Src/stm32g0xx_it.c ****   ******************************************************************************
  17:Core/Src/stm32g0xx_it.c ****   */
  18:Core/Src/stm32g0xx_it.c **** /* USER CODE END Header */
  19:Core/Src/stm32g0xx_it.c **** 
  20:Core/Src/stm32g0xx_it.c **** /* Includes ------------------------------------------------------------------*/
  21:Core/Src/stm32g0xx_it.c **** #include "main.h"
  22:Core/Src/stm32g0xx_it.c **** #include "stm32g0xx_it.h"
  23:Core/Src/stm32g0xx_it.c **** /* Private includes ----------------------------------------------------------*/
  24:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN Includes */
  25:Core/Src/stm32g0xx_it.c **** /* USER CODE END Includes */
  26:Core/Src/stm32g0xx_it.c **** 
  27:Core/Src/stm32g0xx_it.c **** /* Private typedef -----------------------------------------------------------*/
  28:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN TD */
  29:Core/Src/stm32g0xx_it.c **** 
  30:Core/Src/stm32g0xx_it.c **** /* USER CODE END TD */
  31:Core/Src/stm32g0xx_it.c **** 
  32:Core/Src/stm32g0xx_it.c **** /* Private define ------------------------------------------------------------*/
ARM GAS  /tmp/ccacA7RR.s 			page 2


  33:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PD */
  34:Core/Src/stm32g0xx_it.c **** 
  35:Core/Src/stm32g0xx_it.c **** /* USER CODE END PD */
  36:Core/Src/stm32g0xx_it.c **** 
  37:Core/Src/stm32g0xx_it.c **** /* Private macro -------------------------------------------------------------*/
  38:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PM */
  39:Core/Src/stm32g0xx_it.c **** 
  40:Core/Src/stm32g0xx_it.c **** /* USER CODE END PM */
  41:Core/Src/stm32g0xx_it.c **** 
  42:Core/Src/stm32g0xx_it.c **** /* Private variables ---------------------------------------------------------*/
  43:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PV */
  44:Core/Src/stm32g0xx_it.c **** 
  45:Core/Src/stm32g0xx_it.c **** /* USER CODE END PV */
  46:Core/Src/stm32g0xx_it.c **** 
  47:Core/Src/stm32g0xx_it.c **** /* Private function prototypes -----------------------------------------------*/
  48:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PFP */
  49:Core/Src/stm32g0xx_it.c **** 
  50:Core/Src/stm32g0xx_it.c **** /* USER CODE END PFP */
  51:Core/Src/stm32g0xx_it.c **** 
  52:Core/Src/stm32g0xx_it.c **** /* Private user code ---------------------------------------------------------*/
  53:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN 0 */
  54:Core/Src/stm32g0xx_it.c **** 
  55:Core/Src/stm32g0xx_it.c **** /* USER CODE END 0 */
  56:Core/Src/stm32g0xx_it.c **** 
  57:Core/Src/stm32g0xx_it.c **** /* External variables --------------------------------------------------------*/
  58:Core/Src/stm32g0xx_it.c **** 
  59:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN EV */
  60:Core/Src/stm32g0xx_it.c **** 
  61:Core/Src/stm32g0xx_it.c **** /* USER CODE END EV */
  62:Core/Src/stm32g0xx_it.c **** 
  63:Core/Src/stm32g0xx_it.c **** /******************************************************************************/
  64:Core/Src/stm32g0xx_it.c **** /*           Cortex-M0+ Processor Interruption and Exception Handlers          */
  65:Core/Src/stm32g0xx_it.c **** /******************************************************************************/
  66:Core/Src/stm32g0xx_it.c **** /**
  67:Core/Src/stm32g0xx_it.c ****   * @brief This function handles Non maskable interrupt.
  68:Core/Src/stm32g0xx_it.c ****   */
  69:Core/Src/stm32g0xx_it.c **** void NMI_Handler(void)
  70:Core/Src/stm32g0xx_it.c **** {
  27              		.loc 1 70 1 view -0
  28              		.cfi_startproc
  29              		@ Volatile: function does not return.
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		@ link register save eliminated.
  33              	.L2:
  71:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
  72:Core/Src/stm32g0xx_it.c **** 
  73:Core/Src/stm32g0xx_it.c ****   /* USER CODE END NonMaskableInt_IRQn 0 */
  74:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  75:Core/Src/stm32g0xx_it.c ****   while (1)
  34              		.loc 1 75 3 discriminator 1 view .LVU1
  76:Core/Src/stm32g0xx_it.c ****   {
  77:Core/Src/stm32g0xx_it.c ****   }
  35              		.loc 1 77 3 discriminator 1 view .LVU2
  75:Core/Src/stm32g0xx_it.c ****   {
  36              		.loc 1 75 9 discriminator 1 view .LVU3
  37 0000 FEE7     		b	.L2
ARM GAS  /tmp/ccacA7RR.s 			page 3


  38              		.cfi_endproc
  39              	.LFE297:
  41              		.section	.text.HardFault_Handler,"ax",%progbits
  42              		.align	1
  43              		.global	HardFault_Handler
  44              		.syntax unified
  45              		.code	16
  46              		.thumb_func
  47              		.fpu softvfp
  49              	HardFault_Handler:
  50              	.LFB298:
  78:Core/Src/stm32g0xx_it.c ****   /* USER CODE END NonMaskableInt_IRQn 1 */
  79:Core/Src/stm32g0xx_it.c **** }
  80:Core/Src/stm32g0xx_it.c **** 
  81:Core/Src/stm32g0xx_it.c **** /**
  82:Core/Src/stm32g0xx_it.c ****   * @brief This function handles Hard fault interrupt.
  83:Core/Src/stm32g0xx_it.c ****   */
  84:Core/Src/stm32g0xx_it.c **** void HardFault_Handler(void)
  85:Core/Src/stm32g0xx_it.c **** {
  51              		.loc 1 85 1 view -0
  52              		.cfi_startproc
  53              		@ Volatile: function does not return.
  54              		@ args = 0, pretend = 0, frame = 0
  55              		@ frame_needed = 0, uses_anonymous_args = 0
  56              		@ link register save eliminated.
  57              	.L4:
  86:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN HardFault_IRQn 0 */
  87:Core/Src/stm32g0xx_it.c **** 
  88:Core/Src/stm32g0xx_it.c ****   /* USER CODE END HardFault_IRQn 0 */
  89:Core/Src/stm32g0xx_it.c ****   while (1)
  58              		.loc 1 89 3 discriminator 1 view .LVU5
  90:Core/Src/stm32g0xx_it.c ****   {
  91:Core/Src/stm32g0xx_it.c ****     /* USER CODE BEGIN W1_HardFault_IRQn 0 */
  92:Core/Src/stm32g0xx_it.c ****     /* USER CODE END W1_HardFault_IRQn 0 */
  93:Core/Src/stm32g0xx_it.c ****   }
  59              		.loc 1 93 3 discriminator 1 view .LVU6
  89:Core/Src/stm32g0xx_it.c ****   {
  60              		.loc 1 89 9 discriminator 1 view .LVU7
  61 0000 FEE7     		b	.L4
  62              		.cfi_endproc
  63              	.LFE298:
  65              		.section	.text.SVC_Handler,"ax",%progbits
  66              		.align	1
  67              		.global	SVC_Handler
  68              		.syntax unified
  69              		.code	16
  70              		.thumb_func
  71              		.fpu softvfp
  73              	SVC_Handler:
  74              	.LFB299:
  94:Core/Src/stm32g0xx_it.c **** }
  95:Core/Src/stm32g0xx_it.c **** 
  96:Core/Src/stm32g0xx_it.c **** /**
  97:Core/Src/stm32g0xx_it.c ****   * @brief This function handles System service call via SWI instruction.
  98:Core/Src/stm32g0xx_it.c ****   */
  99:Core/Src/stm32g0xx_it.c **** void SVC_Handler(void)
 100:Core/Src/stm32g0xx_it.c **** {
ARM GAS  /tmp/ccacA7RR.s 			page 4


  75              		.loc 1 100 1 view -0
  76              		.cfi_startproc
  77              		@ args = 0, pretend = 0, frame = 0
  78              		@ frame_needed = 0, uses_anonymous_args = 0
  79              		@ link register save eliminated.
 101:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN SVC_IRQn 0 */
 102:Core/Src/stm32g0xx_it.c **** 
 103:Core/Src/stm32g0xx_it.c ****   /* USER CODE END SVC_IRQn 0 */
 104:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN SVC_IRQn 1 */
 105:Core/Src/stm32g0xx_it.c **** 
 106:Core/Src/stm32g0xx_it.c ****   /* USER CODE END SVC_IRQn 1 */
 107:Core/Src/stm32g0xx_it.c **** }
  80              		.loc 1 107 1 view .LVU9
  81              		@ sp needed
  82 0000 7047     		bx	lr
  83              		.cfi_endproc
  84              	.LFE299:
  86              		.section	.text.PendSV_Handler,"ax",%progbits
  87              		.align	1
  88              		.global	PendSV_Handler
  89              		.syntax unified
  90              		.code	16
  91              		.thumb_func
  92              		.fpu softvfp
  94              	PendSV_Handler:
  95              	.LFB300:
 108:Core/Src/stm32g0xx_it.c **** 
 109:Core/Src/stm32g0xx_it.c **** /**
 110:Core/Src/stm32g0xx_it.c ****   * @brief This function handles Pendable request for system service.
 111:Core/Src/stm32g0xx_it.c ****   */
 112:Core/Src/stm32g0xx_it.c **** void PendSV_Handler(void)
 113:Core/Src/stm32g0xx_it.c **** {
  96              		.loc 1 113 1 view -0
  97              		.cfi_startproc
  98              		@ args = 0, pretend = 0, frame = 0
  99              		@ frame_needed = 0, uses_anonymous_args = 0
 100              		@ link register save eliminated.
 114:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN PendSV_IRQn 0 */
 115:Core/Src/stm32g0xx_it.c **** 
 116:Core/Src/stm32g0xx_it.c ****   /* USER CODE END PendSV_IRQn 0 */
 117:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN PendSV_IRQn 1 */
 118:Core/Src/stm32g0xx_it.c **** 
 119:Core/Src/stm32g0xx_it.c ****   /* USER CODE END PendSV_IRQn 1 */
 120:Core/Src/stm32g0xx_it.c **** }
 101              		.loc 1 120 1 view .LVU11
 102              		@ sp needed
 103 0000 7047     		bx	lr
 104              		.cfi_endproc
 105              	.LFE300:
 107              		.section	.text.SysTick_Handler,"ax",%progbits
 108              		.align	1
 109              		.global	SysTick_Handler
 110              		.syntax unified
 111              		.code	16
 112              		.thumb_func
 113              		.fpu softvfp
 115              	SysTick_Handler:
ARM GAS  /tmp/ccacA7RR.s 			page 5


 116              	.LFB301:
 121:Core/Src/stm32g0xx_it.c **** 
 122:Core/Src/stm32g0xx_it.c **** /**
 123:Core/Src/stm32g0xx_it.c ****   * @brief This function handles System tick timer.
 124:Core/Src/stm32g0xx_it.c ****   */
 125:Core/Src/stm32g0xx_it.c **** void SysTick_Handler(void)
 126:Core/Src/stm32g0xx_it.c **** {
 117              		.loc 1 126 1 view -0
 118              		.cfi_startproc
 119              		@ args = 0, pretend = 0, frame = 0
 120              		@ frame_needed = 0, uses_anonymous_args = 0
 121 0000 10B5     		push	{r4, lr}
 122              	.LCFI0:
 123              		.cfi_def_cfa_offset 8
 124              		.cfi_offset 4, -8
 125              		.cfi_offset 14, -4
 127:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN SysTick_IRQn 0 */
 128:Core/Src/stm32g0xx_it.c **** 
 129:Core/Src/stm32g0xx_it.c ****   /* USER CODE END SysTick_IRQn 0 */
 130:Core/Src/stm32g0xx_it.c ****   HAL_IncTick();
 126              		.loc 1 130 3 view .LVU13
 127 0002 FFF7FEFF 		bl	HAL_IncTick
 128              	.LVL0:
 131:Core/Src/stm32g0xx_it.c ****   /* USER CODE BEGIN SysTick_IRQn 1 */
 132:Core/Src/stm32g0xx_it.c **** 
 133:Core/Src/stm32g0xx_it.c ****   /* USER CODE END SysTick_IRQn 1 */
 134:Core/Src/stm32g0xx_it.c **** }
 129              		.loc 1 134 1 is_stmt 0 view .LVU14
 130              		@ sp needed
 131 0006 10BD     		pop	{r4, pc}
 132              		.cfi_endproc
 133              	.LFE301:
 135              		.text
 136              	.Letext0:
 137              		.file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
 138              		.file 3 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h"
 139              		.file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h"
ARM GAS  /tmp/ccacA7RR.s 			page 6


DEFINED SYMBOLS
                            *ABS*:0000000000000000 stm32g0xx_it.c
     /tmp/ccacA7RR.s:16     .text.NMI_Handler:0000000000000000 $t
     /tmp/ccacA7RR.s:24     .text.NMI_Handler:0000000000000000 NMI_Handler
     /tmp/ccacA7RR.s:42     .text.HardFault_Handler:0000000000000000 $t
     /tmp/ccacA7RR.s:49     .text.HardFault_Handler:0000000000000000 HardFault_Handler
     /tmp/ccacA7RR.s:66     .text.SVC_Handler:0000000000000000 $t
     /tmp/ccacA7RR.s:73     .text.SVC_Handler:0000000000000000 SVC_Handler
     /tmp/ccacA7RR.s:87     .text.PendSV_Handler:0000000000000000 $t
     /tmp/ccacA7RR.s:94     .text.PendSV_Handler:0000000000000000 PendSV_Handler
     /tmp/ccacA7RR.s:108    .text.SysTick_Handler:0000000000000000 $t
     /tmp/ccacA7RR.s:115    .text.SysTick_Handler:0000000000000000 SysTick_Handler

UNDEFINED SYMBOLS
HAL_IncTick
